#ifndef __INC_HALMAC_REG_8733B_H
#define __INC_HALMAC_REG_8733B_H

#define REG_SYS_ISO_CTRL_8733B 0x0000
#define REG_SYS_FUNC_EN_8733B 0x0002
#define REG_SYS_PW_CTRL_8733B 0x0004
#define REG_SYS_CLK_CTRL_8733B 0x0008
#define REG_SYS_EEPROM_CTRL_8733B 0x000A
#define REG_EE_VPD_8733B 0x000C
#define REG_SYS_SWR_CTRL1_8733B 0x0010
#define REG_FW_SECURE_CTRL_CFG_8733B 0x0014
#define REG_SYS_SWR_OCP_CFG_8733B 0x0018
#define REG_REG_ACCESS_CTRL_8733B 0x001C
#define REG_RF_CTRL_8733B 0x001F
#define REG_SPS_LDO_VOLT_CTRL_8733B 0x0020
#define REG_SPS_LDO_VOLT_CTRL1_8733B 0x0024
#define REG_AIP_POW_CTRL_8733B 0x0028
#define REG_LDO_CTRL0_8733B 0x002C
#define REG_EFUSE_CTRL_8733B 0x0030
#define REG_LDO_EFUSE_CTRL_8733B 0x0034
#define REG_PWR_OPTION_CTRL_8733B 0x0038
#define REG_CAL_TIMER_8733B 0x003C
#define REG_ACLK_MON_8733B 0x003E
#define REG_GPIO_MUXCFG_8733B 0x0040
#define REG_GPIO_PIN_CTRL_8733B 0x0044
#define REG_GPIO_INTM_8733B 0x0048
#define REG_LED_CFG_8733B 0x004C
#define REG_FSIMR_8733B 0x0050
#define REG_FSISR_8733B 0x0054
#define REG_HSIMR_8733B 0x0058
#define REG_HSISR_8733B 0x005C
#define REG_GPIO_EXT_CTRL_8733B 0x0060
#define REG_PAD_CTRL1_8733B 0x0064
#define REG_WL_BT_PWR_CTRL_8733B 0x0068
#define REG_BT_SCAN_MISC_8733B 0x006C
#define REG_SYS_SDIO_CTRL_8733B 0x0070
#define REG_HCI_OPT_CTRL_8733B 0x0074
#define REG_EFUSE_FW_SECURE_CTRL_8733B 0x0078
#define REG_LDO_SWR_CTRL_8733B 0x007C
#define REG_MCUFW_CTRL_8733B 0x0080
#define REG_MCU_TST_CFG_8733B 0x0084
#define REG_HMEBOX_E0_E1_8733B 0x0088
#define REG_HMEBOX_E2_E3_8733B 0x008C
#define REG_WLLPS_CTRL_8733B 0x0090
#define REG_MEM_POW_CTRL_8733B 0x0094
#define REG_GPIO_DEBOUNCE_CTRL_8733B 0x0098
#define REG_RPWM2_8733B 0x009C
#define REG_SYSON_FSM_MON_8733B 0x00A0
#define REG_EXT_HCI_OPT_8733B 0x00A4
#define REG_PMC_DBG_CTRL1_8733B 0x00A8
#define REG_SCOREBOARD_CTRL_8733B 0x00AC
#define REG_HIMR0_8733B 0x00B0
#define REG_HISR0_8733B 0x00B4
#define REG_HIMR1_8733B 0x00B8
#define REG_HISR1_8733B 0x00BC
#define REG_DBG_PORT_SEL_8733B 0x00C0
#define REG_EEPROM_PIN_CTRL_8733B 0x00C4
#define REG_PMC_DBG_CTRL2_8733B 0x00CC
#define REG_BIST_CTRL_8733B 0x00D0
#define REG_BIST_RPT_8733B 0x00D4
#define REG_MEM_CTRL_8733B 0x00D8
#define REG_SCAN_CTRL_8733B 0x00DC
#define REG_USB_SIE_INTF_8733B 0x00E0
#define REG_MAC_CLK_PHS_CTRL_8733B 0x00E4
#define REG_XTAL_AAC_CFG_8733B 0x00EC
#define REG_SYS_CFG1_8733B 0x00F0
#define REG_SYS_STATUS1_8733B 0x00F4
#define REG_SYS_STATUS2_8733B 0x00F8
#define REG_SYS_CFG2_8733B 0x00FC
#define REG_EXT_SYS_FUNC_EN_8733B 0x1000
#define REG_EXT_SYS_PW_CTRL_8733B 0x1004
#define REG_EXT_SYS_CLK_CTRL_8733B 0x1008
#define REG_ANAPARSW_MAC_ON_0_8733B 0x1010
#define REG_ANAPARSW_MAC_ON_1_8733B 0x1014
#define REG_ANAPARSW_MAC_0_8733B 0x1018
#define REG_ANAPARSW_MAC_1_8733B 0x101C
#define REG_ANAPARSW_MAC_2_8733B 0x1020
#define REG_ANAPARSW_MAC_3_8733B 0x1024
#define REG_ANAPARSW_MAC_4_8733B 0x1028
#define REG_ANAPARSW_MAC_5_8733B 0x102C
#define REG_ANAPARSW_MAC_6_8733B 0x1030
#define REG_ANAPARSW_MAC_7_8733B 0x1034
#define REG_ANAPARSW_MAC_8_8733B 0x1038
#define REG_WL_ANAPAR_XTAL_ON_0_8733B 0x103C
#define REG_WL_ANAPAR_XTAL_ON_1_8733B 0x1040
#define REG_WL_ANAPAR_XTAL_ON_2_8733B 0x1044
#define REG_ANAPAR_LDO_0_8733B 0x1048
#define REG_ANAPAR_LDO_1_8733B 0x104C
#define REG_ANAPAR_MODE_DEC_ON_8733B 0x1064
#define REG_RO_XTAL_MODE_DEC_8733B 0x1068
#define REG_WL_ANAPAR_XTAL_OFF0_8733B 0x106C
#define REG_WL_ANAPAR_XTAL_OFF1_8733B 0x1070
#define REG_ANAPAR_XTAL_AAC_OFF0_8733B 0x1074
#define REG_ANAPAR_XTAL_AAC_OFF1_8733B 0x1078
#define REG_XAAC_READ_ONLY_DATA_8733B 0x107C
#define REG_ANAPAR_PDCK_OFF_8733B 0x1080
#define REG__PDCK_READ_ONLY_DATA_8733B 0x1084
#define REG_ANAPARSW_MAC_OFF0_8733B 0x1088
#define REG_ANAPARSW_MAC_OFF1_8733B 0x108C
#define REG_FW_DBG0_8733B 0x1090
#define REG_FW_DBG1_8733B 0x1094
#define REG_FW_DBG2_8733B 0x1098
#define REG_FW_DBG3_8733B 0x109C
#define REG_FW_DBG4_8733B 0x10A0
#define REG_FW_DBG5_8733B 0x10A4
#define REG_FW_DBG6_8733B 0x10A8
#define REG_FW_DBG7_8733B 0x10AC
#define REG_PAD_CTRL_8733B 0x10C0
#define REG_GPIO_0_8733B 0x10D0
#define REG_GPIO_1_8733B 0x10D4
#define REG_GPIO_2_8733B 0x10D8
#define REG_GPIO_3_8733B 0x10DC
#define REG_GPIO_4_8733B 0x10E0
#define REG_GPIO_5_8733B 0x10E4
#define REG_CR_8733B 0x0100
#define REG_PG_SIZE_8733B 0x0104
#define REG_TSF_CLK_STATE_8733B 0x0108
#define REG_TXDMA_PQ_MAP_8733B 0x010C
#define REG_TRXFF_BNDY_8733B 0x0114
#define REG_PTA_I2C_MBOX_8733B 0x0118
#define REG_RXFF_PTR_8733B 0x011C
#define REG_FE1IMR_8733B 0x0120
#define REG_FE1ISR_8733B 0x0124
#define REG_HEISR_HOST_EXTEND_INTERRUPT_MASK_REGISTER_8733B 0x0128
#define REG_HEISR_HOST_EXTEND_INTERRUPT_STATUS_REGISTER_8733B 0x012C
#define REG_FWIMR_8733B 0x0130
#define REG_FWISR_8733B 0x0134
#define REG_FTIMR_8733B 0x0138
#define REG_FTISR_8733B 0x013C
#define REG_PKTBUF_DBG_CTRL_8733B 0x0140
#define REG_PKTBUF_DBG_DATA_L_8733B 0x0144
#define REG_PKTBUF_DBG_DATA_H_8733B 0x0148
#define REG_CPWM2_8733B 0x014C
#define REG_TC0_CTRL_8733B 0x0150
#define REG_TC1_CTRL_8733B 0x0154
#define REG_TC2_CTRL_8733B 0x0158
#define REG_TC3_CTRL_8733B 0x015C
#define REG_TC4_CTRL_8733B 0x0160
#define REG_TCUNIT_BASE_8733B 0x0164
#define REG_TC5_CTRL_8733B 0x0168
#define REG_TC6_CTRL_8733B 0x016C
#define REG_MBIST_DRF_FAIL_V1_8733B 0x0170
#define REG_MBIST_START_PAUSE_V1_8733B 0x0174
#define REG_MBIST_DONE_V1_8733B 0x0178
#define REG_MBIST_FAIL_NRML_V1_8733B 0x017C
#define REG_AES_DECRPT_DATA_8733B 0x0180
#define REG_AES_DECRPT_CFG_8733B 0x0184
#define REG_MACCLKFRQ_8733B 0x018C
#define REG_TMETER_8733B 0x0190
#define REG_OSC_32K_CTRL_8733B 0x0194
#define REG_32K_CAL_REG0_8733B 0x0198
#define REG_32K_XTAL_CR_8733B 0x019C
#define REG_C2HEVT_8733B 0x01A0
#define REG_C2HEVT_1_8733B 0x01A4
#define REG_C2HEVT_2_8733B 0x01A8
#define REG_C2HEVT_3_8733B 0x01AC
#define REG_HW_IOE_CR_8733B 0x01B0
#define REG_BB_RFC_ATR_8733B 0x01B4
#define REG_SW_DEFINED_PAGE1_8733B 0x01B8
#define REG_SW_DEFINED_PAGE2_8733B 0x01BC
#define REG_MCUTST_I_8733B 0x01C0
#define REG_MCUTST_II_8733B 0x01C4
#define REG_FMETHR_8733B 0x01C8
#define REG_HMETFR_8733B 0x01CC
#define REG_HMEBOX0_8733B 0x01D0
#define REG_HMEBOX1_8733B 0x01D4
#define REG_HMEBOX2_8733B 0x01D8
#define REG_HMEBOX3_8733B 0x01DC
#define REG_LLT_IND_ACCESS_8733B 0x01E0
#define REG_GENTST_8733B 0x01E4
#define REG_BB_ACCESS_CTRL_8733B 0x01E8
#define REG_BB_ACCESS_DATA_8733B 0x01EC
#define REG_HMEBOX_E0_8733B 0x01F0
#define REG_HMEBOX_E1_8733B 0x01F4
#define REG_HMEBOX_E2_8733B 0x01F8
#define REG_HMEBOX_E3_8733B 0x01FC
#define REG_CR_EXT_8733B 0x1100
#define REG_XTAL_CLK_8733B 0x1104
#define REG_LX_TO_OC_8733B 0x1108
#define REG_FE2IMR_8733B 0x1120
#define REG_FE2ISR_8733B 0x1124
#define REG_FE3IMR_8733B 0x1128
#define REG_FE3ISR_8733B 0x112C
#define REG_FE4IMR_8733B 0x1130
#define REG_FE4ISR_8733B 0x1134
#define REG_FT1IMR_8733B 0x1138
#define REG_FT1ISR_8733B 0x113C
#define REG_MBIST_DONE_8733B 0x1140
#define REG_MBIST_FAIL_NRML_L_8733B 0x1144
#define REG_MBIST_FAIL_NRML_H_8733B 0x114C
#define REG_MBIST_DRF_FAIL_L_8733B 0x114C
#define REG_MBIST_DRF_FAIL_H_8733B 0x1154
#define REG_MBIST_START_PAUSE_8733B 0x1154
#define REG_MBIST_RPT_8733B 0x1158
#define REG_FE5IMR_8733B 0x1168
#define REG_FE5ISR_8733B 0x116C
#define REG_FE6IMR_8733B 0x1170
#define REG_FE6ISR_8733B 0x1174
#define REG_BT_MBIST_DONE_8733B 0x1180
#define REG_BT_MBIST_FAIL_8733B 0x1184
#define REG_BT_MBIST_START_PAUSE_8733B 0x1188
#define REG_BT_MBIST_START_PAUSE1_8733B 0x118C
#define REG_FT2IMR_8733B 0x11E0
#define REG_FT2ISR_8733B 0x11E4
#define REG_MSG2_8733B 0x11F0
#define REG_MSG3_8733B 0x11F4
#define REG_MSG4_8733B 0x11F8
#define REG_MSG5_8733B 0x11FC
#define REG_RQPN_CTRL_HLPQ_8733B 0x0200
#define REG_FIFOPAGE_INFO_8733B 0x0204
#define REG_DWBCN0_CTRL_8733B 0x0208
#define REG_TXDMA_OFFSET_CHK_8733B 0x020C
#define REG_TXDMA_STATUS_8733B 0x0210
#define REG_RQPN_NPQ_8733B 0x0214
#define REG_TQPNT1_8733B 0x0218
#define REG_TQPNT2_8733B 0x021C
#define REG_TDE_DEBUG_8733B 0x0220
#define REG_AUTO_LLT_8733B 0x0224
#define REG_DWBCN1_CTRL_8733B 0x0228
#define REG_TX_ALIGNMENT_CTRL_8733B 0x022C
#define REG_RQPN_EXQ1_EXQ2_8733B 0x0230
#define REG_TQPNT3_V1_8733B 0x0234
#define REG_H2C_HEAD_8733B 0x0244
#define REG_H2C_TAIL_8733B 0x0248
#define REG_H2C_READ_ADDR_8733B 0x024C
#define REG_H2C_WR_ADDR_8733B 0x0250
#define REG_H2C_INFO_8733B 0x0254
#define REG_RXDMA_AGG_PG_TH_8733B 0x0280
#define REG_RXPKT_NUM_8733B 0x0284
#define REG_RXDMA_STATUS_8733B 0x0288
#define REG_RXDMA_DPR_8733B 0x028C
#define REG_RXDMA_MODE_8733B 0x0290
#define REG_C2H_PKT_8733B 0x0294
#define REG_DDMA_CH0SA_8733B 0x1200
#define REG_DDMA_CH0DA_8733B 0x1204
#define REG_DDMA_CH0CTRL_8733B 0x1208
#define REG_DDMA_CH1SA_8733B 0x1210
#define REG_DDMA_CH1DA_8733B 0x1214
#define REG_DDMA_CH1CTRL_8733B 0x1218
#define REG_DDMA_CH2SA_8733B 0x1220
#define REG_DDMA_CH2DA_8733B 0x1224
#define REG_DDMA_CH2CTRL_8733B 0x1228
#define REG_DDMA_CH3SA_8733B 0x1230
#define REG_DDMA_CH3DA_8733B 0x1234
#define REG_DDMA_CH3CTRL_8733B 0x1238
#define REG_DDMA_CH4SA_8733B 0x1240
#define REG_DDMA_CH4DA_8733B 0x1244
#define REG_DDMA_CH4CTRL_8733B 0x1248
#define REG_DDMA_CH5SA_8733B 0x1250
#define REG_DDMA_CH5DA_8733B 0x1254
#define REG_DDMA_CH5CTRL_8733B 0x1258
#define REG_DDMA_INT_MSK_8733B 0x12E0
#define REG_DDMA_CHSTATUS_8733B 0x12E8
#define REG_DDMA_CHKSUM_8733B 0x12F0
#define REG_DDMA_MONITOR_8733B 0x12FC
#define REG_Q0_INFO_8733B 0x0400
#define REG_Q1_INFO_8733B 0x0404
#define REG_Q2_INFO_8733B 0x0408
#define REG_Q3_INFO_8733B 0x040C
#define REG_MGQ_INFO_8733B 0x0410
#define REG_HIQ_INFO_8733B 0x0414
#define REG_BCNQ_INFO_8733B 0x0418
#define REG_TXPKT_EMPTY_8733B 0x041A
#define REG_CPU_MGQ_INFO_8733B 0x041C
#define REG_FWHW_TXQ_CTRL_8733B 0x0420
#define REG_HWSEQ_CTRL_8733B 0x0423
#define REG_BCNQ_BDNY_8733B 0x0424
#define REG_LIFETIME_EN_8733B 0x0426
#define REG_FW_FREE_TAIL_8733B 0x0427
#define REG_SPEC_SIFS_8733B 0x0428
#define REG_RETRY_LIMIT_8733B 0x042A
#define REG_TXBF_CTRL_8733B 0x042C
#define REG_DARFRC_8733B 0x0430
#define REG_DARFRCH_8733B 0x0434
#define REG_RARFRC_8733B 0x0438
#define REG_RARFRCH_8733B 0x043C
#define REG_RRSR_8733B 0x0440
#define REG_ARFRL0_8733B 0x0444
#define REG_ARFRH0_8733B 0x0448
#define REG_ARFR1_V1_8733B 0x044C
#define REG_ARFRH1_V1_8733B 0x0450
#define REG_CCK_CHECK_8733B 0x0454
#define REG_BCNQ2_BDNY_8733B 0x0455
#define REG_AMPDU_MAX_TIME_8733B 0x0456
#define REG_BCNQ1_BDNY_8733B 0x0457
#define REG_AMPDU_MAX_LENGTH_8733B 0x0458
#define REG_ACQ_STOP_8733B 0x045C
#define REG_WMAC_LBK_BUF_HD_8733B 0x045D
#define REG_TX_HANG_CTRL_8733B 0x045E
#define REG_NDPA_OPT_CTRL_8733B 0x045F
#define REG_RD_RESP_PKT_TH_8733B 0x0463
#define REG_CMDQ_INFO_8733B 0x0464
#define REG_Q4_INFO_8733B 0x0468
#define REG_Q5_INFO_8733B 0x046C
#define REG_Q6_INFO_8733B 0x0470
#define REG_Q7_INFO_8733B 0x0474
#define REG_TXRPT_CTRL_8733B 0x047C
#define REG_INIRTS_RATE_SEL_8733B 0x0480
#define REG_BASIC_CFEND_RATE_8733B 0x0481
#define REG_STBC_CFEND_RATE_8733B 0x0482
#define REG_DATA_SC_8733B 0x0483
#define REG_MACID_SLEEP3_8733B 0x0484
#define REG_MACID_SLEEP1_8733B 0x0488
#define REG_ARFR2_V1_8733B 0x048C
#define REG_ARFRH2_V1_H_8733B 0x0490
#define REG_ARFR3_V1_8733B 0x0494
#define REG_ARFRH3_V1_H_8733B 0x0498
#define REG_ARFR4_8733B 0x049C
#define REG_ARFRH4_H_8733B 0x04A0
#define REG_ARFR5_8733B 0x04A4
#define REG_ARFRH5_8733B 0x04A8
#define REG_TXRPT_START_OFFSET_8733B 0x04AC
#define REG_POWER_STAGE1_8733B 0x04B4
#define REG_POWER_STAGE2_8733B 0x04B8
#define REG_SW_AMPDU_BURST_MODE_CTRL_8733B 0x04BC
#define REG_PKT_LIFE_TIME_8733B 0x04C0
#define REG_STBC_SETTING_8733B 0x04C4
#define REG_STBC_SETTING2_8733B 0x04C5
#define REG_QUEUE_CTRL_8733B 0x04C6
#define REG_SINGLE_AMPDU_CTRL_8733B 0x04C7
#define REG_PROT_MODE_CTRL_8733B 0x04C8
#define REG_BAR_MODE_CTRL_8733B 0x04CC
#define REG_MACID_SLEEP2_8733B 0x04D0
#define REG_MACID_SLEEP_8733B 0x04D4
#define REG_HW_SEQ0_8733B 0x04D8
#define REG_HW_SEQ1_8733B 0x04DA
#define REG_HW_SEQ2_8733B 0x04DC
#define REG_HW_SEQ3_8733B 0x04DE
#define REG_NULL_PKT_STATUS_8733B 0x04E0
#define REG_PTCL_ERR_STATUS_8733B 0x04E2
#define REG_PTCL_PKT_NUM_8733B 0x04E3
#define REG_DROP_FUN_8733B 0x04E4
#define REG_PRECNT_CTRL_8733B 0x04E5
#define REG_BT_POLLUTE_PKT_CNT_8733B 0x04E8
#define REG_DROP_PKT_NUM_8733B 0x04EC
#define REG_CPUMGQ_TIMER_CTRL_8733B 0x04F4
#define REG_DUMMY_PAGE4_8733B 0x04FC
#define REG_ARFR6_8733B 0x1400
#define REG_ARFRH6_8733B 0x1404
#define REG_ARFR7_8733B 0x1408
#define REG_ARFRH7_8733B 0x140C
#define REG_ARFR8_8733B 0x1410
#define REG_ARFRH8_8733B 0x1414
#define REG_AESIV_SETTING_8733B 0x1424
#define REG_BF0_TIME_SETTING_8733B 0x1428
#define REG_BF1_TIME_SETTING_8733B 0x142C
#define REG_BF_TIMEOUT_EN_8733B 0x1430
#define REG_MACID_RELEASE0_8733B 0x1434
#define REG_MACID_RELEASE1_8733B 0x1438
#define REG_MACID_RELEASE2_8733B 0x143C
#define REG_MACID_RELEASE3_8733B 0x1440
#define REG_MACID_RELEASE_SETTING_8733B 0x1444
#define REG_FAST_EDCA_VOVI_SETTING_8733B 0x1448
#define REG_FAST_EDCA_BEBK_SETTING_8733B 0x144C
#define REG_MACID_DROP0_8733B 0x1450
#define REG_MACID_DROP1_8733B 0x1454
#define REG_MACID_DROP2_8733B 0x1458
#define REG_MACID_DROP3_8733B 0x145C
#define REG_R_MACID_RELEASE_SUCCESS_0_8733B 0x1460
#define REG_R_MACID_RELEASE_SUCCESS_1_8733B 0x1464
#define REG_R_MACID_RELEASE_SUCCESS_2_8733B 0x1468
#define REG_R_MACID_RELEASE_SUCCESS_3_8733B 0x146C
#define REG_MGQ_FIFO_WRITE_POINTER_8733B 0x1470
#define REG_MGQ_FIFO_READ_POINTER_8733B 0x1471
#define REG_MGQ_FIFO_ENABLE_8733B 0x1472
#define REG_MGQ_FIFO_RELEASE_INT_MASK_8733B 0x1474
#define REG_MGQ_FIFO_RELEASE_INT_FLAG_8733B 0x1476
#define REG_MGQ_FIFO_VALID_8733B 0x1478
#define REG_MGQ_FIFO_LIFETIME_8733B 0x147A
#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8733B 0x147C
#define REG_NEW_EDCA_CTRL_8733B 0x14F0
#define REG_SWPS_CTRL_8733B 0x14F4
#define REG_SWPS_TIME_TH_8733B 0x14F8
#define REG_MACID_SWPS_EN_8733B 0x14FC
#define REG_EDCA_VO_PARAM_8733B 0x0500
#define REG_EDCA_VI_PARAM_8733B 0x0504
#define REG_EDCA_BE_PARAM_8733B 0x0508
#define REG_EDCA_BK_PARAM_8733B 0x050C
#define REG_BCNTCFG_8733B 0x0510
#define REG_PIFS_8733B 0x0512
#define REG_RDG_PIFS_8733B 0x0513
#define REG_SIFS_8733B 0x0514
#define REG_TSFTR_SYN_OFFSET_8733B 0x0518
#define REG_AGGR_BREAK_TIME_8733B 0x051A
#define REG_SLOT_8733B 0x051B
#define REG_NOA_ON_ERLY_TIME_8733B 0x051C
#define REG_NOA_OFF_ERLY_TIME_8733B 0x051D
#define REG_TX_PTCL_CTRL_8733B 0x0520
#define REG_TXPAUSE_8733B 0x0522
#define REG_DIS_TXREQ_CLR_8733B 0x0523
#define REG_RD_CTRL_8733B 0x0524
#define REG_P2PPS_CTRL_8733B 0x0527
#define REG_PKT_LIFETIME_CTRL_8733B 0x0528
#define REG_P2PPS_SPEC_STATE_8733B 0x052B
#define REG_TBTT_AREA_BLK_4AC_8733B 0x052C
#define REG_P2PON_DIS_TXTIME_8733B 0x0531
#define REG_EDCA_REF_CTRL_8733B 0x0534
#define REG_QUEUE_INCOL_THR_8733B 0x0538
#define REG_QUEUE_INCOL_EN_8733B 0x053C
#define REG_TBTT_PROHIBIT_8733B 0x0540
#define REG_P2PPS_STATE_8733B 0x0543
#define REG_RD_NAV_NXT_8733B 0x0544
#define REG_NAV_PROT_LEN_8733B 0x0546
#define REG_FTM_CTRL_8733B 0x0548
#define REG_FTM_TSF_CNT_8733B 0x054C
#define REG_BCN_CTRL_8733B 0x0550
#define REG_BCN_CTRL_CLINT0_8733B 0x0551
#define REG_MBID_NUM_8733B 0x0552
#define REG_DUAL_TSF_RST_8733B 0x0553
#define REG_MBSSID_BCN_SPACE_8733B 0x0554
#define REG_DRVERLYINT_8733B 0x0558
#define REG_BCNDMATIM_8733B 0x0559
#define REG_USTIME_TSF_8733B 0x055C
#define REG_BCN_MAX_ERR_8733B 0x055D
#define REG_RXTSF_OFFSET_CCK_8733B 0x055E
#define REG_RXTSF_OFFSET_OFDM_8733B 0x055F
#define REG_TSFTR_8733B 0x0560
#define REG_TSFTR_1_8733B 0x0564
#define REG_FREERUN_CNT_8733B 0x0568
#define REG_FREERUN_CNT_1_8733B 0x056C
#define REG_TBTT_PROHIBIT_INFRA_8733B 0x0571
#define REG_CTWND_8733B 0x0572
#define REG_BCNIVLCUNT_8733B 0x0573
#define REG_BCNDROPCTRL_8733B 0x0574
#define REG_HGQ_TIMEOUT_PERIOD_8733B 0x0575
#define REG_TXCMD_TIMEOUT_PERIOD_8733B 0x0576
#define REG_MISC_CTRL_8733B 0x0577
#define REG_BCN_CTRL_CLINT1_8733B 0x0578
#define REG_BCN_CTRL_CLINT2_8733B 0x0579
#define REG_BCN_CTRL_CLINT3_8733B 0x057A
#define REG_EXTEND_CTRL_8733B 0x057B
#define REG_P2PPS1_SPEC_STATE_8733B 0x057C
#define REG_P2PPS1_STATE_8733B 0x057D
#define REG_P2PPS2_SPEC_STATE_8733B 0x057E
#define REG_P2PPS2_STATE_8733B 0x057F
#define REG_PS_TIMER0_8733B 0x0580
#define REG_PS_TIMER1_8733B 0x0584
#define REG_PS_TIMER2_8733B 0x0588
#define REG_TBTT_CTN_AREA_8733B 0x058C
#define REG_FORCE_BCN_IFS_8733B 0x058E
#define REG_TXOP_MIN_8733B 0x0590
#define REG_PRE_BKF_TIME_8733B 0x0592
#define REG_CROSS_TXOP_CTRL_8733B 0x0593
#define REG_TBTT_INT_SHIFT_CLI_8733B 0x0594
#define REG_TBTT_INT_SHIFT_ENABLE_8733B 0x0598
#define REG_ATIMWND_GROUP1_8733B 0x05A0
#define REG_ATIMWND_GROUP2_8733B 0x05A1
#define REG_ATIMWND_GROUP3_8733B 0x05A2
#define REG_ATIMWND_GROUP4_8733B 0x05A3
#define REG_DTIM_COUNT_GROUP1_8733B 0x05A4
#define REG_DTIM_COUNT_GROUP2_8733B 0x05A5
#define REG_DTIM_COUNT_GROUP3_8733B 0x05A6
#define REG_DTIM_COUNT_GROUP4_8733B 0x05A7
#define REG_HIQ_NO_LMT_EN_V2_8733B 0x05A8
#define REG_MBID_BCNQ_EN_8733B 0x05AC
#define REG_EARLY_128US_8733B 0x05B1
#define REG_P2PPS1_CTRL_8733B 0x05B2
#define REG_P2PPS2_CTRL_8733B 0x05B3
#define REG_TIMER0_SRC_SEL_8733B 0x05B4
#define REG_NOA_UNIT_SEL_8733B 0x05B5
#define REG_P2POFF_DIS_TXTIME_8733B 0x05B7
#define REG_MBSSID_BCN_SPACE2_8733B 0x05B8
#define REG_MBSSID_BCN_SPACE3_8733B 0x05BC
#define REG_ACMHWCTRL_8733B 0x05C0
#define REG_ACMRSTCTRL_8733B 0x05C1
#define REG_ACMAVG_8733B 0x05C2
#define REG_VO_ADMTIME_8733B 0x05C4
#define REG_VI_ADMTIME_8733B 0x05C6
#define REG_BE_ADMTIME_8733B 0x05C8
#define REG_EDCA_RANDOM_GEN_8733B 0x05CC
#define REG_TXCMD_NOA_SEL_8733B 0x05CF
#define REG_BCNERR_CFG_8733B 0x05D0
#define REG_BCN_ELY_ADJ_8733B 0x05D4
#define REG_BCNERR_CNT1_8733B 0x05D8
#define REG_BCNERR_CNT2_8733B 0x05DC
#define REG_NOA_PARAM_8733B 0x05E0
#define REG_NOA_PARAM_1_8733B 0x05E4
#define REG_NOA_PARAM_2_8733B 0x05E8
#define REG_NOA_PARAM_3_8733B 0x05EC
#define REG_P2P_RST_8733B 0x05F0
#define REG_SCHEDULER_RST_8733B 0x05F1
#define REG_SCHEDULER_DBG_8733B 0x05F4
#define REG_SCH_TXCMD_8733B 0x05F8
#define REG_PAGE5_DUMMY_8733B 0x05FC
#define REG_CPUMGQ_TX_TIMER_8733B 0x1500
#define REG_PS_TIMER_A_8733B 0x1504
#define REG_PS_TIMER_B_8733B 0x1508
#define REG_PS_TIMER_C_8733B 0x150C
#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8733B 0x1510
#define REG_CPUMGQ_TX_TIMER_EARLY_8733B 0x1514
#define REG_PS_TIMER_A_EARLY_8733B 0x1515
#define REG_PS_TIMER_B_EARLY_8733B 0x1516
#define REG_PS_TIMER_C_EARLY_8733B 0x1517
#define REG_CPUMGQ_PARAMETER_8733B 0x1518
#define REG_TSF_SYN_CTRL0_8733B 0x1520
#define REG_TSF_SYN_OFFSET1_8733B 0x1524
#define REG_TSF_SYN_OFFSET2_8733B 0x1528
#define REG_TSF_SYN_COMPARE_VALUE_L_8733B 0x1530
#define REG_TSF_SYN_COMPARE_VALUE_H_8733B 0x1534
#define REG_SCHEDULER_COUNTER_8733B 0x15D0
#define REG_WMAC_CR_8733B 0x0600
#define REG_FWPKT_CR_8733B 0x0601
#define REG_FWPKT_CR_EXT_8733B 0x0602
#define REG_WMAC_BWOPMODE_8733B 0x0603
#define REG_TCR_8733B 0x0604
#define REG_RCR_8733B 0x0608
#define REG_RX_PKT_LIMIT_8733B 0x060C
#define REG_MBIDCTRL_8733B 0x060E
#define REG_RX_DRVINFO_SZ_8733B 0x060F
#define REG_MACID_8733B 0x0610
#define REG_MACID_H_8733B 0x0614
#define REG_BSSID_8733B 0x0618
#define REG_BSSID_H_8733B 0x061C
#define REG_MAR_8733B 0x0620
#define REG_MAR_H_8733B 0x0624
#define REG_MBIDCAMCFG_1_8733B 0x0628
#define REG_MBIDCAMCFG_2_8733B 0x062C
#define REG_WMAC_TCR_TSFT_OFS_8733B 0x0630
#define REG_UDF_THSD_8733B 0x0632
#define REG_ZLD_NUM_8733B 0x0633
#define REG_STMP_THSD_8733B 0x0634
#define REG_WMAC_TXTIMEOUT_8733B 0x0635
#define REG_USTIME_EDCA_8733B 0x0638
#define REG_ACKTO_CCK_8733B 0x0639
#define REG_MAC_SPEC_SIFS_8733B 0x063A
#define REG_RESP_SIFS_CCK_8733B 0x063C
#define REG_RESP_SIFS_OFDM_8733B 0x063E
#define REG_ACKTO_8733B 0x0640
#define REG_CTS2TO_8733B 0x0641
#define REG_EIFS_8733B 0x0642
#define REG_RPFM_MAP_8733B 0x0644
#define REG_RPFMCAM_CMD_8733B 0x0648
#define REG_RPFMCAM_WD_8733B 0x064C
#define REG_NAV_CTRL_8733B 0x0650
#define REG_BACAMCMD_8733B 0x0654
#define REG_BACAM_WD_L_8733B 0x0658
#define REG_BACAM_WD_H_8733B 0x065C
#define REG_LBK_DLY_8733B 0x0660
#define REG_BITMAP_CMD_8733B 0x0661
#define REG_TX_RX_8733B 0x0662
#define REG_WMAC_BITMAP_CTL_8733B 0x0663
#define REG_RXERR_RPT_8733B 0x0664
#define REG_WMAC_TRXPTCL_CTL_8733B 0x0668
#define REG_WMAC_TRXPTCL_CTL_H_8733B 0x066C
#define REG_KEYCAMCMD_8733B 0x0670
#define REG_KEYCAM_WD_8733B 0x0674
#define REG_CAMREAD_8733B 0x0678
#define REG_CAMDBG_8733B 0x067C
#define REG_SECCFG_8733B 0x0680
#define REG_RXFILTER_CATEGORY_ACTION_8733B 0x0684
#define REG_RXFLTMAP3_8733B 0x0688
#define REG_RXFLTMAP4_8733B 0x068A
#define REG_RXFLTMAP5_8733B 0x068C
#define REG_RXFLTMAP6_8733B 0x068E
#define REG_WOW_CTRL_8733B 0x0690
#define REG_NAN_RX_FILTER_8733B 0x0691
#define REG_PS_RX_INFO_8733B 0x0692
#define REG_WMMPS_UAPSD_TID_8733B 0x0693
#define REG_LPNAV_CTRL_8733B 0x0694
#define REG_WKFMCAM_CMD_8733B 0x0698
#define REG_WKFMCAM_WD_8733B 0x069C
#define REG_RXFLTMAP0_8733B 0x06A0
#define REG_RXFLTMAP1_8733B 0x06A2
#define REG_RXFLTMAP2_8733B 0x06A4
#define REG_BCN_PSR_RPT_8733B 0x06A8
#define REG_FLC_CTRL_8733B 0x06AC
#define REG_FLC_RPCT_8733B 0x06AD
#define REG_FLC_PTS_8733B 0x06AE
#define REG_FLC_TRPC_8733B 0x06AF
#define REG_RXPKTMON_CTRL_8733B 0x06B0
#define REG_STATE_MON_8733B 0x06B4
#define REG_ERROR_EVT_CTL_8733B 0x06B8
#define REG_SEARCH_MACID_8733B 0x06BC
#define REG_BT_COEX_TABLE_V1_8733B 0x06C0
#define REG_BT_COEX_TABLE2_V1_8733B 0x06C4
#define REG_BT_COEX_BREAK_TABLE_8733B 0x06C8
#define REG_BT_COEX_TABLE_H_V1_8733B 0x06CC
#define REG_RXCMD_0_8733B 0x06D0
#define REG_RXCMD_1_8733B 0x06D4
#define REG_RESP_TXINFO_CFG_8733B 0x06D8
#define REG_BBPSF_CTRL_8733B 0x06DC
#define REG_RESP_TXINFO_RATE_8733B 0x06DE
#define REG_P2P_RX_BCN_NOA_8733B 0x06E0
#define REG_ASSOCIATED_BFMER0_INFO_8733B 0x06E4
#define REG_SOUNDING_CFG1_8733B 0x06E8
#define REG_SOUNDING_CFG2_8733B 0x06EC
#define REG_SOUNDING_CFG3_8733B 0x06F0
#define REG_SOUNDING_CFG0_8733B 0x06F4
#define REG_ANTCD_INFO_8733B 0x06F8
#define REG_CSI_PTR_8733B 0x06FC
#define REG_BCN_PSR_RPT2_8733B 0x1600
#define REG_BCN_PSR_RPT3_8733B 0x1604
#define REG_BCN_PSR_RPT4_8733B 0x1608
#define REG_A1_ADDR_MASK_8733B 0x160C
#define REG_RXPSF_CTRL_8733B 0x1610
#define REG_RXPSF_TYPE_CTRL_8733B 0x1614
#define REG_WAIT_PHYSTS_CTL_8733B 0x1618
#define REG_MACID2_8733B 0x1620
#define REG_MACID2_H_8733B 0x1624
#define REG_BSSID2_8733B 0x1628
#define REG_BSSID2_H_8733B 0x162C
#define REG_MACID3_8733B 0x1630
#define REG_MACID3_H_8733B 0x1634
#define REG_BSSID3_8733B 0x1638
#define REG_BSSID3_H_8733B 0x163C
#define REG_MACID4_8733B 0x1640
#define REG_MACID4_H_8733B 0x1644
#define REG_BSSID4_8733B 0x1648
#define REG_BSSID4_H_8733B 0x164C
#define REG_NOA_REPORT_8733B 0x1650
#define REG_NOA_REPORT_1_8733B 0x1654
#define REG_NOA_REPORT_2_8733B 0x1658
#define REG_NOA_REPORT_3_8733B 0x165C
#define REG_PWRBIT_SETTING_8733B 0x1660
#define REG_GENERAL_OPTION_8733B 0x1664
#define REG_RXAI_CTRL_8733B 0x1668
#define REG_CSI_RRSR_8733B 0x1678
#define REG_MU_BF_OPTION_8733B 0x167C
#define REG_WMAC_PAUSE_BB_CLR_TH_8733B 0x167D
#define REG_WMAC_ARB_CLR_8733B 0x167E
#define REG_WMAC_MU_OPTION_8733B 0x167F
#define REG_WMAC_MU_BF_CTL_8733B 0x1680
#define REG_WMAC_MU_BFRPT_PARA_8733B 0x1682
#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8733B 0x1684
#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8733B 0x1686
#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8733B 0x1688
#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8733B 0x168A
#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8733B 0x168C
#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8733B 0x168E
#define REG_WMAC_BB_STOP_RX_COUNTER_8733B 0x1690
#define REG_WMAC_PLCP_MONITOR_8733B 0x1694
#define REG_WMAC_CSIDMA_CFG_8733B 0x169C
#define REG_TRANSMIT_ADDRSS_0_8733B 0x16A0
#define REG_TRANSMIT_ADDRSS_0_H_8733B 0x16A4
#define REG_TRANSMIT_ADDRSS_1_8733B 0x16A8
#define REG_TRANSMIT_ADDRSS_1_H_8733B 0x16AC
#define REG_TRANSMIT_ADDRSS_2_8733B 0x16B0
#define REG_TRANSMIT_ADDRSS_2_H_8733B 0x16B4
#define REG_TRANSMIT_ADDRSS_3_8733B 0x16B8
#define REG_TRANSMIT_ADDRSS_3_H_8733B 0x16BC
#define REG_TRANSMIT_ADDRSS_4_8733B 0x16C0
#define REG_TRANSMIT_ADDRSS_4_H_8733B 0x16C4
#define REG_MACID1_8733B 0x0700
#define REG_MACID1_1_8733B 0x0704
#define REG_BSSID1_8733B 0x0708
#define REG_BSSID1_1_8733B 0x070C
#define REG_BCN_PSR_RPT1_8733B 0x0710
#define REG_ASSOCIATED_BFMEE_SEL_8733B 0x0714
#define REG_SND_PTCL_CTRL_8733B 0x0718
#define REG_BEAMFORM_STATUS_8733B 0x071C
#define REG_NSARP_CFG_8733B 0x0720
#define REG_BEAMFORMING_INFO_NSARP_8733B 0x072C
#define REG_IPV6_0_8733B 0x0730
#define REG_IPV6_1_8733B 0x0734
#define REG_IPV6_2_8733B 0x0738
#define REG_IPV6_3_8733B 0x073C
#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8733B 0x0750
#define REG_WMAC_SWAES_CFG_8733B 0x0760
#define REG_BT_PRI_8733B 0x0762
#define REG_BT_COEX_ENH_8733B 0x0764
#define REG_WLAN_ACT_MASK_CTRL_8733B 0x0768
#define REG_WLAN_ACT_MASK_CTRL_1_8733B 0x076C
#define REG_BT_COEX_ENHANCED_INTR_CTRL_8733B 0x076E
#define REG_BT_PROPRI_8733B 0x0778
#define REG_BT_STATUS_REPORT_REGISTER_8733B 0x077C
#define REG_BT_INTERRUPT_CONTROL_REGISTER_8733B 0x0780
#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8733B 0x0784
#define REG_CH_COEXIST_8733B 0x0785
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8733B 0x0788
#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8733B 0x078C
#define REG_BT_INTERRUPT_STATUS_REGISTER_8733B 0x078F
#define REG_BT_TDMA_TIME_REGISTER_8733B 0x0790
#define REG_BT_ACT_REGISTER_8733B 0x0794
#define REG_LTR_IDLE_LATENCY_V2_8733B 0x0798
#define REG_LTR_ACTIVE_LATENCY_V2_8733B 0x079C
#define REG_OBFF_CTRL_8733B 0x07A0
#define REG_LTR_CTRL_8733B 0x07A4
#define REG_LTR_CTRL2_8733B 0x07A8
#define REG_ANTTRN_CTR_V1_8733B 0x07B0
#define REG_ANTTRN_CTR_8733B 0x07B4
#define REG_WMAC_PKTCNT_RWD_8733B 0x07B8
#define REG_WMAC_PKTCNT_CTRL_8733B 0x07BC
#define REG_IQ_DUMP_8733B 0x07C0
#define REG_MASK_LA_MAC_8733B 0x07C4
#define REG_MATCH_REF_MAC_8733B 0x07C8
#define REG_WMAC_FTM_CTL_8733B 0x07CC
#define REG_WMAC_LA_DUMP_FUNC_EXT_8733B 0x07CE
#define REG_OFDM_CCK_LEN_MASK_8733B 0x07D0
#define REG_WMAC_OPTION_FUNCTION_1_8733B 0x07D4
#define REG_WMAC_OPTION_FUNCTION_2_8733B 0x07D8
#define REG_RX_FILTER_FUNCTION_8733B 0x07DA
#define REG_NDP_SIG_8733B 0x07E0
#define REG_WSEC_OPTION_8733B 0x07EC
#define REG_RTS_ADDRESS_0_8733B 0x07F0
#define REG_RTS_ADDRESS_0_1_8733B 0x07F4
#define REG_RTS_ADDRESS_1_8733B 0x07F8
#define REG_RTS_ADDRESS_1_1_8733B 0x07FC
#define REG_SDIO_TX_CTRL_8733B 0x10250000
#define REG_SDIO_CMD11_VOL_SWITCH_8733B 0x10250004
#define REG_SDIO_CTRL_8733B 0x10250005
#define REG_SDIO_DRIVING_8733B 0x10250006
#define REG_SDIO_MONITOR_8733B 0x10250008
#define REG_SDIO_MONITOR_2_8733B 0x1025000C
#define REG_SDIO_HIMR_8733B 0x10250014
#define REG_SDIO_HISR_8733B 0x10250018
#define REG_SDIO_RX_REQ_LEN_8733B 0x1025001C
#define REG_SDIO_FREE_TXPG_SEQ_V1_8733B 0x1025001F
#define REG_SDIO_FREE_TXPG_8733B 0x10250020
#define REG_SDIO_FREE_TXPG2_8733B 0x10250024
#define REG_SDIO_OQT_FREE_TXPG_V1_8733B 0x10250028
#define REG_SDIO_TXPKT_EMPTY_8733B 0x1025002C
#define REG_SDIO_HTSFR_INFO_8733B 0x10250030
#define REG_SDIO_HCPWM1_V2_8733B 0x10250038
#define REG_SDIO_HCPWM2_V2_8733B 0x1025003A
#define REG_SDIO_INDIRECT_REG_CFG_8733B 0x10250040
#define REG_SDIO_INDIRECT_REG_DATA_8733B 0x10250044
#define REG_SDIO_H2C_8733B 0x10250060
#define REG_SDIO_C2H_8733B 0x10250064
#define REG_SDIO_HRPWM1_8733B 0x10250080
#define REG_SDIO_HRPWM2_8733B 0x10250082
#define REG_SDIO_HPS_CLKR_8733B 0x10250084
#define REG_SDIO_BUS_CTRL_8733B 0x10250085
#define REG_SDIO_HSUS_CTRL_8733B 0x10250086
#define REG_SDIO_RESPONSE_TIMER_8733B 0x10250088
#define REG_SDIO_CMD_CRC_8733B 0x1025008A
#define REG_SDIO_HSISR_8733B 0x10250090
#define REG_SDIO_HSIMR_8733B 0x10250091
#define REG_SDIO_DIOERR_RPT_8733B 0x102500C0
#define REG_SDIO_CMD_ERRCNT_8733B 0x102500C2
#define REG_SDIO_DATA_ERRCNT_8733B 0x102500C3
#define REG_SDIO_CMD_ERR_CONTENT_8733B 0x102500C4
#define REG_SDIO_CRC_ERR_IDX_8733B 0x102500C9
#define REG_SDIO_DATA_CRC_8733B 0x102500CA
#define REG_SDIO_TRANS_FIFO_STATUS_8733B 0x102500CC

#endif
