/******************************************************************************
 *
 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 ******************************************************************************/

#include "halmac_pwr_seq_8733b.h"

#if HALMAC_8733B_SUPPORT

//for sdio, after 0x5[1]=1(mac power off),only can use cmd52

static struct halmac_wlan_pwr_cfg TRANS_CARDDIS_TO_CARDEMU_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3), 0},
	{0x0086,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_SDIO,
	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
	{0x0086,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_SDIO,
	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
	{0x004A,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
	 {0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	 {0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(0), 0},

	{0x1002,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	 /*jerry_zhou
	 for bb/rf reset
	 */
	{0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},

	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},

	{0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_ACT_power_on_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(3)|BIT(2), 0},
	{0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
	 {0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	 {0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(0), 0},

	{0x1002,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	 {0x1002,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},

	 /*jerry_zhou
	 for bb/rf reset
	 */
	{0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},

	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	{0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_sus_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	  /*jerry_zhou
	 for bb/rf reset
	 */
	{0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	{0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	{0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	{0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	{0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	{0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	
	{0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	{0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
	 {0x10260005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
	{0x10260005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};



static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_card_dis_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x00CD,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},//0xCD[0],release SYS PMC,to avoid SYS PMC being halted by FW
	{0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	{0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	
	{0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},

	{0x0049,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3), 0},
	{0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	{0x10260005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
	{0x10260005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
	 {0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_CARDEMU_power_off_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	//rf reset
	{0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	{0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x87},
	 {0x001F,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	 {0x0077,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	
	{0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), BIT(1)| BIT(0)},
	 {0x2,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1)| BIT(0), 0},
	 {0x0047,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)},
	 {0x0049,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3), 0},
	{0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
	 {0x10260005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
	{0x10260005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_CARDDIS_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
	{0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7)| BIT(6), 0},
	 {0x10260005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
	{0x10260006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(6), 0},
	 {0x10260007,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x0},
	 {0x0007,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x10},
	 {0x10261004,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3)|BIT(2)|BIT(1)|BIT(0), 0x0},
	 {0x1004,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3)|BIT(2)|BIT(1)|BIT(0), 0x2},
	 {0x0024,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3)|BIT(2)|BIT(1)|BIT(0), 0},
	 {0x10260024,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3)|BIT(2)|BIT(1)|BIT(0), 0},
	 {0x0025,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7)|BIT(6)|BIT(5)|BIT(4), BIT(4)},
	 {0x10260025,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7)|BIT(6)|BIT(5)|BIT(4), BIT(4)},
	 {0x0021,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7)|BIT(6)|BIT(5)|BIT(4), BIT(6)|BIT(5)|BIT(4)},
	 {0x10260021,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7)|BIT(6)|BIT(5)|BIT(4), BIT(6)|BIT(5)|BIT(4)},
	{0x004A,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	 {0x0086,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_SDIO,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	 {0x0086,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_SDIO,
	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

/* Card Enable Array */
struct halmac_wlan_pwr_cfg *card_en_flow_8733b[] = {
	TRANS_CARDDIS_TO_CARDEMU_8733B,
	TRANS_CARDEMU_TO_ACT_8733B,
	NULL
};

/* Card Disable Array */
struct halmac_wlan_pwr_cfg *card_dis_flow_8733b[] = {
	TRANS_ACT_TO_CARDEMU_card_dis_8733B,
	TRANS_CARDEMU_TO_CARDDIS_8733B,
	NULL
};

#if HALMAC_PLATFORM_TESTPROGRAM

static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_SUS_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3) , BIT(3)},
	 {0x10260005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3) , BIT(3)},
	{0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(6), 0},
	 {0x10260006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(6), 0},
	{0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
	 {0x10260006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
	{0x10260007,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x0},
	 {0x0007,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x10},
	 {0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(6), 0},
	 {0x10260006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(6), 0},
	 {0x10261004,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3)| BIT(2)|BIT(1)|BIT(0), 0x0},
	{0x1004,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3)| BIT(2)|BIT(1)|BIT(0), 0x2},

	{0x0024,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3)| BIT(2)|BIT(1)|BIT(0), 0},
	 {0x10260024,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3)| BIT(2)|BIT(1)|BIT(0), 0},

	 {0x0025,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7)| BIT(6)|BIT(5)|BIT(4), BIT(4)},
	 {0x10260025,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7)| BIT(6)|BIT(5)|BIT(4), BIT(4)},

	 {0x0021,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7)| BIT(6)|BIT(5)|BIT(4), BIT(6)|BIT(5)|BIT(4)},
	 {0x10260021,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7)| BIT(6)|BIT(5)|BIT(4), BIT(6)|BIT(5)|BIT(4)},
	 {0x0086,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_SDIO,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0x0086,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_SDIO,
	 HALMAC_PWR_CMD_POLLING, BIT(1), 0},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg TRANS_SUS_TO_CARDEMU_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x0086,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_SDIO,
	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
	{0x0086,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_SDIO,
	 HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)},
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3), 0},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg TRANS_CARDEMU_TO_PDN_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x0007,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x20},
	{0x0006,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg TRANS_PDN_TO_CARDEMU_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_LPS_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x0101,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	{0x0199,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
	{0x019B,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
	{0x1138,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)},
	{0x0194,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0x0093,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_PCI_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x06},
	{0x0092,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_PCI_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x68},
	{0x0093,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x02},
	{0x0092,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x68},
	{0x0093,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x03},
	{0x0092,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x68},
	{0x0090,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
	{0x0301,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_PCI_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0x7F, 0xFF},
	{0x0522,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
	{0x05F8,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
	{0x05F9,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
	{0x05FA,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
	{0x05FB,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
	{0x0002,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
	{0x0002,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US},
	{0x0100,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F},
	{0x0008,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
	{0x0109,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)},
	 {0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	{0x0090,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg TRANS_ACT_TO_DEEP_LPS_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x0101,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	{0x0199,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
	{0x019B,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
	{0x1138,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)},
	{0x0194,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0x0093,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_PCI_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x04},
	{0x0092,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_PCI_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x28},
	{0x0093,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x00},
	{0x0092,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x28},
	{0x0093,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x01},
	{0x0092,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x28},
	{0x0090,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)},
	{0x0301,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_PCI_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0x7F, 0xFF},
	{0x0522,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
	{0x05F8,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
	{0x05F9,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
	{0x05FA,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
	{0x05FB,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, 0xFF, 0},
	{0x0002,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},
	{0x0002,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_US},
	{0x0100,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F},
	{0x0008,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)},
	{0x0109,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)},
	{0x0090,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg TRANS_LPS_TO_ACT_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x0080,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_SDIO,
	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
	{0x0002,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
	{0x0080,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_SDIO,
	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
	{0xFE58,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x84},
	{0x03D9,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_PCI_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
	{0x0002,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_PCI_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
	{0x03D9,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_PCI_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7), 0},
	{0x0002,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWR_DELAY_MS},
	{0x0008,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(4), 0},
	{0x0109,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_POLLING, BIT(7), 0},
	{0x0100,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF },
	{0x0002,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)},
	{0x0522,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0},
	{0x113C,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x03},
	{0x0124,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
	{0x0125,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
	{0x0126,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
	{0x0127,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF},
	{0x0090,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(1), 0},
	{0x0101,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},
	{0x0301,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_PCI_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0x7F, 0x00},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg HWPND_8733B[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	{0x10DD,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_UART_MASK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3)| BIT(2)|BIT(1)|BIT(0), BIT(0)},
	{0x0068,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_UART_MASK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0x006A,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_UART_MASK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},
	{0x0062,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_UART_MASK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(5), 0},
	{0x0046,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_UART_MASK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(6), 0},
	{0x0058,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_UART_MASK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7)| BIT(6), BIT(7)|BIT(6)},
	{0x0068,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_SDIO_UART_MASK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)},
	{0x0005,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
	{0x0004,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)},
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg active_to_lps[]={
	{0x006A,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},//0x6a[2]=0 ,disable BT
	 {0x0092,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},//0x90[16]=1, not partial off
	{0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6)},//0x90[14]=1, not low voltage
	{0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	{0x0090,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},//0x90[0]=1, enter LPS mode
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg active_to_lps_32k[]={
	{0x006A,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},//0x6a[2]=0 ,disable BT
	{0x0194,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},//0x194[0]=1, not partial off
	{0x018c,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x00},
	{0x018d,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x2d},
	 {0x018e,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x31},
	 {0x018f,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, 0xFF, 0x01},//0x18c[31:0]=0x01312d00, 20M
	 {0x0101,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},
	 {0x0101,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	 {0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	{0x0090,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},//0x90[0]=1, enter LPS mode
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg active_to_lps_lv[]={
	{0x006A,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},//0x6a[2]=0 ,disable BT
	
	{0x0092,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},//0x90[16]=1, not partial off
	{0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(6), 0},//0x90[14]=0, low voltage
	  {0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	{0x0090,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},//0x90[0]=1, enter LPS mode
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};

static struct halmac_wlan_pwr_cfg active_to_lps_pg[]={
	{0x006A,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},//0x6a[2]=0 ,disable BT
	
	{0x0092,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},//0x90[16]=1, partial off
	{0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6)},//0x90[14]=1, not low voltage
	 {0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	{0x0090,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},//0x90[0]=1, enter LPS mode
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};


static struct halmac_wlan_pwr_cfg active_to_lps_lv_pg[]={
	{0x006A,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), 0},//0x6a[2]=0 ,disable BT

	
	{0x0092,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), 0},//0x90[16]=1,  partial off
	{0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(6), 0},//0x90[14]=1, low voltage
	 {0x0091,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)},
	{0x0090,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 HALMAC_PWR_ADDR_MAC,
	 HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)},//0x90[0]=1, enter LPS mode
	{0xFFFF,
	 HALMAC_PWR_CUT_ALL_MSK,
	 HALMAC_PWR_INTF_ALL_MSK,
	 0,
	 HALMAC_PWR_CMD_END, 0, 0},
};


/* Suspend Array */
struct halmac_wlan_pwr_cfg *suspend_flow_8733b[] = {
	TRANS_ACT_TO_CARDEMU_sus_8733B,
	TRANS_CARDEMU_TO_SUS_8733B,
	NULL
};

/* Resume Array */
struct halmac_wlan_pwr_cfg *resume_flow_8733b[] = {
	TRANS_SUS_TO_CARDEMU_8733B,
	TRANS_CARDEMU_TO_ACT_8733B,
	NULL
};

/* HWPDN Array - HW behavior */
struct halmac_wlan_pwr_cfg *hwpdn_flow_8733b[] = {
	HWPND_8733B,
	NULL
};


/* Enter LPS - FW behavior */
struct halmac_wlan_pwr_cfg *enter_lps_flow_8733b[] = {
	//TRANS_ACT_TO_LPS_8733B,
	NULL
};

/* Enter Deep LPS - FW behavior */
struct halmac_wlan_pwr_cfg *enter_dlps_flow_8733b[] = {
	//TRANS_ACT_TO_DEEP_LPS_8733B,
	NULL
};

/* Leave LPS -FW behavior */
struct halmac_wlan_pwr_cfg *leave_lps_flow_8733b[] = {
	//TRANS_LPS_TO_ACT_8733B,
	NULL
};



/* power off */
struct halmac_wlan_pwr_cfg *power_off_flow_8733b[] = {
	TRANS_ACT_TO_CARDEMU_power_off_8733B,
	NULL
};

/* power on */
struct halmac_wlan_pwr_cfg *power_on_flow_8733b[] = {
	TRANS_CARDEMU_TO_ACT_power_on_8733B,
	NULL
};

struct halmac_wlan_pwr_cfg *lps_8733b[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	active_to_lps,
	NULL
};

struct halmac_wlan_pwr_cfg *lps_32k_8733b[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	active_to_lps_32k,
	NULL
};

struct halmac_wlan_pwr_cfg *lps_lv_8733b[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	active_to_lps_lv,
	NULL
};

struct halmac_wlan_pwr_cfg *lps_pg_8733b[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	active_to_lps_pg,
	NULL
};

struct halmac_wlan_pwr_cfg *lps_lv_pg_8733b[] = {
	/* { offset, cut_msk, interface_msk, base|cmd, msk, value } */
	active_to_lps_lv_pg,
	NULL
};

#endif

#endif /* HALMAC_8733B_SUPPORT */
