#ifndef __RTL_WLAN_BITDEF_H__
#define __RTL_WLAN_BITDEF_H__

#include "halmac_hw_cfg.h"

#define CPU_OPT_WIDTH 0x1F

#if (HALMAC_8733B_SUPPORT)

/* 2 REG_SDIO_TX_CTRL			(Offset 0x10250000) */

#define BIT_SHIFT_SDIO_INT_TIMEOUT			16
#define BIT_MASK_SDIO_INT_TIMEOUT			0xffff
#define BIT_SDIO_INT_TIMEOUT(x)			(((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT)
#define BITS_SDIO_INT_TIMEOUT				(BIT_MASK_SDIO_INT_TIMEOUT << BIT_SHIFT_SDIO_INT_TIMEOUT)
#define BIT_CLEAR_SDIO_INT_TIMEOUT(x)			((x) & (~BITS_SDIO_INT_TIMEOUT))
#define BIT_GET_SDIO_INT_TIMEOUT(x)			(((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT)
#define BIT_SET_SDIO_INT_TIMEOUT(x, v)			(BIT_CLEAR_SDIO_INT_TIMEOUT(x) | BIT_SDIO_INT_TIMEOUT(v))

#define BIT_PWC_EV12V					BIT(15)
#define BIT_IO_ERR_STATUS				BIT(15)
#define BIT_CMD53_W_MIX				BIT(14)

#define BIT_SHIFT_PWC_EV33V				13
#define BIT_MASK_PWC_EV33V				0x3
#define BIT_PWC_EV33V(x)				(((x) & BIT_MASK_PWC_EV33V) << BIT_SHIFT_PWC_EV33V)
#define BITS_PWC_EV33V					(BIT_MASK_PWC_EV33V << BIT_SHIFT_PWC_EV33V)
#define BIT_CLEAR_PWC_EV33V(x)				((x) & (~BITS_PWC_EV33V))
#define BIT_GET_PWC_EV33V(x)				(((x) >> BIT_SHIFT_PWC_EV33V) & BIT_MASK_PWC_EV33V)
#define BIT_SET_PWC_EV33V(x, v)			(BIT_CLEAR_PWC_EV33V(x) | BIT_PWC_EV33V(v))

#define BIT_CMD53_TX_FORMAT				BIT(13)
#define BIT_PA12V_EN					BIT(12)
#define BIT_CMD53_R_TIMEOUT_MASK			BIT(12)
#define BIT_UA33V_EN					BIT(11)
#define BIT_UA12V_EN					BIT(10)

#define BIT_SHIFT_CMD53_R_TIMEOUT_UNIT			10
#define BIT_MASK_CMD53_R_TIMEOUT_UNIT			0x3
#define BIT_CMD53_R_TIMEOUT_UNIT(x)			(((x) & BIT_MASK_CMD53_R_TIMEOUT_UNIT) << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT)
#define BITS_CMD53_R_TIMEOUT_UNIT			(BIT_MASK_CMD53_R_TIMEOUT_UNIT << BIT_SHIFT_CMD53_R_TIMEOUT_UNIT)
#define BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x)		((x) & (~BITS_CMD53_R_TIMEOUT_UNIT))
#define BIT_GET_CMD53_R_TIMEOUT_UNIT(x)		(((x) >> BIT_SHIFT_CMD53_R_TIMEOUT_UNIT) & BIT_MASK_CMD53_R_TIMEOUT_UNIT)
#define BIT_SET_CMD53_R_TIMEOUT_UNIT(x, v)		(BIT_CLEAR_CMD53_R_TIMEOUT_UNIT(x) | BIT_CMD53_R_TIMEOUT_UNIT(v))

#define BIT_ISO_RFDIO					BIT(9)
#define BIT_REPLY_ERRCRC_IN_DATA			BIT(9)
#define BIT_ISO_EB2CORE				BIT(8)
#define BIT_EN_CMD53_OVERLAP				BIT(8)
#define BIT_ISO_DIOE					BIT(7)
#define BIT_REPLY_ERR_IN_R5				BIT(7)
#define BIT_ISO_WP2PP					BIT(6)
#define BIT_R18A_EN					BIT(6)
#define BIT_ISO_WLPLL2PP				BIT(5)
#define BIT_SDIO_CMD_FORCE_VLD				BIT(5)
#define BIT_ISO_PD2CORE				BIT(4)
#define BIT_INIT_CMD_EN				BIT(4)
#define BIT_ISO_PA2PCIE				BIT(3)
#define BIT_RXINT_READ_MASK_DIS			BIT(3)
#define BIT_ISO_UD2CORE				BIT(2)
#define BIT_EN_RXDMA_MASK_INT				BIT(2)
#define BIT_ISO_UA2USB					BIT(1)
#define BIT_EN_MASK_TIMER				BIT(1)
#define BIT_ISO_WD2PP					BIT(0)
#define BIT_CMD_ERR_STOP_INT_EN			BIT(0)

/* 2 REG_SYS_FUNC_EN				(Offset 0x0002) */

#define BIT_FEN_MREGEN					BIT(15)
#define BIT_FEN_HWPDN					BIT(14)
#define BIT_EFUSE_POR					BIT(13)
#define BIT_FEN_ELDR					BIT(12)
#define BIT_FEN_DCORE					BIT(11)
#define BIT_FEN_CPUEN					BIT(10)
#define BIT_FEN_DIOE					BIT(9)
#define BIT_FEN_PCIED					BIT(8)
#define BIT_FEN_PPLL					BIT(7)
#define BIT_FEN_PCIEA					BIT(6)
#define BIT_FEN_DIO_PCIE				BIT(5)
#define BIT_FEN_USBD					BIT(4)
#define BIT_FEN_USBA					BIT(3)
#define BIT_FEN_UPHY					BIT(2)
#define BIT_FEN_BB_GLB_RSTN				BIT(1)
#define BIT_FEN_BBRSTB					BIT(0)

/* 2 REG_SYS_PW_CTRL				(Offset 0x0004) */

#define BIT_SOP_EABM					BIT(31)
#define BIT_SOP_ACKF					BIT(30)
#define BIT_SOP_ERCK					BIT(29)
#define BIT_SOP_ESWR					BIT(28)
#define BIT_SOP_PWMM					BIT(27)
#define BIT_SOP_EECK					BIT(26)
#define BIT_BIS_SOP_SHCI				BIT(25)
#define BIT_SOP_EXTL					BIT(24)
#define BIT_SOP_HCI_MEM_STB				BIT(23)
#define BIT_SOP_RING_12M				BIT(22)
#define BIT_ROP_SWPR					BIT(21)
#define BIT_DIS_HW_LPLDM				BIT(20)
#define BIT_OPT_SWRST_WLMCU				BIT(19)
#define BIT_RDY_SYSPWR					BIT(17)
#define BIT_EN_WLON					BIT(16)
#define BIT_APDM_HPDN					BIT(15)
#define BIT_AFSM_PCIE_SUS_EN				BIT(12)
#define BIT_AFSM_WLSUS_EN				BIT(11)
#define BIT_APFM_SWLPS					BIT(10)
#define BIT_APFM_OFFMAC				BIT(9)
#define BIT_APFN_ONMAC					BIT(8)
#define BIT_CHIP_PDN_EN				BIT(7)
#define BIT_RDY_MACDIS					BIT(6)
#define BIT_POF_APHY_IN_L2				BIT(5)

#define BIT_SHIFT_CMD11_SEQ_END_DELAY			4
#define BIT_MASK_CMD11_SEQ_END_DELAY			0xf
#define BIT_CMD11_SEQ_END_DELAY(x)			(((x) & BIT_MASK_CMD11_SEQ_END_DELAY) << BIT_SHIFT_CMD11_SEQ_END_DELAY)
#define BITS_CMD11_SEQ_END_DELAY			(BIT_MASK_CMD11_SEQ_END_DELAY << BIT_SHIFT_CMD11_SEQ_END_DELAY)
#define BIT_CLEAR_CMD11_SEQ_END_DELAY(x)		((x) & (~BITS_CMD11_SEQ_END_DELAY))
#define BIT_GET_CMD11_SEQ_END_DELAY(x)			(((x) >> BIT_SHIFT_CMD11_SEQ_END_DELAY) & BIT_MASK_CMD11_SEQ_END_DELAY)
#define BIT_SET_CMD11_SEQ_END_DELAY(x, v)		(BIT_CLEAR_CMD11_SEQ_END_DELAY(x) | BIT_CMD11_SEQ_END_DELAY(v))

#define BIT_PFM_WOWL					BIT(3)
#define BIT_PFM_LDKP					BIT(2)
#define BIT_WL_HCI_ALD					BIT(1)

#define BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL		1
#define BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL		0x7
#define BIT_CMD11_SEQ_SAMPLE_INTERVAL(x)		(((x) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL) << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL)
#define BITS_CMD11_SEQ_SAMPLE_INTERVAL			(BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL << BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL)
#define BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x)	((x) & (~BITS_CMD11_SEQ_SAMPLE_INTERVAL))
#define BIT_GET_CMD11_SEQ_SAMPLE_INTERVAL(x)		(((x) >> BIT_SHIFT_CMD11_SEQ_SAMPLE_INTERVAL) & BIT_MASK_CMD11_SEQ_SAMPLE_INTERVAL)
#define BIT_SET_CMD11_SEQ_SAMPLE_INTERVAL(x, v)	(BIT_CLEAR_CMD11_SEQ_SAMPLE_INTERVAL(x) | BIT_CMD11_SEQ_SAMPLE_INTERVAL(v))

#define BIT_PFM_LDALL					BIT(0)
#define BIT_CMD11_SEQ_EN				BIT(0)

/* 2 REG_SDIO_CTRL				(Offset 0x10250005) */

#define BIT_SIG_OUT_PH					BIT(0)

/* 2 REG_SDIO_DRIVING			(Offset 0x10250006) */

#define BIT_SHIFT_SDIO_DRV_TYPE_D			12
#define BIT_MASK_SDIO_DRV_TYPE_D			0xf
#define BIT_SDIO_DRV_TYPE_D(x)				(((x) & BIT_MASK_SDIO_DRV_TYPE_D) << BIT_SHIFT_SDIO_DRV_TYPE_D)
#define BITS_SDIO_DRV_TYPE_D				(BIT_MASK_SDIO_DRV_TYPE_D << BIT_SHIFT_SDIO_DRV_TYPE_D)
#define BIT_CLEAR_SDIO_DRV_TYPE_D(x)			((x) & (~BITS_SDIO_DRV_TYPE_D))
#define BIT_GET_SDIO_DRV_TYPE_D(x)			(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_D) & BIT_MASK_SDIO_DRV_TYPE_D)
#define BIT_SET_SDIO_DRV_TYPE_D(x, v)			(BIT_CLEAR_SDIO_DRV_TYPE_D(x) | BIT_SDIO_DRV_TYPE_D(v))

#define BIT_SHIFT_SDIO_DRV_TYPE_C			8
#define BIT_MASK_SDIO_DRV_TYPE_C			0xf
#define BIT_SDIO_DRV_TYPE_C(x)				(((x) & BIT_MASK_SDIO_DRV_TYPE_C) << BIT_SHIFT_SDIO_DRV_TYPE_C)
#define BITS_SDIO_DRV_TYPE_C				(BIT_MASK_SDIO_DRV_TYPE_C << BIT_SHIFT_SDIO_DRV_TYPE_C)
#define BIT_CLEAR_SDIO_DRV_TYPE_C(x)			((x) & (~BITS_SDIO_DRV_TYPE_C))
#define BIT_GET_SDIO_DRV_TYPE_C(x)			(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_C) & BIT_MASK_SDIO_DRV_TYPE_C)
#define BIT_SET_SDIO_DRV_TYPE_C(x, v)			(BIT_CLEAR_SDIO_DRV_TYPE_C(x) | BIT_SDIO_DRV_TYPE_C(v))

#define BIT_SHIFT_SDIO_DRV_TYPE_B			4
#define BIT_MASK_SDIO_DRV_TYPE_B			0xf
#define BIT_SDIO_DRV_TYPE_B(x)				(((x) & BIT_MASK_SDIO_DRV_TYPE_B) << BIT_SHIFT_SDIO_DRV_TYPE_B)
#define BITS_SDIO_DRV_TYPE_B				(BIT_MASK_SDIO_DRV_TYPE_B << BIT_SHIFT_SDIO_DRV_TYPE_B)
#define BIT_CLEAR_SDIO_DRV_TYPE_B(x)			((x) & (~BITS_SDIO_DRV_TYPE_B))
#define BIT_GET_SDIO_DRV_TYPE_B(x)			(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_B) & BIT_MASK_SDIO_DRV_TYPE_B)
#define BIT_SET_SDIO_DRV_TYPE_B(x, v)			(BIT_CLEAR_SDIO_DRV_TYPE_B(x) | BIT_SDIO_DRV_TYPE_B(v))

#define BIT_SHIFT_SDIO_DRV_TYPE_A			0
#define BIT_MASK_SDIO_DRV_TYPE_A			0xf
#define BIT_SDIO_DRV_TYPE_A(x)				(((x) & BIT_MASK_SDIO_DRV_TYPE_A) << BIT_SHIFT_SDIO_DRV_TYPE_A)
#define BITS_SDIO_DRV_TYPE_A				(BIT_MASK_SDIO_DRV_TYPE_A << BIT_SHIFT_SDIO_DRV_TYPE_A)
#define BIT_CLEAR_SDIO_DRV_TYPE_A(x)			((x) & (~BITS_SDIO_DRV_TYPE_A))
#define BIT_GET_SDIO_DRV_TYPE_A(x)			(((x) >> BIT_SHIFT_SDIO_DRV_TYPE_A) & BIT_MASK_SDIO_DRV_TYPE_A)
#define BIT_SET_SDIO_DRV_TYPE_A(x, v)			(BIT_CLEAR_SDIO_DRV_TYPE_A(x) | BIT_SDIO_DRV_TYPE_A(v))

/* 2 REG_SYS_CLK_CTRL			(Offset 0x0008) */

#define BIT_WLHCI_CLK_EN				BIT(15)
#define BIT_CPU_CLK_EN					BIT(14)
#define BIT_SYMREG_CLK_EN				BIT(13)
#define BIT_HCI_CLK_EN					BIT(12)
#define BIT_MAC_CLK_EN					BIT(11)
#define BIT_SEC_CLK_EN					BIT(10)
#define BIT_PHY_SSC_RSTB				BIT(9)
#define BIT_EXT_32K_EN					BIT(8)
#define BIT_WL_CLK_TEST				BIT(7)
#define BIT_LOADER_CLK_EN				BIT(5)
#define BIT_MACSLP					BIT(4)
#define BIT_OSC32K_POW_CKGEN_WL			BIT(3)
#define BIT_ROMD16V_EN					BIT(2)
#define BIT_CKSL_CKANA					BIT(1)
#define BIT_CNTD16V_EN					BIT(0)

#define BIT_SHIFT_SDIO_INT_START			0
#define BIT_MASK_SDIO_INT_START			0xffffffffL
#define BIT_SDIO_INT_START(x)				(((x) & BIT_MASK_SDIO_INT_START) << BIT_SHIFT_SDIO_INT_START)
#define BITS_SDIO_INT_START				(BIT_MASK_SDIO_INT_START << BIT_SHIFT_SDIO_INT_START)
#define BIT_CLEAR_SDIO_INT_START(x)			((x) & (~BITS_SDIO_INT_START))
#define BIT_GET_SDIO_INT_START(x)			(((x) >> BIT_SHIFT_SDIO_INT_START) & BIT_MASK_SDIO_INT_START)
#define BIT_SET_SDIO_INT_START(x, v)			(BIT_CLEAR_SDIO_INT_START(x) | BIT_SDIO_INT_START(v))

/* 2 REG_SYS_EEPROM_CTRL			(Offset 0x000A) */

#define BIT_SHIFT_VPDIDX				8
#define BIT_MASK_VPDIDX				0xff
#define BIT_VPDIDX(x)					(((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX)
#define BITS_VPDIDX					(BIT_MASK_VPDIDX << BIT_SHIFT_VPDIDX)
#define BIT_CLEAR_VPDIDX(x)				((x) & (~BITS_VPDIDX))
#define BIT_GET_VPDIDX(x)				(((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX)
#define BIT_SET_VPDIDX(x, v)				(BIT_CLEAR_VPDIDX(x) | BIT_VPDIDX(v))

#define BIT_SHIFT_EEM1_0				6
#define BIT_MASK_EEM1_0				0x3
#define BIT_EEM1_0(x)					(((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0)
#define BITS_EEM1_0					(BIT_MASK_EEM1_0 << BIT_SHIFT_EEM1_0)
#define BIT_CLEAR_EEM1_0(x)				((x) & (~BITS_EEM1_0))
#define BIT_GET_EEM1_0(x)				(((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0)
#define BIT_SET_EEM1_0(x, v)				(BIT_CLEAR_EEM1_0(x) | BIT_EEM1_0(v))

#define BIT_AUTOLOAD_SUS				BIT(5)
#define BIT_EERPOMSEL					BIT(4)
#define BIT_EECS					BIT(3)
#define BIT_EESK					BIT(2)
#define BIT_EEDI					BIT(1)
#define BIT_EEDO					BIT(0)

/* 2 REG_SDIO_MONITOR_2			(Offset 0x1025000C) */

#define BIT_CMD53_WT_EN				BIT(23)

#define BIT_SHIFT_SDIO_CLK_MONITOR			21
#define BIT_MASK_SDIO_CLK_MONITOR			0x3
#define BIT_SDIO_CLK_MONITOR(x)			(((x) & BIT_MASK_SDIO_CLK_MONITOR) << BIT_SHIFT_SDIO_CLK_MONITOR)
#define BITS_SDIO_CLK_MONITOR				(BIT_MASK_SDIO_CLK_MONITOR << BIT_SHIFT_SDIO_CLK_MONITOR)
#define BIT_CLEAR_SDIO_CLK_MONITOR(x)			((x) & (~BITS_SDIO_CLK_MONITOR))
#define BIT_GET_SDIO_CLK_MONITOR(x)			(((x) >> BIT_SHIFT_SDIO_CLK_MONITOR) & BIT_MASK_SDIO_CLK_MONITOR)
#define BIT_SET_SDIO_CLK_MONITOR(x, v)			(BIT_CLEAR_SDIO_CLK_MONITOR(x) | BIT_SDIO_CLK_MONITOR(v))

#define BIT_SHIFT_VPD_DATA				0
#define BIT_MASK_VPD_DATA				0xffffffffL
#define BIT_VPD_DATA(x)				(((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA)
#define BITS_VPD_DATA					(BIT_MASK_VPD_DATA << BIT_SHIFT_VPD_DATA)
#define BIT_CLEAR_VPD_DATA(x)				((x) & (~BITS_VPD_DATA))
#define BIT_GET_VPD_DATA(x)				(((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA)
#define BIT_SET_VPD_DATA(x, v)				(BIT_CLEAR_VPD_DATA(x) | BIT_VPD_DATA(v))

#define BIT_SHIFT_SDIO_CLK_CNT				0
#define BIT_MASK_SDIO_CLK_CNT				0x1fffff
#define BIT_SDIO_CLK_CNT(x)				(((x) & BIT_MASK_SDIO_CLK_CNT) << BIT_SHIFT_SDIO_CLK_CNT)
#define BITS_SDIO_CLK_CNT				(BIT_MASK_SDIO_CLK_CNT << BIT_SHIFT_SDIO_CLK_CNT)
#define BIT_CLEAR_SDIO_CLK_CNT(x)			((x) & (~BITS_SDIO_CLK_CNT))
#define BIT_GET_SDIO_CLK_CNT(x)			(((x) >> BIT_SHIFT_SDIO_CLK_CNT) & BIT_MASK_SDIO_CLK_CNT)
#define BIT_SET_SDIO_CLK_CNT(x, v)			(BIT_CLEAR_SDIO_CLK_CNT(x) | BIT_SDIO_CLK_CNT(v))

/* 2 REG_SYS_SWR_CTRL1			(Offset 0x0010) */

#define BIT_SYM_EN_SWR_DUMMY_LOAD			BIT(20)

#define BIT_SHIFT_PWM_ZCDC_H_LL			18
#define BIT_MASK_PWM_ZCDC_H_LL				0x3
#define BIT_PWM_ZCDC_H_LL(x)				(((x) & BIT_MASK_PWM_ZCDC_H_LL) << BIT_SHIFT_PWM_ZCDC_H_LL)
#define BITS_PWM_ZCDC_H_LL				(BIT_MASK_PWM_ZCDC_H_LL << BIT_SHIFT_PWM_ZCDC_H_LL)
#define BIT_CLEAR_PWM_ZCDC_H_LL(x)			((x) & (~BITS_PWM_ZCDC_H_LL))
#define BIT_GET_PWM_ZCDC_H_LL(x)			(((x) >> BIT_SHIFT_PWM_ZCDC_H_LL) & BIT_MASK_PWM_ZCDC_H_LL)
#define BIT_SET_PWM_ZCDC_H_LL(x, v)			(BIT_CLEAR_PWM_ZCDC_H_LL(x) | BIT_PWM_ZCDC_H_LL(v))

#define BIT_PWM_ZCD_SEL_WL				BIT(17)
#define BIT_OPTION_PWM_FORCE				BIT(16)
#define BIT_SPS_PFM_MOS_HALF				BIT(15)

#define BIT_SHIFT_SPS_PFM_ZCD_H			13
#define BIT_MASK_SPS_PFM_ZCD_H				0x3
#define BIT_SPS_PFM_ZCD_H(x)				(((x) & BIT_MASK_SPS_PFM_ZCD_H) << BIT_SHIFT_SPS_PFM_ZCD_H)
#define BITS_SPS_PFM_ZCD_H				(BIT_MASK_SPS_PFM_ZCD_H << BIT_SHIFT_SPS_PFM_ZCD_H)
#define BIT_CLEAR_SPS_PFM_ZCD_H(x)			((x) & (~BITS_SPS_PFM_ZCD_H))
#define BIT_GET_SPS_PFM_ZCD_H(x)			(((x) >> BIT_SHIFT_SPS_PFM_ZCD_H) & BIT_MASK_SPS_PFM_ZCD_H)
#define BIT_SET_SPS_PFM_ZCD_H(x, v)			(BIT_CLEAR_SPS_PFM_ZCD_H(x) | BIT_SPS_PFM_ZCD_H(v))

#define BIT_ENB_LDO_DIODE				BIT(12)
#define BIT_SW18_PFM_FREQ				BIT(10)
#define BIT_SPS_SWR_EN					BIT(9)
#define BIT_SPS_SLDO_EN				BIT(8)
#define BIT_MAC_ID_EN					BIT(7)

/* 2 REG_SDIO_HIMR				(Offset 0x10250014) */

#define BIT_SDIO_CRCERR_MSK				BIT(31)
#define BIT_SDIO_HSISR3_IND_MSK			BIT(30)
#define BIT_SDIO_HSISR2_IND_MSK			BIT(29)
#define BIT_SDIO_HEISR_IND_MSK				BIT(28)
#define BIT_SDIO_CTWEND_MSK				BIT(27)
#define BIT_SDIO_ATIMEND_E_MSK				BIT(26)
#define BIT_SDIIO_ATIMEND_MSK				BIT(25)
#define BIT_SDIO_OCPINT_MSK				BIT(24)
#define BIT_SDIO_PSTIMEOUT_MSK				BIT(23)
#define BIT_SDIO_GTINT4_MSK				BIT(22)
#define BIT_SDIO_GTINT3_MSK				BIT(21)
#define BIT_SDIO_HSISR_IND_MSK				BIT(20)
#define BIT_SDIO_CPWM2_MSK				BIT(19)
#define BIT_SDIO_CPWM1_MSK				BIT(18)
#define BIT_SDIO_C2HCMD_INT_MSK			BIT(17)
#define BIT_SDIO_BCNERLY_INT_MSK			BIT(16)

#define BIT_SHIFT_BT_SEC_DIS_1				14
#define BIT_MASK_BT_SEC_DIS_1				0x3
#define BIT_BT_SEC_DIS_1(x)				(((x) & BIT_MASK_BT_SEC_DIS_1) << BIT_SHIFT_BT_SEC_DIS_1)
#define BITS_BT_SEC_DIS_1				(BIT_MASK_BT_SEC_DIS_1 << BIT_SHIFT_BT_SEC_DIS_1)
#define BIT_CLEAR_BT_SEC_DIS_1(x)			((x) & (~BITS_BT_SEC_DIS_1))
#define BIT_GET_BT_SEC_DIS_1(x)			(((x) >> BIT_SHIFT_BT_SEC_DIS_1) & BIT_MASK_BT_SEC_DIS_1)
#define BIT_SET_BT_SEC_DIS_1(x, v)			(BIT_CLEAR_BT_SEC_DIS_1(x) | BIT_BT_SEC_DIS_1(v))

#define BIT_SHIFT_BT_SEC_DIS_0				12
#define BIT_MASK_BT_SEC_DIS_0				0x3
#define BIT_BT_SEC_DIS_0(x)				(((x) & BIT_MASK_BT_SEC_DIS_0) << BIT_SHIFT_BT_SEC_DIS_0)
#define BITS_BT_SEC_DIS_0				(BIT_MASK_BT_SEC_DIS_0 << BIT_SHIFT_BT_SEC_DIS_0)
#define BIT_CLEAR_BT_SEC_DIS_0(x)			((x) & (~BITS_BT_SEC_DIS_0))
#define BIT_GET_BT_SEC_DIS_0(x)			(((x) >> BIT_SHIFT_BT_SEC_DIS_0) & BIT_MASK_BT_SEC_DIS_0)
#define BIT_SET_BT_SEC_DIS_0(x, v)			(BIT_CLEAR_BT_SEC_DIS_0(x) | BIT_BT_SEC_DIS_0(v))

#define BIT_SHIFT_UART_RX_EN				10
#define BIT_MASK_UART_RX_EN				0x3
#define BIT_UART_RX_EN(x)				(((x) & BIT_MASK_UART_RX_EN) << BIT_SHIFT_UART_RX_EN)
#define BITS_UART_RX_EN				(BIT_MASK_UART_RX_EN << BIT_SHIFT_UART_RX_EN)
#define BIT_CLEAR_UART_RX_EN(x)			((x) & (~BITS_UART_RX_EN))
#define BIT_GET_UART_RX_EN(x)				(((x) >> BIT_SHIFT_UART_RX_EN) & BIT_MASK_UART_RX_EN)
#define BIT_SET_UART_RX_EN(x, v)			(BIT_CLEAR_UART_RX_EN(x) | BIT_UART_RX_EN(v))

#define BIT_SHIFT_UART_TX_EN				8
#define BIT_MASK_UART_TX_EN				0x3
#define BIT_UART_TX_EN(x)				(((x) & BIT_MASK_UART_TX_EN) << BIT_SHIFT_UART_TX_EN)
#define BITS_UART_TX_EN				(BIT_MASK_UART_TX_EN << BIT_SHIFT_UART_TX_EN)
#define BIT_CLEAR_UART_TX_EN(x)			((x) & (~BITS_UART_TX_EN))
#define BIT_GET_UART_TX_EN(x)				(((x) >> BIT_SHIFT_UART_TX_EN) & BIT_MASK_UART_TX_EN)
#define BIT_SET_UART_TX_EN(x, v)			(BIT_CLEAR_UART_TX_EN(x) | BIT_UART_TX_EN(v))

#define BIT_BT_INT_MASK				BIT(8)
#define BIT_SDIO_TXBCNERR_MSK				BIT(7)

#define BIT_SHIFT_KEY_NUM_SEL				6
#define BIT_MASK_KEY_NUM_SEL				0x3
#define BIT_KEY_NUM_SEL(x)				(((x) & BIT_MASK_KEY_NUM_SEL) << BIT_SHIFT_KEY_NUM_SEL)
#define BITS_KEY_NUM_SEL				(BIT_MASK_KEY_NUM_SEL << BIT_SHIFT_KEY_NUM_SEL)
#define BIT_CLEAR_KEY_NUM_SEL(x)			((x) & (~BITS_KEY_NUM_SEL))
#define BIT_GET_KEY_NUM_SEL(x)				(((x) >> BIT_SHIFT_KEY_NUM_SEL) & BIT_MASK_KEY_NUM_SEL)
#define BIT_SET_KEY_NUM_SEL(x, v)			(BIT_CLEAR_KEY_NUM_SEL(x) | BIT_KEY_NUM_SEL(v))

#define BIT_SDIO_TXBCNOK_MSK				BIT(6)
#define BIT_COMP_EN					BIT(5)
#define BIT_SDIO_RXFOVW_MSK				BIT(5)
#define BIT_BT_JTAG_EN					BIT(4)
#define BIT_SDIO_TXFOVW_MSK				BIT(4)
#define BIT_SDIO_RXERR_MSK				BIT(3)

#define BIT_SHIFT_SIC_EN				2
#define BIT_MASK_SIC_EN				0x3
#define BIT_SIC_EN(x)					(((x) & BIT_MASK_SIC_EN) << BIT_SHIFT_SIC_EN)
#define BITS_SIC_EN					(BIT_MASK_SIC_EN << BIT_SHIFT_SIC_EN)
#define BIT_CLEAR_SIC_EN(x)				((x) & (~BITS_SIC_EN))
#define BIT_GET_SIC_EN(x)				(((x) >> BIT_SHIFT_SIC_EN) & BIT_MASK_SIC_EN)
#define BIT_SET_SIC_EN(x, v)				(BIT_CLEAR_SIC_EN(x) | BIT_SIC_EN(v))

#define BIT_SDIO_TXERR_MSK				BIT(2)
#define BIT_SDIO_AVAL_MSK				BIT(1)

#define BIT_SHIFT_SEC_DIS				0
#define BIT_MASK_SEC_DIS				0x3
#define BIT_SEC_DIS(x)					(((x) & BIT_MASK_SEC_DIS) << BIT_SHIFT_SEC_DIS)
#define BITS_SEC_DIS					(BIT_MASK_SEC_DIS << BIT_SHIFT_SEC_DIS)
#define BIT_CLEAR_SEC_DIS(x)				((x) & (~BITS_SEC_DIS))
#define BIT_GET_SEC_DIS(x)				(((x) >> BIT_SHIFT_SEC_DIS) & BIT_MASK_SEC_DIS)
#define BIT_SET_SEC_DIS(x, v)				(BIT_CLEAR_SEC_DIS(x) | BIT_SEC_DIS(v))

#define BIT_RX_REQUEST_MSK				BIT(0)

/* 2 REG_SYS_SWR_OCP_CFG			(Offset 0x0018) */

#define BIT_SPS18_OCP_DIS				BIT(31)
#define BIT_SDIO_CRCERR				BIT(31)
#define BIT_SDIO_HSISR3_IND				BIT(30)
#define BIT_SDIO_HSISR2_IND				BIT(29)
#define BIT_SDIO_HEISR_IND				BIT(28)
#define BIT_SDIO_CTWEND				BIT(27)
#define BIT_SDIO_ATIMEND_E				BIT(26)
#define BIT_SDIO_ATIMEND				BIT(25)
#define BIT_SDIO_OCPINT				BIT(24)
#define BIT_SDIO_PSTIMEOUT				BIT(23)
#define BIT_SDIO_GTINT4				BIT(22)
#define BIT_SDIO_GTINT3				BIT(21)
#define BIT_SDIO_HSISR_IND				BIT(20)
#define BIT_SDIO_CPWM2					BIT(19)
#define BIT_SDIO_CPWM1					BIT(18)
#define BIT_SDIO_C2HCMD_INT				BIT(17)

#define BIT_SHIFT_SPS18_OCP_TH				16
#define BIT_MASK_SPS18_OCP_TH				0x7fff
#define BIT_SPS18_OCP_TH(x)				(((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH)
#define BITS_SPS18_OCP_TH				(BIT_MASK_SPS18_OCP_TH << BIT_SHIFT_SPS18_OCP_TH)
#define BIT_CLEAR_SPS18_OCP_TH(x)			((x) & (~BITS_SPS18_OCP_TH))
#define BIT_GET_SPS18_OCP_TH(x)			(((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH)
#define BIT_SET_SPS18_OCP_TH(x, v)			(BIT_CLEAR_SPS18_OCP_TH(x) | BIT_SPS18_OCP_TH(v))

#define BIT_SDIO_BCNERLY_INT				BIT(16)
#define BIT_BT_INT					BIT(8)
#define BIT_SDIO_TXBCNERR				BIT(7)
#define BIT_SDIO_TXBCNOK				BIT(6)
#define BIT_SDIO_RXFOVW				BIT(5)
#define BIT_SDIO_TXFOVW				BIT(4)
#define BIT_SDIO_RXERR					BIT(3)
#define BIT_SDIO_TXERR					BIT(2)
#define BIT_SDIO_AVAL					BIT(1)

#define BIT_SHIFT_OCP_WINDOW				0
#define BIT_MASK_OCP_WINDOW				0xffff
#define BIT_OCP_WINDOW(x)				(((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW)
#define BITS_OCP_WINDOW				(BIT_MASK_OCP_WINDOW << BIT_SHIFT_OCP_WINDOW)
#define BIT_CLEAR_OCP_WINDOW(x)			((x) & (~BITS_OCP_WINDOW))
#define BIT_GET_OCP_WINDOW(x)				(((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW)
#define BIT_SET_OCP_WINDOW(x, v)			(BIT_CLEAR_OCP_WINDOW(x) | BIT_OCP_WINDOW(v))

#define BIT_RX_REQUEST					BIT(0)

/* 2 REG_REG_ACCESS_CTRL			(Offset 0x001C) */

#define BIT_HREG_DBG					BIT(23)
#define BIT_WLMCUIOIF					BIT(8)
#define BIT_LOCK_ALL_EN				BIT(7)
#define BIT_R_DIS_PRST					BIT(6)
#define BIT_WLOCK_1C_B6				BIT(5)
#define BIT_WLOCK_40					BIT(4)
#define BIT_WLOCK_08					BIT(3)
#define BIT_WLOCK_04					BIT(2)
#define BIT_WLOCK_00					BIT(1)
#define BIT_WLOCK_ALL					BIT(0)

#define BIT_SHIFT_RX_REQ_LEN_V1			0
#define BIT_MASK_RX_REQ_LEN_V1				0x3ffff
#define BIT_RX_REQ_LEN_V1(x)				(((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1)
#define BITS_RX_REQ_LEN_V1				(BIT_MASK_RX_REQ_LEN_V1 << BIT_SHIFT_RX_REQ_LEN_V1)
#define BIT_CLEAR_RX_REQ_LEN_V1(x)			((x) & (~BITS_RX_REQ_LEN_V1))
#define BIT_GET_RX_REQ_LEN_V1(x)			(((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1)
#define BIT_SET_RX_REQ_LEN_V1(x, v)			(BIT_CLEAR_RX_REQ_LEN_V1(x) | BIT_RX_REQ_LEN_V1(v))

/* 2 REG_RF_CTRL				(Offset 0x001F) */

#define BIT_RF_RCK_CK_GATED				BIT(4)
#define BIT_RF_SDMRSTB					BIT(2)
#define BIT_RF_RSTB					BIT(1)
#define BIT_RF_EN					BIT(0)

#define BIT_SHIFT_FREE_TXPG_SEQ			0
#define BIT_MASK_FREE_TXPG_SEQ				0xff
#define BIT_FREE_TXPG_SEQ(x)				(((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ)
#define BITS_FREE_TXPG_SEQ				(BIT_MASK_FREE_TXPG_SEQ << BIT_SHIFT_FREE_TXPG_SEQ)
#define BIT_CLEAR_FREE_TXPG_SEQ(x)			((x) & (~BITS_FREE_TXPG_SEQ))
#define BIT_GET_FREE_TXPG_SEQ(x)			(((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ)
#define BIT_SET_FREE_TXPG_SEQ(x, v)			(BIT_CLEAR_FREE_TXPG_SEQ(x) | BIT_FREE_TXPG_SEQ(v))

/* 2 REG_SPS_LDO_VOLT_CTRL			(Offset 0x0020) */

#define BIT_SHIFT_SML_LDO_LPS_VOLT			28
#define BIT_MASK_SML_LDO_LPS_VOLT			0xf
#define BIT_SML_LDO_LPS_VOLT(x)			(((x) & BIT_MASK_SML_LDO_LPS_VOLT) << BIT_SHIFT_SML_LDO_LPS_VOLT)
#define BITS_SML_LDO_LPS_VOLT				(BIT_MASK_SML_LDO_LPS_VOLT << BIT_SHIFT_SML_LDO_LPS_VOLT)
#define BIT_CLEAR_SML_LDO_LPS_VOLT(x)			((x) & (~BITS_SML_LDO_LPS_VOLT))
#define BIT_GET_SML_LDO_LPS_VOLT(x)			(((x) >> BIT_SHIFT_SML_LDO_LPS_VOLT) & BIT_MASK_SML_LDO_LPS_VOLT)
#define BIT_SET_SML_LDO_LPS_VOLT(x, v)			(BIT_CLEAR_SML_LDO_LPS_VOLT(x) | BIT_SML_LDO_LPS_VOLT(v))

#define BIT_SHIFT_PHYDIG_LDO_SUS_VOLT			24
#define BIT_MASK_PHYDIG_LDO_SUS_VOLT			0xf
#define BIT_PHYDIG_LDO_SUS_VOLT(x)			(((x) & BIT_MASK_PHYDIG_LDO_SUS_VOLT) << BIT_SHIFT_PHYDIG_LDO_SUS_VOLT)
#define BITS_PHYDIG_LDO_SUS_VOLT			(BIT_MASK_PHYDIG_LDO_SUS_VOLT << BIT_SHIFT_PHYDIG_LDO_SUS_VOLT)
#define BIT_CLEAR_PHYDIG_LDO_SUS_VOLT(x)		((x) & (~BITS_PHYDIG_LDO_SUS_VOLT))
#define BIT_GET_PHYDIG_LDO_SUS_VOLT(x)			(((x) >> BIT_SHIFT_PHYDIG_LDO_SUS_VOLT) & BIT_MASK_PHYDIG_LDO_SUS_VOLT)
#define BIT_SET_PHYDIG_LDO_SUS_VOLT(x, v)		(BIT_CLEAR_PHYDIG_LDO_SUS_VOLT(x) | BIT_PHYDIG_LDO_SUS_VOLT(v))

#define BIT_SHIFT_WLOFF_LDO_LPS_VOLT			20
#define BIT_MASK_WLOFF_LDO_LPS_VOLT			0xf
#define BIT_WLOFF_LDO_LPS_VOLT(x)			(((x) & BIT_MASK_WLOFF_LDO_LPS_VOLT) << BIT_SHIFT_WLOFF_LDO_LPS_VOLT)
#define BITS_WLOFF_LDO_LPS_VOLT			(BIT_MASK_WLOFF_LDO_LPS_VOLT << BIT_SHIFT_WLOFF_LDO_LPS_VOLT)
#define BIT_CLEAR_WLOFF_LDO_LPS_VOLT(x)		((x) & (~BITS_WLOFF_LDO_LPS_VOLT))
#define BIT_GET_WLOFF_LDO_LPS_VOLT(x)			(((x) >> BIT_SHIFT_WLOFF_LDO_LPS_VOLT) & BIT_MASK_WLOFF_LDO_LPS_VOLT)
#define BIT_SET_WLOFF_LDO_LPS_VOLT(x, v)		(BIT_CLEAR_WLOFF_LDO_LPS_VOLT(x) | BIT_WLOFF_LDO_LPS_VOLT(v))

#define BIT_SHIFT_WLPON_LDO_LPS_VOLT			16
#define BIT_MASK_WLPON_LDO_LPS_VOLT			0xf
#define BIT_WLPON_LDO_LPS_VOLT(x)			(((x) & BIT_MASK_WLPON_LDO_LPS_VOLT) << BIT_SHIFT_WLPON_LDO_LPS_VOLT)
#define BITS_WLPON_LDO_LPS_VOLT			(BIT_MASK_WLPON_LDO_LPS_VOLT << BIT_SHIFT_WLPON_LDO_LPS_VOLT)
#define BIT_CLEAR_WLPON_LDO_LPS_VOLT(x)		((x) & (~BITS_WLPON_LDO_LPS_VOLT))
#define BIT_GET_WLPON_LDO_LPS_VOLT(x)			(((x) >> BIT_SHIFT_WLPON_LDO_LPS_VOLT) & BIT_MASK_WLPON_LDO_LPS_VOLT)
#define BIT_SET_WLPON_LDO_LPS_VOLT(x, v)		(BIT_CLEAR_WLPON_LDO_LPS_VOLT(x) | BIT_WLPON_LDO_LPS_VOLT(v))

#define BIT_SHIFT_MID_FREEPG_V1			16
#define BIT_MASK_MID_FREEPG_V1				0xfff
#define BIT_MID_FREEPG_V1(x)				(((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1)
#define BITS_MID_FREEPG_V1				(BIT_MASK_MID_FREEPG_V1 << BIT_SHIFT_MID_FREEPG_V1)
#define BIT_CLEAR_MID_FREEPG_V1(x)			((x) & (~BITS_MID_FREEPG_V1))
#define BIT_GET_MID_FREEPG_V1(x)			(((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1)
#define BIT_SET_MID_FREEPG_V1(x, v)			(BIT_CLEAR_MID_FREEPG_V1(x) | BIT_MID_FREEPG_V1(v))

#define BIT_SHIFT_AON_LDO_SUS_VOLT			12
#define BIT_MASK_AON_LDO_SUS_VOLT			0xf
#define BIT_AON_LDO_SUS_VOLT(x)			(((x) & BIT_MASK_AON_LDO_SUS_VOLT) << BIT_SHIFT_AON_LDO_SUS_VOLT)
#define BITS_AON_LDO_SUS_VOLT				(BIT_MASK_AON_LDO_SUS_VOLT << BIT_SHIFT_AON_LDO_SUS_VOLT)
#define BIT_CLEAR_AON_LDO_SUS_VOLT(x)			((x) & (~BITS_AON_LDO_SUS_VOLT))
#define BIT_GET_AON_LDO_SUS_VOLT(x)			(((x) >> BIT_SHIFT_AON_LDO_SUS_VOLT) & BIT_MASK_AON_LDO_SUS_VOLT)
#define BIT_SET_AON_LDO_SUS_VOLT(x, v)			(BIT_CLEAR_AON_LDO_SUS_VOLT(x) | BIT_AON_LDO_SUS_VOLT(v))

#define BIT_SHIFT_AON_LDO_LPS_VOLT			8
#define BIT_MASK_AON_LDO_LPS_VOLT			0xf
#define BIT_AON_LDO_LPS_VOLT(x)			(((x) & BIT_MASK_AON_LDO_LPS_VOLT) << BIT_SHIFT_AON_LDO_LPS_VOLT)
#define BITS_AON_LDO_LPS_VOLT				(BIT_MASK_AON_LDO_LPS_VOLT << BIT_SHIFT_AON_LDO_LPS_VOLT)
#define BIT_CLEAR_AON_LDO_LPS_VOLT(x)			((x) & (~BITS_AON_LDO_LPS_VOLT))
#define BIT_GET_AON_LDO_LPS_VOLT(x)			(((x) >> BIT_SHIFT_AON_LDO_LPS_VOLT) & BIT_MASK_AON_LDO_LPS_VOLT)
#define BIT_SET_AON_LDO_LPS_VOLT(x, v)			(BIT_CLEAR_AON_LDO_LPS_VOLT(x) | BIT_AON_LDO_LPS_VOLT(v))

#define BIT_PHYDIG_LDO_VOLT_FLAG			BIT(6)
#define BIT_SWR_PFM_VOLT_FLAG				BIT(5)
#define BIT_LRG_LDO_VOLT_FLAG				BIT(4)
#define BIT_SML_LDO_VOLT_FLAG				BIT(3)
#define BIT_WLOFF_LDO_VOLT_FLAG			BIT(2)
#define BIT_WLPON_LDO_VOLT_FLAG			BIT(1)
#define BIT_AON_LDO_VOLT_FLAG				BIT(0)

#define BIT_SHIFT_HIQ_FREEPG_V1			0
#define BIT_MASK_HIQ_FREEPG_V1				0xfff
#define BIT_HIQ_FREEPG_V1(x)				(((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1)
#define BITS_HIQ_FREEPG_V1				(BIT_MASK_HIQ_FREEPG_V1 << BIT_SHIFT_HIQ_FREEPG_V1)
#define BIT_CLEAR_HIQ_FREEPG_V1(x)			((x) & (~BITS_HIQ_FREEPG_V1))
#define BIT_GET_HIQ_FREEPG_V1(x)			(((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1)
#define BIT_SET_HIQ_FREEPG_V1(x, v)			(BIT_CLEAR_HIQ_FREEPG_V1(x) | BIT_HIQ_FREEPG_V1(v))

/* 2 REG_SPS_LDO_VOLT_CTRL1			(Offset 0x0024) */

#define BIT_POW_XTAL_LPS_EN				BIT(26)
#define BIT_POW_XTAL					BIT(25)

#define BIT_SHIFT_SPSLDO_STEP_DELAY			24
#define BIT_MASK_SPSLDO_STEP_DELAY			0xff
#define BIT_SPSLDO_STEP_DELAY(x)			(((x) & BIT_MASK_SPSLDO_STEP_DELAY) << BIT_SHIFT_SPSLDO_STEP_DELAY)
#define BITS_SPSLDO_STEP_DELAY				(BIT_MASK_SPSLDO_STEP_DELAY << BIT_SHIFT_SPSLDO_STEP_DELAY)
#define BIT_CLEAR_SPSLDO_STEP_DELAY(x)			((x) & (~BITS_SPSLDO_STEP_DELAY))
#define BIT_GET_SPSLDO_STEP_DELAY(x)			(((x) >> BIT_SHIFT_SPSLDO_STEP_DELAY) & BIT_MASK_SPSLDO_STEP_DELAY)
#define BIT_SET_SPSLDO_STEP_DELAY(x, v)		(BIT_CLEAR_SPSLDO_STEP_DELAY(x) | BIT_SPSLDO_STEP_DELAY(v))

#define BIT_POW_BG					BIT(24)
#define BIT_XTAL_XORES_SEL				BIT(23)
#define BIT_SYM_SW_ADJ_BTLDO				BIT(22)
#define BIT_POW_REGU_P1				BIT(22)
#define BIT_POW_REGU_P0				BIT(21)

#define BIT_SHIFT_MAC_CLK_SEL				20
#define BIT_MASK_MAC_CLK_SEL				0x3
#define BIT_MAC_CLK_SEL(x)				(((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL)
#define BITS_MAC_CLK_SEL				(BIT_MASK_MAC_CLK_SEL << BIT_SHIFT_MAC_CLK_SEL)
#define BIT_CLEAR_MAC_CLK_SEL(x)			((x) & (~BITS_MAC_CLK_SEL))
#define BIT_GET_MAC_CLK_SEL(x)				(((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL)
#define BIT_SET_MAC_CLK_SEL(x, v)			(BIT_CLEAR_MAC_CLK_SEL(x) | BIT_MAC_CLK_SEL(v))

#define BIT_POW_PLL_200				BIT(20)
#define BIT_POW_PLL					BIT(19)
#define BIT_POW_PLL_LDO				BIT(18)
#define BIT_POW_XTAL_NC				BIT(17)

#define BIT_SHIFT_SYM_AON_LDO_PDN_VOLT			16
#define BIT_MASK_SYM_AON_LDO_PDN_VOLT			0xf
#define BIT_SYM_AON_LDO_PDN_VOLT(x)			(((x) & BIT_MASK_SYM_AON_LDO_PDN_VOLT) << BIT_SHIFT_SYM_AON_LDO_PDN_VOLT)
#define BITS_SYM_AON_LDO_PDN_VOLT			(BIT_MASK_SYM_AON_LDO_PDN_VOLT << BIT_SHIFT_SYM_AON_LDO_PDN_VOLT)
#define BIT_CLEAR_SYM_AON_LDO_PDN_VOLT(x)		((x) & (~BITS_SYM_AON_LDO_PDN_VOLT))
#define BIT_GET_SYM_AON_LDO_PDN_VOLT(x)		(((x) >> BIT_SHIFT_SYM_AON_LDO_PDN_VOLT) & BIT_MASK_SYM_AON_LDO_PDN_VOLT)
#define BIT_SET_SYM_AON_LDO_PDN_VOLT(x, v)		(BIT_CLEAR_SYM_AON_LDO_PDN_VOLT(x) | BIT_SYM_AON_LDO_PDN_VOLT(v))

#define BIT_POW_BG_NC					BIT(16)

#define BIT_SHIFT_PUB_FREEPG_V1			16
#define BIT_MASK_PUB_FREEPG_V1				0xfff
#define BIT_PUB_FREEPG_V1(x)				(((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1)
#define BITS_PUB_FREEPG_V1				(BIT_MASK_PUB_FREEPG_V1 << BIT_SHIFT_PUB_FREEPG_V1)
#define BIT_CLEAR_PUB_FREEPG_V1(x)			((x) & (~BITS_PUB_FREEPG_V1))
#define BIT_GET_PUB_FREEPG_V1(x)			(((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1)
#define BIT_SET_PUB_FREEPG_V1(x, v)			(BIT_CLEAR_PUB_FREEPG_V1(x) | BIT_PUB_FREEPG_V1(v))

#define BIT_EN_PCIE_BG					BIT(15)
#define BIT_EN_USB_BG					BIT(14)
#define BIT_USB_APHY_POR				BIT(13)

#define BIT_SHIFT_SWR_PFM_SUS_VOLT			12
#define BIT_MASK_SWR_PFM_SUS_VOLT			0xf
#define BIT_SWR_PFM_SUS_VOLT(x)			(((x) & BIT_MASK_SWR_PFM_SUS_VOLT) << BIT_SHIFT_SWR_PFM_SUS_VOLT)
#define BITS_SWR_PFM_SUS_VOLT				(BIT_MASK_SWR_PFM_SUS_VOLT << BIT_SHIFT_SWR_PFM_SUS_VOLT)
#define BIT_CLEAR_SWR_PFM_SUS_VOLT(x)			((x) & (~BITS_SWR_PFM_SUS_VOLT))
#define BIT_GET_SWR_PFM_SUS_VOLT(x)			(((x) >> BIT_SHIFT_SWR_PFM_SUS_VOLT) & BIT_MASK_SWR_PFM_SUS_VOLT)
#define BIT_SET_SWR_PFM_SUS_VOLT(x, v)			(BIT_CLEAR_SWR_PFM_SUS_VOLT(x) | BIT_SWR_PFM_SUS_VOLT(v))

#define BIT_SHIFT_SWR_PFM_LPS_VOLT			8
#define BIT_MASK_SWR_PFM_LPS_VOLT			0xf
#define BIT_SWR_PFM_LPS_VOLT(x)			(((x) & BIT_MASK_SWR_PFM_LPS_VOLT) << BIT_SHIFT_SWR_PFM_LPS_VOLT)
#define BITS_SWR_PFM_LPS_VOLT				(BIT_MASK_SWR_PFM_LPS_VOLT << BIT_SHIFT_SWR_PFM_LPS_VOLT)
#define BIT_CLEAR_SWR_PFM_LPS_VOLT(x)			((x) & (~BITS_SWR_PFM_LPS_VOLT))
#define BIT_GET_SWR_PFM_LPS_VOLT(x)			(((x) >> BIT_SHIFT_SWR_PFM_LPS_VOLT) & BIT_MASK_SWR_PFM_LPS_VOLT)
#define BIT_SET_SWR_PFM_LPS_VOLT(x, v)			(BIT_CLEAR_SWR_PFM_LPS_VOLT(x) | BIT_SWR_PFM_LPS_VOLT(v))

#define BIT_SHIFT_LARGE_LDO_LPS_VOLT			4
#define BIT_MASK_LARGE_LDO_LPS_VOLT			0xf
#define BIT_LARGE_LDO_LPS_VOLT(x)			(((x) & BIT_MASK_LARGE_LDO_LPS_VOLT) << BIT_SHIFT_LARGE_LDO_LPS_VOLT)
#define BITS_LARGE_LDO_LPS_VOLT			(BIT_MASK_LARGE_LDO_LPS_VOLT << BIT_SHIFT_LARGE_LDO_LPS_VOLT)
#define BIT_CLEAR_LARGE_LDO_LPS_VOLT(x)		((x) & (~BITS_LARGE_LDO_LPS_VOLT))
#define BIT_GET_LARGE_LDO_LPS_VOLT(x)			(((x) >> BIT_SHIFT_LARGE_LDO_LPS_VOLT) & BIT_MASK_LARGE_LDO_LPS_VOLT)
#define BIT_SET_LARGE_LDO_LPS_VOLT(x, v)		(BIT_CLEAR_LARGE_LDO_LPS_VOLT(x) | BIT_LARGE_LDO_LPS_VOLT(v))

#define BIT_SHIFT_SML_LDO_SUS_VOLT			0
#define BIT_MASK_SML_LDO_SUS_VOLT			0xf
#define BIT_SML_LDO_SUS_VOLT(x)			(((x) & BIT_MASK_SML_LDO_SUS_VOLT) << BIT_SHIFT_SML_LDO_SUS_VOLT)
#define BITS_SML_LDO_SUS_VOLT				(BIT_MASK_SML_LDO_SUS_VOLT << BIT_SHIFT_SML_LDO_SUS_VOLT)
#define BIT_CLEAR_SML_LDO_SUS_VOLT(x)			((x) & (~BITS_SML_LDO_SUS_VOLT))
#define BIT_GET_SML_LDO_SUS_VOLT(x)			(((x) >> BIT_SHIFT_SML_LDO_SUS_VOLT) & BIT_MASK_SML_LDO_SUS_VOLT)
#define BIT_SET_SML_LDO_SUS_VOLT(x, v)			(BIT_CLEAR_SML_LDO_SUS_VOLT(x) | BIT_SML_LDO_SUS_VOLT(v))

#define BIT_SHIFT_LOW_FREEPG_V1			0
#define BIT_MASK_LOW_FREEPG_V1				0xfff
#define BIT_LOW_FREEPG_V1(x)				(((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1)
#define BITS_LOW_FREEPG_V1				(BIT_MASK_LOW_FREEPG_V1 << BIT_SHIFT_LOW_FREEPG_V1)
#define BIT_CLEAR_LOW_FREEPG_V1(x)			((x) & (~BITS_LOW_FREEPG_V1))
#define BIT_GET_LOW_FREEPG_V1(x)			(((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1)
#define BIT_SET_LOW_FREEPG_V1(x, v)			(BIT_CLEAR_LOW_FREEPG_V1(x) | BIT_LOW_FREEPG_V1(v))

/* 2 REG_SDIO_OQT_FREE_TXPG_V1		(Offset 0x10250028) */

#define BIT_SHIFT_NOAC_OQT_FREEPG_V1			24
#define BIT_MASK_NOAC_OQT_FREEPG_V1			0xff
#define BIT_NOAC_OQT_FREEPG_V1(x)			(((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1)
#define BITS_NOAC_OQT_FREEPG_V1			(BIT_MASK_NOAC_OQT_FREEPG_V1 << BIT_SHIFT_NOAC_OQT_FREEPG_V1)
#define BIT_CLEAR_NOAC_OQT_FREEPG_V1(x)		((x) & (~BITS_NOAC_OQT_FREEPG_V1))
#define BIT_GET_NOAC_OQT_FREEPG_V1(x)			(((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1)
#define BIT_SET_NOAC_OQT_FREEPG_V1(x, v)		(BIT_CLEAR_NOAC_OQT_FREEPG_V1(x) | BIT_NOAC_OQT_FREEPG_V1(v))

#define BIT_SHIFT_AC_OQT_FREEPG_V1			16
#define BIT_MASK_AC_OQT_FREEPG_V1			0xff
#define BIT_AC_OQT_FREEPG_V1(x)			(((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1)
#define BITS_AC_OQT_FREEPG_V1				(BIT_MASK_AC_OQT_FREEPG_V1 << BIT_SHIFT_AC_OQT_FREEPG_V1)
#define BIT_CLEAR_AC_OQT_FREEPG_V1(x)			((x) & (~BITS_AC_OQT_FREEPG_V1))
#define BIT_GET_AC_OQT_FREEPG_V1(x)			(((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1)
#define BIT_SET_AC_OQT_FREEPG_V1(x, v)			(BIT_CLEAR_AC_OQT_FREEPG_V1(x) | BIT_AC_OQT_FREEPG_V1(v))

#define BIT_SHIFT_EXQ_FREEPG_V1			0
#define BIT_MASK_EXQ_FREEPG_V1				0xfff
#define BIT_EXQ_FREEPG_V1(x)				(((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1)
#define BITS_EXQ_FREEPG_V1				(BIT_MASK_EXQ_FREEPG_V1 << BIT_SHIFT_EXQ_FREEPG_V1)
#define BIT_CLEAR_EXQ_FREEPG_V1(x)			((x) & (~BITS_EXQ_FREEPG_V1))
#define BIT_GET_EXQ_FREEPG_V1(x)			(((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1)
#define BIT_SET_EXQ_FREEPG_V1(x, v)			(BIT_CLEAR_EXQ_FREEPG_V1(x) | BIT_EXQ_FREEPG_V1(v))

/* 2 REG_LDO_CTRL0				(Offset 0x002C) */

#define BIT_SYM_UPD_LRG_LDO_ACT_VOLT			BIT(31)
#define BIT_SYM_UPD_SML_LDO_ACT_VOLT			BIT(30)
#define BIT_SYM_UPD_SWR_PFM_ACT_VOLT			BIT(29)
#define BIT_SYM_UPD_AON_LDO_ACT_VOLT			BIT(28)

#define BIT_SHIFT_REG_CC_WL_PON_L			22
#define BIT_MASK_REG_CC_WL_PON_L			0x3
#define BIT_REG_CC_WL_PON_L(x)				(((x) & BIT_MASK_REG_CC_WL_PON_L) << BIT_SHIFT_REG_CC_WL_PON_L)
#define BITS_REG_CC_WL_PON_L				(BIT_MASK_REG_CC_WL_PON_L << BIT_SHIFT_REG_CC_WL_PON_L)
#define BIT_CLEAR_REG_CC_WL_PON_L(x)			((x) & (~BITS_REG_CC_WL_PON_L))
#define BIT_GET_REG_CC_WL_PON_L(x)			(((x) >> BIT_SHIFT_REG_CC_WL_PON_L) & BIT_MASK_REG_CC_WL_PON_L)
#define BIT_SET_REG_CC_WL_PON_L(x, v)			(BIT_CLEAR_REG_CC_WL_PON_L(x) | BIT_REG_CC_WL_PON_L(v))

#define BIT_REG_STANDBY_WL_PON_L			BIT(21)
#define BIT_POW_LDO_WL_PON				BIT(20)

#define BIT_SHIFT_REG_RES_WL_L				18
#define BIT_MASK_REG_RES_WL_L				0x3
#define BIT_REG_RES_WL_L(x)				(((x) & BIT_MASK_REG_RES_WL_L) << BIT_SHIFT_REG_RES_WL_L)
#define BITS_REG_RES_WL_L				(BIT_MASK_REG_RES_WL_L << BIT_SHIFT_REG_RES_WL_L)
#define BIT_CLEAR_REG_RES_WL_L(x)			((x) & (~BITS_REG_RES_WL_L))
#define BIT_GET_REG_RES_WL_L(x)			(((x) >> BIT_SHIFT_REG_RES_WL_L) & BIT_MASK_REG_RES_WL_L)
#define BIT_SET_REG_RES_WL_L(x, v)			(BIT_CLEAR_REG_RES_WL_L(x) | BIT_REG_RES_WL_L(v))

#define BIT_SHIFT_REG_BIAS_WL_L			16
#define BIT_MASK_REG_BIAS_WL_L				0x3
#define BIT_REG_BIAS_WL_L(x)				(((x) & BIT_MASK_REG_BIAS_WL_L) << BIT_SHIFT_REG_BIAS_WL_L)
#define BITS_REG_BIAS_WL_L				(BIT_MASK_REG_BIAS_WL_L << BIT_SHIFT_REG_BIAS_WL_L)
#define BIT_CLEAR_REG_BIAS_WL_L(x)			((x) & (~BITS_REG_BIAS_WL_L))
#define BIT_GET_REG_BIAS_WL_L(x)			(((x) >> BIT_SHIFT_REG_BIAS_WL_L) & BIT_MASK_REG_BIAS_WL_L)
#define BIT_SET_REG_BIAS_WL_L(x, v)			(BIT_CLEAR_REG_BIAS_WL_L(x) | BIT_REG_BIAS_WL_L(v))

#define BIT_SHIFT_LDOD_V12ADJ_WL_L			12
#define BIT_MASK_LDOD_V12ADJ_WL_L			0xf
#define BIT_LDOD_V12ADJ_WL_L(x)			(((x) & BIT_MASK_LDOD_V12ADJ_WL_L) << BIT_SHIFT_LDOD_V12ADJ_WL_L)
#define BITS_LDOD_V12ADJ_WL_L				(BIT_MASK_LDOD_V12ADJ_WL_L << BIT_SHIFT_LDOD_V12ADJ_WL_L)
#define BIT_CLEAR_LDOD_V12ADJ_WL_L(x)			((x) & (~BITS_LDOD_V12ADJ_WL_L))
#define BIT_GET_LDOD_V12ADJ_WL_L(x)			(((x) >> BIT_SHIFT_LDOD_V12ADJ_WL_L) & BIT_MASK_LDOD_V12ADJ_WL_L)
#define BIT_SET_LDOD_V12ADJ_WL_L(x, v)			(BIT_CLEAR_LDOD_V12ADJ_WL_L(x) | BIT_LDOD_V12ADJ_WL_L(v))

#define BIT_SDIO_BCNQ_EMPTY				BIT(11)

#define BIT_SHIFT_REG_CC_WL_L				10
#define BIT_MASK_REG_CC_WL_L				0x3
#define BIT_REG_CC_WL_L(x)				(((x) & BIT_MASK_REG_CC_WL_L) << BIT_SHIFT_REG_CC_WL_L)
#define BITS_REG_CC_WL_L				(BIT_MASK_REG_CC_WL_L << BIT_SHIFT_REG_CC_WL_L)
#define BIT_CLEAR_REG_CC_WL_L(x)			((x) & (~BITS_REG_CC_WL_L))
#define BIT_GET_REG_CC_WL_L(x)				(((x) >> BIT_SHIFT_REG_CC_WL_L) & BIT_MASK_REG_CC_WL_L)
#define BIT_SET_REG_CC_WL_L(x, v)			(BIT_CLEAR_REG_CC_WL_L(x) | BIT_REG_CC_WL_L(v))

#define BIT_SDIO_HQQ_EMPTY				BIT(10)
#define BIT_REG_STANDBY_WL_L				BIT(9)
#define BIT_SDIO_MQQ_EMPTY				BIT(9)
#define BIT_POW_LDO_WL					BIT(8)
#define BIT_SDIO_MGQ_CPU_EMPTY				BIT(8)
#define BIT_SDIO_AC7Q_EMPTY				BIT(7)
#define BIT_CK12M_EN					BIT(6)
#define BIT_SDIO_AC6Q_EMPTY				BIT(6)
#define BIT_REG_CK_SEL					BIT(5)
#define BIT_SDIO_AC5Q_EMPTY				BIT(5)
#define BIT_EN_SLEEP_L					BIT(4)
#define BIT_SDIO_AC4Q_EMPTY				BIT(4)
#define BIT_SDIO_AC3Q_EMPTY				BIT(3)
#define BIT_SDIO_AC2Q_EMPTY				BIT(2)
#define BIT_SDIO_AC1Q_EMPTY				BIT(1)

#define BIT_SHIFT_LDOH12_V12ADJ_L			0
#define BIT_MASK_LDOH12_V12ADJ_L			0xf
#define BIT_LDOH12_V12ADJ_L(x)				(((x) & BIT_MASK_LDOH12_V12ADJ_L) << BIT_SHIFT_LDOH12_V12ADJ_L)
#define BITS_LDOH12_V12ADJ_L				(BIT_MASK_LDOH12_V12ADJ_L << BIT_SHIFT_LDOH12_V12ADJ_L)
#define BIT_CLEAR_LDOH12_V12ADJ_L(x)			((x) & (~BITS_LDOH12_V12ADJ_L))
#define BIT_GET_LDOH12_V12ADJ_L(x)			(((x) >> BIT_SHIFT_LDOH12_V12ADJ_L) & BIT_MASK_LDOH12_V12ADJ_L)
#define BIT_SET_LDOH12_V12ADJ_L(x, v)			(BIT_CLEAR_LDOH12_V12ADJ_L(x) | BIT_LDOH12_V12ADJ_L(v))

#define BIT_SDIO_AC0Q_EMPTY				BIT(0)

/* 2 REG_EFUSE_CTRL				(Offset 0x0030) */

#define BIT_EF_FLAG					BIT(31)

#define BIT_SHIFT_EF_PGPD				28
#define BIT_MASK_EF_PGPD				0x7
#define BIT_EF_PGPD(x)					(((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD)
#define BITS_EF_PGPD					(BIT_MASK_EF_PGPD << BIT_SHIFT_EF_PGPD)
#define BIT_CLEAR_EF_PGPD(x)				((x) & (~BITS_EF_PGPD))
#define BIT_GET_EF_PGPD(x)				(((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD)
#define BIT_SET_EF_PGPD(x, v)				(BIT_CLEAR_EF_PGPD(x) | BIT_EF_PGPD(v))

#define BIT_SHIFT_EF_RDT				24
#define BIT_MASK_EF_RDT				0xf
#define BIT_EF_RDT(x)					(((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT)
#define BITS_EF_RDT					(BIT_MASK_EF_RDT << BIT_SHIFT_EF_RDT)
#define BIT_CLEAR_EF_RDT(x)				((x) & (~BITS_EF_RDT))
#define BIT_GET_EF_RDT(x)				(((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT)
#define BIT_SET_EF_RDT(x, v)				(BIT_CLEAR_EF_RDT(x) | BIT_EF_RDT(v))

#define BIT_SHIFT_EF_PGTS				20
#define BIT_MASK_EF_PGTS				0xf
#define BIT_EF_PGTS(x)					(((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS)
#define BITS_EF_PGTS					(BIT_MASK_EF_PGTS << BIT_SHIFT_EF_PGTS)
#define BIT_CLEAR_EF_PGTS(x)				((x) & (~BITS_EF_PGTS))
#define BIT_GET_EF_PGTS(x)				(((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS)
#define BIT_SET_EF_PGTS(x, v)				(BIT_CLEAR_EF_PGTS(x) | BIT_EF_PGTS(v))

#define BIT_EF_PDWN					BIT(19)
#define BIT_EF_ALDEN					BIT(18)

#define BIT_SHIFT_HTSFR1				16
#define BIT_MASK_HTSFR1				0xffff
#define BIT_HTSFR1(x)					(((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1)
#define BITS_HTSFR1					(BIT_MASK_HTSFR1 << BIT_SHIFT_HTSFR1)
#define BIT_CLEAR_HTSFR1(x)				((x) & (~BITS_HTSFR1))
#define BIT_GET_HTSFR1(x)				(((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1)
#define BIT_SET_HTSFR1(x, v)				(BIT_CLEAR_HTSFR1(x) | BIT_HTSFR1(v))

#define BIT_SHIFT_EF_ADDR				8
#define BIT_MASK_EF_ADDR				0x3ff
#define BIT_EF_ADDR(x)					(((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR)
#define BITS_EF_ADDR					(BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)
#define BIT_CLEAR_EF_ADDR(x)				((x) & (~BITS_EF_ADDR))
#define BIT_GET_EF_ADDR(x)				(((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR)
#define BIT_SET_EF_ADDR(x, v)				(BIT_CLEAR_EF_ADDR(x) | BIT_EF_ADDR(v))

#define BIT_SHIFT_EF_DATA				0
#define BIT_MASK_EF_DATA				0xff
#define BIT_EF_DATA(x)					(((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA)
#define BITS_EF_DATA					(BIT_MASK_EF_DATA << BIT_SHIFT_EF_DATA)
#define BIT_CLEAR_EF_DATA(x)				((x) & (~BITS_EF_DATA))
#define BIT_GET_EF_DATA(x)				(((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA)
#define BIT_SET_EF_DATA(x, v)				(BIT_CLEAR_EF_DATA(x) | BIT_EF_DATA(v))

#define BIT_SHIFT_HTSFR0				0
#define BIT_MASK_HTSFR0				0xffff
#define BIT_HTSFR0(x)					(((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0)
#define BITS_HTSFR0					(BIT_MASK_HTSFR0 << BIT_SHIFT_HTSFR0)
#define BIT_CLEAR_HTSFR0(x)				((x) & (~BITS_HTSFR0))
#define BIT_GET_HTSFR0(x)				(((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0)
#define BIT_SET_HTSFR0(x, v)				(BIT_CLEAR_HTSFR0(x) | BIT_HTSFR0(v))

/* 2 REG_LDO_EFUSE_CTRL			(Offset 0x0034) */

#define BIT_SHIFT_EF_SCAN_START			16
#define BIT_MASK_EF_SCAN_START				0x1ff
#define BIT_EF_SCAN_START(x)				(((x) & BIT_MASK_EF_SCAN_START) << BIT_SHIFT_EF_SCAN_START)
#define BITS_EF_SCAN_START				(BIT_MASK_EF_SCAN_START << BIT_SHIFT_EF_SCAN_START)
#define BIT_CLEAR_EF_SCAN_START(x)			((x) & (~BITS_EF_SCAN_START))
#define BIT_GET_EF_SCAN_START(x)			(((x) >> BIT_SHIFT_EF_SCAN_START) & BIT_MASK_EF_SCAN_START)
#define BIT_SET_EF_SCAN_START(x, v)			(BIT_CLEAR_EF_SCAN_START(x) | BIT_EF_SCAN_START(v))

#define BIT_SHIFT_EF_SCAN_END_9_TO_8			12
#define BIT_MASK_EF_SCAN_END_9_TO_8			0x3
#define BIT_EF_SCAN_END_9_TO_8(x)			(((x) & BIT_MASK_EF_SCAN_END_9_TO_8) << BIT_SHIFT_EF_SCAN_END_9_TO_8)
#define BITS_EF_SCAN_END_9_TO_8			(BIT_MASK_EF_SCAN_END_9_TO_8 << BIT_SHIFT_EF_SCAN_END_9_TO_8)
#define BIT_CLEAR_EF_SCAN_END_9_TO_8(x)		((x) & (~BITS_EF_SCAN_END_9_TO_8))
#define BIT_GET_EF_SCAN_END_9_TO_8(x)			(((x) >> BIT_SHIFT_EF_SCAN_END_9_TO_8) & BIT_MASK_EF_SCAN_END_9_TO_8)
#define BIT_SET_EF_SCAN_END_9_TO_8(x, v)		(BIT_CLEAR_EF_SCAN_END_9_TO_8(x) | BIT_EF_SCAN_END_9_TO_8(v))

#define BIT_EF_FORCE_PGMEN				BIT(11)

#define BIT_SHIFT_EF_CELL_SEL				8
#define BIT_MASK_EF_CELL_SEL				0x3
#define BIT_EF_CELL_SEL(x)				(((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL)
#define BITS_EF_CELL_SEL				(BIT_MASK_EF_CELL_SEL << BIT_SHIFT_EF_CELL_SEL)
#define BIT_CLEAR_EF_CELL_SEL(x)			((x) & (~BITS_EF_CELL_SEL))
#define BIT_GET_EF_CELL_SEL(x)				(((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL)
#define BIT_SET_EF_CELL_SEL(x, v)			(BIT_CLEAR_EF_CELL_SEL(x) | BIT_EF_CELL_SEL(v))

#define BIT_EF_TRPT					BIT(7)

#define BIT_SHIFT_EF_TTHD				0
#define BIT_MASK_EF_TTHD				0x7f
#define BIT_EF_TTHD(x)					(((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD)
#define BITS_EF_TTHD					(BIT_MASK_EF_TTHD << BIT_SHIFT_EF_TTHD)
#define BIT_CLEAR_EF_TTHD(x)				((x) & (~BITS_EF_TTHD))
#define BIT_GET_EF_TTHD(x)				(((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD)
#define BIT_SET_EF_TTHD(x, v)				(BIT_CLEAR_EF_TTHD(x) | BIT_EF_TTHD(v))

/* 2 REG_PWR_OPTION_CTRL			(Offset 0x0038) */

#define BIT_SHIFT_SYSON_XTAL_STABLE_WT			30
#define BIT_MASK_SYSON_XTAL_STABLE_WT			0x3
#define BIT_SYSON_XTAL_STABLE_WT(x)			(((x) & BIT_MASK_SYSON_XTAL_STABLE_WT) << BIT_SHIFT_SYSON_XTAL_STABLE_WT)
#define BITS_SYSON_XTAL_STABLE_WT			(BIT_MASK_SYSON_XTAL_STABLE_WT << BIT_SHIFT_SYSON_XTAL_STABLE_WT)
#define BIT_CLEAR_SYSON_XTAL_STABLE_WT(x)		((x) & (~BITS_SYSON_XTAL_STABLE_WT))
#define BIT_GET_SYSON_XTAL_STABLE_WT(x)		(((x) >> BIT_SHIFT_SYSON_XTAL_STABLE_WT) & BIT_MASK_SYSON_XTAL_STABLE_WT)
#define BIT_SET_SYSON_XTAL_STABLE_WT(x, v)		(BIT_CLEAR_SYSON_XTAL_STABLE_WT(x) | BIT_SYSON_XTAL_STABLE_WT(v))

#define BIT_SHIFT_SYSON_SWT_PWM_WT			28
#define BIT_MASK_SYSON_SWT_PWM_WT			0x3
#define BIT_SYSON_SWT_PWM_WT(x)			(((x) & BIT_MASK_SYSON_SWT_PWM_WT) << BIT_SHIFT_SYSON_SWT_PWM_WT)
#define BITS_SYSON_SWT_PWM_WT				(BIT_MASK_SYSON_SWT_PWM_WT << BIT_SHIFT_SYSON_SWT_PWM_WT)
#define BIT_CLEAR_SYSON_SWT_PWM_WT(x)			((x) & (~BITS_SYSON_SWT_PWM_WT))
#define BIT_GET_SYSON_SWT_PWM_WT(x)			(((x) >> BIT_SHIFT_SYSON_SWT_PWM_WT) & BIT_MASK_SYSON_SWT_PWM_WT)
#define BIT_SET_SYSON_SWT_PWM_WT(x, v)			(BIT_CLEAR_SYSON_SWT_PWM_WT(x) | BIT_SYSON_SWT_PWM_WT(v))

#define BIT_SHIFT_SYSON_BT_LDO_WT			26
#define BIT_MASK_SYSON_BT_LDO_WT			0x3
#define BIT_SYSON_BT_LDO_WT(x)				(((x) & BIT_MASK_SYSON_BT_LDO_WT) << BIT_SHIFT_SYSON_BT_LDO_WT)
#define BITS_SYSON_BT_LDO_WT				(BIT_MASK_SYSON_BT_LDO_WT << BIT_SHIFT_SYSON_BT_LDO_WT)
#define BIT_CLEAR_SYSON_BT_LDO_WT(x)			((x) & (~BITS_SYSON_BT_LDO_WT))
#define BIT_GET_SYSON_BT_LDO_WT(x)			(((x) >> BIT_SHIFT_SYSON_BT_LDO_WT) & BIT_MASK_SYSON_BT_LDO_WT)
#define BIT_SET_SYSON_BT_LDO_WT(x, v)			(BIT_CLEAR_SYSON_BT_LDO_WT(x) | BIT_SYSON_BT_LDO_WT(v))

#define BIT_SHIFT_DBG_SHIFT				24
#define BIT_MASK_DBG_SHIFT				0x3
#define BIT_DBG_SHIFT(x)				(((x) & BIT_MASK_DBG_SHIFT) << BIT_SHIFT_DBG_SHIFT)
#define BITS_DBG_SHIFT					(BIT_MASK_DBG_SHIFT << BIT_SHIFT_DBG_SHIFT)
#define BIT_CLEAR_DBG_SHIFT(x)				((x) & (~BITS_DBG_SHIFT))
#define BIT_GET_DBG_SHIFT(x)				(((x) >> BIT_SHIFT_DBG_SHIFT) & BIT_MASK_DBG_SHIFT)
#define BIT_SET_DBG_SHIFT(x, v)			(BIT_CLEAR_DBG_SHIFT(x) | BIT_DBG_SHIFT(v))

#define BIT_SHIFT_DBG_SEL_V1				16
#define BIT_MASK_DBG_SEL_V1				0xff
#define BIT_DBG_SEL_V1(x)				(((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1)
#define BITS_DBG_SEL_V1				(BIT_MASK_DBG_SEL_V1 << BIT_SHIFT_DBG_SEL_V1)
#define BIT_CLEAR_DBG_SEL_V1(x)			((x) & (~BITS_DBG_SEL_V1))
#define BIT_GET_DBG_SEL_V1(x)				(((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1)
#define BIT_SET_DBG_SEL_V1(x, v)			(BIT_CLEAR_DBG_SEL_V1(x) | BIT_DBG_SEL_V1(v))

#define BIT_DIS_LPS_WT_PDNSUS				BIT(15)

#define BIT_SHIFT_SYSON_WLPLL_LDO_WT			12
#define BIT_MASK_SYSON_WLPLL_LDO_WT			0x3
#define BIT_SYSON_WLPLL_LDO_WT(x)			(((x) & BIT_MASK_SYSON_WLPLL_LDO_WT) << BIT_SHIFT_SYSON_WLPLL_LDO_WT)
#define BITS_SYSON_WLPLL_LDO_WT			(BIT_MASK_SYSON_WLPLL_LDO_WT << BIT_SHIFT_SYSON_WLPLL_LDO_WT)
#define BIT_CLEAR_SYSON_WLPLL_LDO_WT(x)		((x) & (~BITS_SYSON_WLPLL_LDO_WT))
#define BIT_GET_SYSON_WLPLL_LDO_WT(x)			(((x) >> BIT_SHIFT_SYSON_WLPLL_LDO_WT) & BIT_MASK_SYSON_WLPLL_LDO_WT)
#define BIT_SET_SYSON_WLPLL_LDO_WT(x, v)		(BIT_CLEAR_SYSON_WLPLL_LDO_WT(x) | BIT_SYSON_WLPLL_LDO_WT(v))

#define BIT_SHIFT_SYSON_WLOFF_LDO_WT			10
#define BIT_MASK_SYSON_WLOFF_LDO_WT			0x3
#define BIT_SYSON_WLOFF_LDO_WT(x)			(((x) & BIT_MASK_SYSON_WLOFF_LDO_WT) << BIT_SHIFT_SYSON_WLOFF_LDO_WT)
#define BITS_SYSON_WLOFF_LDO_WT			(BIT_MASK_SYSON_WLOFF_LDO_WT << BIT_SHIFT_SYSON_WLOFF_LDO_WT)
#define BIT_CLEAR_SYSON_WLOFF_LDO_WT(x)		((x) & (~BITS_SYSON_WLOFF_LDO_WT))
#define BIT_GET_SYSON_WLOFF_LDO_WT(x)			(((x) >> BIT_SHIFT_SYSON_WLOFF_LDO_WT) & BIT_MASK_SYSON_WLOFF_LDO_WT)
#define BIT_SET_SYSON_WLOFF_LDO_WT(x, v)		(BIT_CLEAR_SYSON_WLOFF_LDO_WT(x) | BIT_SYSON_WLOFF_LDO_WT(v))

#define BIT_SHIFT_SYSON_APHY_LDO_WT			8
#define BIT_MASK_SYSON_APHY_LDO_WT			0x3
#define BIT_SYSON_APHY_LDO_WT(x)			(((x) & BIT_MASK_SYSON_APHY_LDO_WT) << BIT_SHIFT_SYSON_APHY_LDO_WT)
#define BITS_SYSON_APHY_LDO_WT				(BIT_MASK_SYSON_APHY_LDO_WT << BIT_SHIFT_SYSON_APHY_LDO_WT)
#define BIT_CLEAR_SYSON_APHY_LDO_WT(x)			((x) & (~BITS_SYSON_APHY_LDO_WT))
#define BIT_GET_SYSON_APHY_LDO_WT(x)			(((x) >> BIT_SHIFT_SYSON_APHY_LDO_WT) & BIT_MASK_SYSON_APHY_LDO_WT)
#define BIT_SET_SYSON_APHY_LDO_WT(x, v)		(BIT_CLEAR_SYSON_APHY_LDO_WT(x) | BIT_SYSON_APHY_LDO_WT(v))

#define BIT_SHIFT_SYSON_PHYDIG_LDO_WT			6
#define BIT_MASK_SYSON_PHYDIG_LDO_WT			0x3
#define BIT_SYSON_PHYDIG_LDO_WT(x)			(((x) & BIT_MASK_SYSON_PHYDIG_LDO_WT) << BIT_SHIFT_SYSON_PHYDIG_LDO_WT)
#define BITS_SYSON_PHYDIG_LDO_WT			(BIT_MASK_SYSON_PHYDIG_LDO_WT << BIT_SHIFT_SYSON_PHYDIG_LDO_WT)
#define BIT_CLEAR_SYSON_PHYDIG_LDO_WT(x)		((x) & (~BITS_SYSON_PHYDIG_LDO_WT))
#define BIT_GET_SYSON_PHYDIG_LDO_WT(x)			(((x) >> BIT_SHIFT_SYSON_PHYDIG_LDO_WT) & BIT_MASK_SYSON_PHYDIG_LDO_WT)
#define BIT_SET_SYSON_PHYDIG_LDO_WT(x, v)		(BIT_CLEAR_SYSON_PHYDIG_LDO_WT(x) | BIT_SYSON_PHYDIG_LDO_WT(v))

#define BIT_SHIFT_SYSON_SPS0WWV_WT			4
#define BIT_MASK_SYSON_SPS0WWV_WT			0x3
#define BIT_SYSON_SPS0WWV_WT(x)			(((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT)
#define BITS_SYSON_SPS0WWV_WT				(BIT_MASK_SYSON_SPS0WWV_WT << BIT_SHIFT_SYSON_SPS0WWV_WT)
#define BIT_CLEAR_SYSON_SPS0WWV_WT(x)			((x) & (~BITS_SYSON_SPS0WWV_WT))
#define BIT_GET_SYSON_SPS0WWV_WT(x)			(((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT)
#define BIT_SET_SYSON_SPS0WWV_WT(x, v)			(BIT_CLEAR_SYSON_SPS0WWV_WT(x) | BIT_SYSON_SPS0WWV_WT(v))

#define BIT_SHIFT_SYSON_SPS0LDO_WT			2
#define BIT_MASK_SYSON_SPS0LDO_WT			0x3
#define BIT_SYSON_SPS0LDO_WT(x)			(((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT)
#define BITS_SYSON_SPS0LDO_WT				(BIT_MASK_SYSON_SPS0LDO_WT << BIT_SHIFT_SYSON_SPS0LDO_WT)
#define BIT_CLEAR_SYSON_SPS0LDO_WT(x)			((x) & (~BITS_SYSON_SPS0LDO_WT))
#define BIT_GET_SYSON_SPS0LDO_WT(x)			(((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT)
#define BIT_SET_SYSON_SPS0LDO_WT(x, v)			(BIT_CLEAR_SYSON_SPS0LDO_WT(x) | BIT_SYSON_SPS0LDO_WT(v))

#define BIT_SHIFT_SYSON_RCLK_SCALE			0
#define BIT_MASK_SYSON_RCLK_SCALE			0x3
#define BIT_SYSON_RCLK_SCALE(x)			(((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE)
#define BITS_SYSON_RCLK_SCALE				(BIT_MASK_SYSON_RCLK_SCALE << BIT_SHIFT_SYSON_RCLK_SCALE)
#define BIT_CLEAR_SYSON_RCLK_SCALE(x)			((x) & (~BITS_SYSON_RCLK_SCALE))
#define BIT_GET_SYSON_RCLK_SCALE(x)			(((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE)
#define BIT_SET_SYSON_RCLK_SCALE(x, v)			(BIT_CLEAR_SYSON_RCLK_SCALE(x) | BIT_SYSON_RCLK_SCALE(v))

#define BIT_CUR_PS					BIT(0)

/* 2 REG_CAL_TIMER				(Offset 0x003C) */

#define BIT_SHIFT_MATCH_CNT				8
#define BIT_MASK_MATCH_CNT				0xff
#define BIT_MATCH_CNT(x)				(((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT)
#define BITS_MATCH_CNT					(BIT_MASK_MATCH_CNT << BIT_SHIFT_MATCH_CNT)
#define BIT_CLEAR_MATCH_CNT(x)				((x) & (~BITS_MATCH_CNT))
#define BIT_GET_MATCH_CNT(x)				(((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT)
#define BIT_SET_MATCH_CNT(x, v)			(BIT_CLEAR_MATCH_CNT(x) | BIT_MATCH_CNT(v))

#define BIT_SHIFT_CAL_SCAL				0
#define BIT_MASK_CAL_SCAL				0xff
#define BIT_CAL_SCAL(x)				(((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL)
#define BITS_CAL_SCAL					(BIT_MASK_CAL_SCAL << BIT_SHIFT_CAL_SCAL)
#define BIT_CLEAR_CAL_SCAL(x)				((x) & (~BITS_CAL_SCAL))
#define BIT_GET_CAL_SCAL(x)				(((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL)
#define BIT_SET_CAL_SCAL(x, v)				(BIT_CLEAR_CAL_SCAL(x) | BIT_CAL_SCAL(v))

/* 2 REG_ACLK_MON				(Offset 0x003E) */

#define BIT_SHIFT_RCLK_MON				5
#define BIT_MASK_RCLK_MON				0x7ff
#define BIT_RCLK_MON(x)				(((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON)
#define BITS_RCLK_MON					(BIT_MASK_RCLK_MON << BIT_SHIFT_RCLK_MON)
#define BIT_CLEAR_RCLK_MON(x)				((x) & (~BITS_RCLK_MON))
#define BIT_GET_RCLK_MON(x)				(((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON)
#define BIT_SET_RCLK_MON(x, v)				(BIT_CLEAR_RCLK_MON(x) | BIT_RCLK_MON(v))

#define BIT_CAL_EN					BIT(4)

#define BIT_SHIFT_DPSTU				2
#define BIT_MASK_DPSTU					0x3
#define BIT_DPSTU(x)					(((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU)
#define BITS_DPSTU					(BIT_MASK_DPSTU << BIT_SHIFT_DPSTU)
#define BIT_CLEAR_DPSTU(x)				((x) & (~BITS_DPSTU))
#define BIT_GET_DPSTU(x)				(((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU)
#define BIT_SET_DPSTU(x, v)				(BIT_CLEAR_DPSTU(x) | BIT_DPSTU(v))

#define BIT_SUS_16X					BIT(1)
#define BIT_RSM_EN					BIT(0)

/* 2 REG_GPIO_MUXCFG				(Offset 0x0040) */

#define BIT_PCIE_WAKE_EN				BIT(23)
#define BIT_INDIRECT_REG_RDY				BIT(20)
#define BIT_R_SYM_BT_SIC_EN				BIT(19)
#define BIT_INDIRECT_REG_R				BIT(19)
#define BIT_WL_EXT_32K_SEL				BIT(18)
#define BIT_INDIRECT_REG_W				BIT(18)

#define BIT_SHIFT_INDIRECT_REG_SIZE			16
#define BIT_MASK_INDIRECT_REG_SIZE			0x3
#define BIT_INDIRECT_REG_SIZE(x)			(((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE)
#define BITS_INDIRECT_REG_SIZE				(BIT_MASK_INDIRECT_REG_SIZE << BIT_SHIFT_INDIRECT_REG_SIZE)
#define BIT_CLEAR_INDIRECT_REG_SIZE(x)			((x) & (~BITS_INDIRECT_REG_SIZE))
#define BIT_GET_INDIRECT_REG_SIZE(x)			(((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE)
#define BIT_SET_INDIRECT_REG_SIZE(x, v)		(BIT_CLEAR_INDIRECT_REG_SIZE(x) | BIT_INDIRECT_REG_SIZE(v))

#define BIT_SIC_LBK					BIT(15)
#define BIT_ENHTP					BIT(14)
#define BIT_ENSIC					BIT(12)
#define BIT_SIC_SWRST					BIT(11)
#define BIT_ENUART					BIT(8)

#define BIT_SHIFT_BTMODE				6
#define BIT_MASK_BTMODE				0x3
#define BIT_BTMODE(x)					(((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE)
#define BITS_BTMODE					(BIT_MASK_BTMODE << BIT_SHIFT_BTMODE)
#define BIT_CLEAR_BTMODE(x)				((x) & (~BITS_BTMODE))
#define BIT_GET_BTMODE(x)				(((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE)
#define BIT_SET_BTMODE(x, v)				(BIT_CLEAR_BTMODE(x) | BIT_BTMODE(v))

#define BIT_ENBT					BIT(5)
#define BIT_EROM_EN					BIT(4)
#define BIT_WL_WAKE_HOST				BIT(3)
#define BIT_WLRFE_4_5_EN				BIT(2)

#define BIT_SHIFT_GPIOSEL				0
#define BIT_MASK_GPIOSEL				0x3
#define BIT_GPIOSEL(x)					(((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL)
#define BITS_GPIOSEL					(BIT_MASK_GPIOSEL << BIT_SHIFT_GPIOSEL)
#define BIT_CLEAR_GPIOSEL(x)				((x) & (~BITS_GPIOSEL))
#define BIT_GET_GPIOSEL(x)				(((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL)
#define BIT_SET_GPIOSEL(x, v)				(BIT_CLEAR_GPIOSEL(x) | BIT_GPIOSEL(v))

#define BIT_SHIFT_INDIRECT_REG_ADDR			0
#define BIT_MASK_INDIRECT_REG_ADDR			0xffff
#define BIT_INDIRECT_REG_ADDR(x)			(((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR)
#define BITS_INDIRECT_REG_ADDR				(BIT_MASK_INDIRECT_REG_ADDR << BIT_SHIFT_INDIRECT_REG_ADDR)
#define BIT_CLEAR_INDIRECT_REG_ADDR(x)			((x) & (~BITS_INDIRECT_REG_ADDR))
#define BIT_GET_INDIRECT_REG_ADDR(x)			(((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR)
#define BIT_SET_INDIRECT_REG_ADDR(x, v)		(BIT_CLEAR_INDIRECT_REG_ADDR(x) | BIT_INDIRECT_REG_ADDR(v))

/* 2 REG_GPIO_PIN_CTRL			(Offset 0x0044) */

#define BIT_SHIFT_GPIO_MOD_7_TO_0			24
#define BIT_MASK_GPIO_MOD_7_TO_0			0xff
#define BIT_GPIO_MOD_7_TO_0(x)				(((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0)
#define BITS_GPIO_MOD_7_TO_0				(BIT_MASK_GPIO_MOD_7_TO_0 << BIT_SHIFT_GPIO_MOD_7_TO_0)
#define BIT_CLEAR_GPIO_MOD_7_TO_0(x)			((x) & (~BITS_GPIO_MOD_7_TO_0))
#define BIT_GET_GPIO_MOD_7_TO_0(x)			(((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0)
#define BIT_SET_GPIO_MOD_7_TO_0(x, v)			(BIT_CLEAR_GPIO_MOD_7_TO_0(x) | BIT_GPIO_MOD_7_TO_0(v))

#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0			16
#define BIT_MASK_GPIO_IO_SEL_7_TO_0			0xff
#define BIT_GPIO_IO_SEL_7_TO_0(x)			(((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0)
#define BITS_GPIO_IO_SEL_7_TO_0			(BIT_MASK_GPIO_IO_SEL_7_TO_0 << BIT_SHIFT_GPIO_IO_SEL_7_TO_0)
#define BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x)		((x) & (~BITS_GPIO_IO_SEL_7_TO_0))
#define BIT_GET_GPIO_IO_SEL_7_TO_0(x)			(((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0)
#define BIT_SET_GPIO_IO_SEL_7_TO_0(x, v)		(BIT_CLEAR_GPIO_IO_SEL_7_TO_0(x) | BIT_GPIO_IO_SEL_7_TO_0(v))

#define BIT_SHIFT_GPIO_OUT_7_TO_0			8
#define BIT_MASK_GPIO_OUT_7_TO_0			0xff
#define BIT_GPIO_OUT_7_TO_0(x)				(((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0)
#define BITS_GPIO_OUT_7_TO_0				(BIT_MASK_GPIO_OUT_7_TO_0 << BIT_SHIFT_GPIO_OUT_7_TO_0)
#define BIT_CLEAR_GPIO_OUT_7_TO_0(x)			((x) & (~BITS_GPIO_OUT_7_TO_0))
#define BIT_GET_GPIO_OUT_7_TO_0(x)			(((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0)
#define BIT_SET_GPIO_OUT_7_TO_0(x, v)			(BIT_CLEAR_GPIO_OUT_7_TO_0(x) | BIT_GPIO_OUT_7_TO_0(v))

#define BIT_SHIFT_GPIO_IN_7_TO_0			0
#define BIT_MASK_GPIO_IN_7_TO_0			0xff
#define BIT_GPIO_IN_7_TO_0(x)				(((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0)
#define BITS_GPIO_IN_7_TO_0				(BIT_MASK_GPIO_IN_7_TO_0 << BIT_SHIFT_GPIO_IN_7_TO_0)
#define BIT_CLEAR_GPIO_IN_7_TO_0(x)			((x) & (~BITS_GPIO_IN_7_TO_0))
#define BIT_GET_GPIO_IN_7_TO_0(x)			(((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0)
#define BIT_SET_GPIO_IN_7_TO_0(x, v)			(BIT_CLEAR_GPIO_IN_7_TO_0(x) | BIT_GPIO_IN_7_TO_0(v))

#define BIT_SHIFT_INDIRECT_REG_DATA			0
#define BIT_MASK_INDIRECT_REG_DATA			0xffffffffL
#define BIT_INDIRECT_REG_DATA(x)			(((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA)
#define BITS_INDIRECT_REG_DATA				(BIT_MASK_INDIRECT_REG_DATA << BIT_SHIFT_INDIRECT_REG_DATA)
#define BIT_CLEAR_INDIRECT_REG_DATA(x)			((x) & (~BITS_INDIRECT_REG_DATA))
#define BIT_GET_INDIRECT_REG_DATA(x)			(((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA)
#define BIT_SET_INDIRECT_REG_DATA(x, v)		(BIT_CLEAR_INDIRECT_REG_DATA(x) | BIT_INDIRECT_REG_DATA(v))

/* 2 REG_GPIO_INTM				(Offset 0x0048) */

#define BIT_SHIFT_MUXDBG_SEL				30
#define BIT_MASK_MUXDBG_SEL				0x3
#define BIT_MUXDBG_SEL(x)				(((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL)
#define BITS_MUXDBG_SEL				(BIT_MASK_MUXDBG_SEL << BIT_SHIFT_MUXDBG_SEL)
#define BIT_CLEAR_MUXDBG_SEL(x)			((x) & (~BITS_MUXDBG_SEL))
#define BIT_GET_MUXDBG_SEL(x)				(((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL)
#define BIT_SET_MUXDBG_SEL(x, v)			(BIT_CLEAR_MUXDBG_SEL(x) | BIT_MUXDBG_SEL(v))

#define BIT_HWD_OPT_SEL1				BIT(30)
#define BIT_PCI_LPS_LDO_ACT				BIT(29)
#define BIT_HWD_CTS_SEL				BIT(29)
#define BIT_GPIO_UART_O				BIT(28)
#define BIT_A4WP_SMT					BIT(28)
#define BIT_GPIO_UART_E				BIT(27)
#define BIT_GPIO161718					BIT(27)
#define BIT_GPIO8_HWD_PULL				BIT(26)
#define BIT_LNAON_SEL_EN				BIT(26)
#define BIT_UART_CTS_HWD_PULL				BIT(25)
#define BIT_PAPE_SEL_EN				BIT(25)
#define BIT_GPIO4_CLR					BIT(24)
#define BIT_DPDT_WLBT_SEL				BIT(24)
#define BIT_GPIO5_CLR					BIT(23)
#define BIT_GPIO12_CLR					BIT(22)
#define BIT_LED2DIS					BIT(22)
#define BIT_UART_CTS_PLY				BIT(21)
#define BIT_LED2EN					BIT(21)
#define BIT_BTGP_WAKE_EN				BIT(20)
#define BIT_LED2PL					BIT(20)
#define BIT_WLGP_WAKE_EN				BIT(19)
#define BIT_LED2SV					BIT(19)
#define BIT_DEVGP_WAKE_EN				BIT(18)
#define BIT_EXTWOL0_SEL				BIT(17)
#define BIT_EXTWOL0_EN					BIT(16)

#define BIT_SHIFT_LED2CM				16
#define BIT_MASK_LED2CM				0x7
#define BIT_LED2CM(x)					(((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM)
#define BITS_LED2CM					(BIT_MASK_LED2CM << BIT_SHIFT_LED2CM)
#define BIT_CLEAR_LED2CM(x)				((x) & (~BITS_LED2CM))
#define BIT_GET_LED2CM(x)				(((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM)
#define BIT_SET_LED2CM(x, v)				(BIT_CLEAR_LED2CM(x) | BIT_LED2CM(v))

#define BIT_GPIOF_INT_MD				BIT(15)
#define BIT_LED1DIS					BIT(15)
#define BIT_GPIOE_INT_MD				BIT(14)
#define BIT_GPIOD_INT_MD				BIT(13)
#define BIT_GPIOC_INT_MD				BIT(12)
#define BIT_LED1PL					BIT(12)
#define BIT_GPIOB_INT_MD				BIT(11)
#define BIT_LED1SV					BIT(11)
#define BIT_GPIOA_INT_MD				BIT(10)
#define BIT_GPIO9_INT_MD				BIT(9)
#define BIT_GPIO8_INT_MD				BIT(8)

#define BIT_SHIFT_LED1CM				8
#define BIT_MASK_LED1CM				0x7
#define BIT_LED1CM(x)					(((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM)
#define BITS_LED1CM					(BIT_MASK_LED1CM << BIT_SHIFT_LED1CM)
#define BIT_CLEAR_LED1CM(x)				((x) & (~BITS_LED1CM))
#define BIT_GET_LED1CM(x)				(((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM)
#define BIT_SET_LED1CM(x, v)				(BIT_CLEAR_LED1CM(x) | BIT_LED1CM(v))

#define BIT_GPIO7_INT_MD				BIT(7)
#define BIT_LED0DIS					BIT(7)
#define BIT_GPIO6_INT_MD				BIT(6)
#define BIT_GPIO5_INT_MD				BIT(5)

#define BIT_SHIFT_AFE_LDO_SWR_CHECK			5
#define BIT_MASK_AFE_LDO_SWR_CHECK			0x3
#define BIT_AFE_LDO_SWR_CHECK(x)			(((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK)
#define BITS_AFE_LDO_SWR_CHECK				(BIT_MASK_AFE_LDO_SWR_CHECK << BIT_SHIFT_AFE_LDO_SWR_CHECK)
#define BIT_CLEAR_AFE_LDO_SWR_CHECK(x)			((x) & (~BITS_AFE_LDO_SWR_CHECK))
#define BIT_GET_AFE_LDO_SWR_CHECK(x)			(((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK)
#define BIT_SET_AFE_LDO_SWR_CHECK(x, v)		(BIT_CLEAR_AFE_LDO_SWR_CHECK(x) | BIT_AFE_LDO_SWR_CHECK(v))

#define BIT_GPIO4_INT_MD				BIT(4)
#define BIT_LED0PL					BIT(4)
#define BIT_GPIO3_INT_MD				BIT(3)
#define BIT_LED0SV					BIT(3)
#define BIT_GPIO2_INT_MD				BIT(2)
#define BIT_GPIO1_INT_MD				BIT(1)
#define BIT_GPIO0_INT_MD				BIT(0)

#define BIT_SHIFT_LED0CM				0
#define BIT_MASK_LED0CM				0x7
#define BIT_LED0CM(x)					(((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM)
#define BITS_LED0CM					(BIT_MASK_LED0CM << BIT_SHIFT_LED0CM)
#define BIT_CLEAR_LED0CM(x)				((x) & (~BITS_LED0CM))
#define BIT_GET_LED0CM(x)				(((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM)
#define BIT_SET_LED0CM(x, v)				(BIT_CLEAR_LED0CM(x) | BIT_LED0CM(v))

/* 2 REG_FSIMR				(Offset 0x0050) */

#define BIT_FS_PDNINT_EN				BIT(31)
#define BIT_UART_CTS_INT_EN				BIT(30)
#define BIT_FS_SPS_OCP_INT_EN				BIT(29)
#define BIT_FS_PWMERR_INT_EN				BIT(28)
#define BIT_FS_GPIOF_INT_EN				BIT(27)
#define BIT_FS_GPIOE_INT_EN				BIT(26)
#define BIT_FS_GPIOD_INT_EN				BIT(25)
#define BIT_FS_GPIOC_INT_EN				BIT(24)
#define BIT_FS_GPIOB_INT_EN				BIT(23)
#define BIT_FS_GPIOA_INT_EN				BIT(22)
#define BIT_FS_GPIO9_INT_EN				BIT(21)
#define BIT_FS_GPIO8_INT_EN				BIT(20)
#define BIT_FS_GPIO7_INT_EN				BIT(19)
#define BIT_FS_GPIO6_INT_EN				BIT(18)
#define BIT_FS_GPIO5_INT_EN				BIT(17)
#define BIT_FS_GPIO4_INT_EN				BIT(16)
#define BIT_FS_GPIO3_INT_EN				BIT(15)
#define BIT_FS_GPIO2_INT_EN				BIT(14)
#define BIT_FS_GPIO1_INT_EN				BIT(13)
#define BIT_FS_GPIO0_INT_EN				BIT(12)
#define BIT_FS_HCI_SUS_EN				BIT(11)
#define BIT_FS_HCI_RES_EN				BIT(10)
#define BIT_FS_HCI_RESET_EN				BIT(9)
#define BIT_FS_BTON_STS_UPDATE_EN			BIT(7)
#define BIT_SIDE_BAND_INT_EN				BIT(6)
#define BIT_FS_TRPC_TO_INT_EN				BIT(5)
#define BIT_FS_RPC_O_T_INT_EN				BIT(4)
#define BIT_FS_32K_LEAVE_SETTING_EN			BIT(3)
#define BIT_FS_32K_ENTER_SETTING_EN			BIT(2)
#define BIT_FS_USB_LPMRSM_EN				BIT(1)
#define BIT_FS_USB_LPMINT_EN				BIT(0)

/* 2 REG_FSISR				(Offset 0x0054) */

#define BIT_FS_PDNINT					BIT(31)
#define BIT_UART_CTS_INT				BIT(30)
#define BIT_FS_SPS_OCP_INT				BIT(29)
#define BIT_FS_PWMERR_INT				BIT(28)
#define BIT_FS_GPIOF_INT				BIT(27)
#define BIT_FS_GPIOE_INT				BIT(26)
#define BIT_FS_GPIOD_INT				BIT(25)
#define BIT_FS_GPIOC_INT				BIT(24)
#define BIT_FS_GPIOB_INT				BIT(23)
#define BIT_FS_GPIOA_INT				BIT(22)
#define BIT_FS_GPIO9_INT				BIT(21)
#define BIT_FS_GPIO8_INT				BIT(20)
#define BIT_FS_GPIO7_INT				BIT(19)
#define BIT_FS_GPIO6_INT				BIT(18)
#define BIT_FS_GPIO5_INT				BIT(17)
#define BIT_FS_GPIO4_INT				BIT(16)
#define BIT_FS_GPIO3_INT				BIT(15)
#define BIT_FS_GPIO2_INT				BIT(14)
#define BIT_FS_GPIO1_INT				BIT(13)
#define BIT_FS_GPIO0_INT				BIT(12)
#define BIT_FS_HCI_SUS_INT				BIT(11)
#define BIT_FS_HCI_RES_INT				BIT(10)
#define BIT_FS_HCI_RESET_INT				BIT(9)
#define BIT_FS_BTON_STS_UPDATE_INT			BIT(7)
#define BIT_FS_TRPC_TO_INT_INT				BIT(5)
#define BIT_FS_RPC_O_T_INT_INT				BIT(4)
#define BIT_FS_32K_LEAVE_SETTING_INT			BIT(3)
#define BIT_FS_32K_ENTER_SETTING_INT			BIT(2)
#define BIT_FS_USB_LPMRSM_INT				BIT(1)
#define BIT_FS_USB_LPMINT_INT				BIT(0)

/* 2 REG_HSIMR				(Offset 0x0058) */

#define BIT_GPIOF_INT_EN				BIT(31)
#define BIT_GPIOE_INT_EN				BIT(30)
#define BIT_GPIOD_INT_EN				BIT(29)
#define BIT_GPIOC_INT_EN				BIT(28)
#define BIT_GPIOB_INT_EN				BIT(27)
#define BIT_GPIOA_INT_EN				BIT(26)
#define BIT_GPIO9_INT_EN				BIT(25)
#define BIT_GPIO8_INT_EN				BIT(24)
#define BIT_GPIO7_INT_EN				BIT(23)
#define BIT_GPIO6_INT_EN				BIT(22)
#define BIT_GPIO5_INT_EN				BIT(21)
#define BIT_GPIO4_INT_EN				BIT(20)
#define BIT_GPIO3_INT_EN				BIT(19)
#define BIT_GPIO2_INT_EN				BIT(18)
#define BIT_GPIO1_INT_EN				BIT(17)
#define BIT_GPIO0_INT_EN				BIT(16)
#define BIT_PDNINT_EN					BIT(7)
#define BIT_RON_INT_EN					BIT(6)
#define BIT_SPS_OCP_INT_EN				BIT(5)
#define BIT_GPIO15_0_INT_EN				BIT(0)

/* 2 REG_HSISR				(Offset 0x005C) */

#define BIT_GPIOF_INT					BIT(31)
#define BIT_GPIOE_INT					BIT(30)
#define BIT_GPIOD_INT					BIT(29)
#define BIT_GPIOC_INT					BIT(28)
#define BIT_GPIOB_INT					BIT(27)
#define BIT_GPIOA_INT					BIT(26)
#define BIT_GPIO9_INT					BIT(25)
#define BIT_GPIO8_INT					BIT(24)
#define BIT_GPIO7_INT					BIT(23)
#define BIT_GPIO6_INT					BIT(22)
#define BIT_GPIO5_INT					BIT(21)
#define BIT_GPIO4_INT					BIT(20)
#define BIT_GPIO3_INT					BIT(19)
#define BIT_GPIO2_INT					BIT(18)
#define BIT_GPIO1_INT					BIT(17)
#define BIT_GPIO0_INT					BIT(16)
#define BIT_PDNINT					BIT(7)
#define BIT_RON_INT					BIT(6)
#define BIT_SPS_OCP_INT				BIT(5)
#define BIT_VBAT_LOW_INT				BIT(4)
#define BIT_GPIO15_0_INT				BIT(0)

/* 2 REG_GPIO_EXT_CTRL			(Offset 0x0060) */

#define BIT_SHIFT_GPIO_MOD_15_TO_8			24
#define BIT_MASK_GPIO_MOD_15_TO_8			0xff
#define BIT_GPIO_MOD_15_TO_8(x)			(((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8)
#define BITS_GPIO_MOD_15_TO_8				(BIT_MASK_GPIO_MOD_15_TO_8 << BIT_SHIFT_GPIO_MOD_15_TO_8)
#define BIT_CLEAR_GPIO_MOD_15_TO_8(x)			((x) & (~BITS_GPIO_MOD_15_TO_8))
#define BIT_GET_GPIO_MOD_15_TO_8(x)			(((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8)
#define BIT_SET_GPIO_MOD_15_TO_8(x, v)			(BIT_CLEAR_GPIO_MOD_15_TO_8(x) | BIT_GPIO_MOD_15_TO_8(v))

#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8			16
#define BIT_MASK_GPIO_IO_SEL_15_TO_8			0xff
#define BIT_GPIO_IO_SEL_15_TO_8(x)			(((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8)
#define BITS_GPIO_IO_SEL_15_TO_8			(BIT_MASK_GPIO_IO_SEL_15_TO_8 << BIT_SHIFT_GPIO_IO_SEL_15_TO_8)
#define BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x)		((x) & (~BITS_GPIO_IO_SEL_15_TO_8))
#define BIT_GET_GPIO_IO_SEL_15_TO_8(x)			(((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8)
#define BIT_SET_GPIO_IO_SEL_15_TO_8(x, v)		(BIT_CLEAR_GPIO_IO_SEL_15_TO_8(x) | BIT_GPIO_IO_SEL_15_TO_8(v))

#define BIT_SHIFT_GPIO_OUT_15_TO_8			8
#define BIT_MASK_GPIO_OUT_15_TO_8			0xff
#define BIT_GPIO_OUT_15_TO_8(x)			(((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8)
#define BITS_GPIO_OUT_15_TO_8				(BIT_MASK_GPIO_OUT_15_TO_8 << BIT_SHIFT_GPIO_OUT_15_TO_8)
#define BIT_CLEAR_GPIO_OUT_15_TO_8(x)			((x) & (~BITS_GPIO_OUT_15_TO_8))
#define BIT_GET_GPIO_OUT_15_TO_8(x)			(((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8)
#define BIT_SET_GPIO_OUT_15_TO_8(x, v)			(BIT_CLEAR_GPIO_OUT_15_TO_8(x) | BIT_GPIO_OUT_15_TO_8(v))

#define BIT_SHIFT_GPIO_IN_15_TO_8			0
#define BIT_MASK_GPIO_IN_15_TO_8			0xff
#define BIT_GPIO_IN_15_TO_8(x)				(((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8)
#define BITS_GPIO_IN_15_TO_8				(BIT_MASK_GPIO_IN_15_TO_8 << BIT_SHIFT_GPIO_IN_15_TO_8)
#define BIT_CLEAR_GPIO_IN_15_TO_8(x)			((x) & (~BITS_GPIO_IN_15_TO_8))
#define BIT_GET_GPIO_IN_15_TO_8(x)			(((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8)
#define BIT_SET_GPIO_IN_15_TO_8(x, v)			(BIT_CLEAR_GPIO_IN_15_TO_8(x) | BIT_GPIO_IN_15_TO_8(v))

#define BIT_SHIFT_SDIO_H2C_MSG				0
#define BIT_MASK_SDIO_H2C_MSG				0xffffffffL
#define BIT_SDIO_H2C_MSG(x)				(((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG)
#define BITS_SDIO_H2C_MSG				(BIT_MASK_SDIO_H2C_MSG << BIT_SHIFT_SDIO_H2C_MSG)
#define BIT_CLEAR_SDIO_H2C_MSG(x)			((x) & (~BITS_SDIO_H2C_MSG))
#define BIT_GET_SDIO_H2C_MSG(x)			(((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG)
#define BIT_SET_SDIO_H2C_MSG(x, v)			(BIT_CLEAR_SDIO_H2C_MSG(x) | BIT_SDIO_H2C_MSG(v))

/* 2 REG_PAD_CTRL1				(Offset 0x0064) */

#define BIT_BT_BTG_SEL					BIT(31)
#define BIT_BT_SWGPIO_SEL				BIT(29)
#define BIT_BT_SWGPIO89_1_EN				BIT(28)
#define BIT_BT_SWGPIO_3DGLEN				BIT(27)
#define BIT_BT_SWGPIO89_EN				BIT(26)
#define BIT_BT_SWGPIO10_EN				BIT(25)
#define BIT_BTGP_JTAG_EN				BIT(24)
#define BIT_XTAL_CLK_EXTARNAL_EN			BIT(23)
#define BIT_BTGP_UART0_EN				BIT(22)
#define BIT_SDIO_SUS_DIS_LD15				BIT(21)
#define BIT_BTGP_SPI_EN				BIT(20)
#define BIT_BTGP_GPIO_E2				BIT(19)
#define BIT_BTGP_GPIO_EN				BIT(18)

#define BIT_SHIFT_BTGP_GPIO_FSL			16
#define BIT_MASK_BTGP_GPIO_FSL				0x3
#define BIT_BTGP_GPIO_FSL(x)				(((x) & BIT_MASK_BTGP_GPIO_FSL) << BIT_SHIFT_BTGP_GPIO_FSL)
#define BITS_BTGP_GPIO_FSL				(BIT_MASK_BTGP_GPIO_FSL << BIT_SHIFT_BTGP_GPIO_FSL)
#define BIT_CLEAR_BTGP_GPIO_FSL(x)			((x) & (~BITS_BTGP_GPIO_FSL))
#define BIT_GET_BTGP_GPIO_FSL(x)			(((x) >> BIT_SHIFT_BTGP_GPIO_FSL) & BIT_MASK_BTGP_GPIO_FSL)
#define BIT_SET_BTGP_GPIO_FSL(x, v)			(BIT_CLEAR_BTGP_GPIO_FSL(x) | BIT_BTGP_GPIO_FSL(v))

#define BIT_PDN_FSM_WAIT				BIT(15)
#define BIT_PAD_SDIO_SR				BIT(14)
#define BIT_GPIO15_OUTPUT_PL				BIT(13)
#define BIT_HOST_WAKE_PAD_PULL_EN			BIT(12)
#define BIT_HOST_WAKE_PAD_SL				BIT(11)
#define BIT_PAD_LNAON_SR				BIT(10)
#define BIT_PAD_LNAON_E2				BIT(9)
#define BIT_SW_LNAON_G_SEL_DATA			BIT(8)
#define BIT_SW_LNAON_A_SEL_DATA			BIT(7)
#define BIT_PAD_PAPE_SR				BIT(6)
#define BIT_PAD_PAPE_E2				BIT(5)
#define BIT_SW_PAPE_G_SEL_DATA				BIT(4)
#define BIT_SW_PAPE_A_SEL_DATA				BIT(3)
#define BIT_PAD_DPDT_SR				BIT(2)
#define BIT_PAD_DPDT_PAD_E2				BIT(1)
#define BIT_SW_DPDT_SEL_DATA				BIT(0)

#define BIT_SHIFT_SDIO_C2H_MSG				0
#define BIT_MASK_SDIO_C2H_MSG				0xffffffffL
#define BIT_SDIO_C2H_MSG(x)				(((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG)
#define BITS_SDIO_C2H_MSG				(BIT_MASK_SDIO_C2H_MSG << BIT_SHIFT_SDIO_C2H_MSG)
#define BIT_CLEAR_SDIO_C2H_MSG(x)			((x) & (~BITS_SDIO_C2H_MSG))
#define BIT_GET_SDIO_C2H_MSG(x)			(((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG)
#define BIT_SET_SDIO_C2H_MSG(x, v)			(BIT_CLEAR_SDIO_C2H_MSG(x) | BIT_SDIO_C2H_MSG(v))

/* 2 REG_WL_BT_PWR_CTRL			(Offset 0x0068) */

#define BIT_ISO_BD2PP					BIT(31)
#define BIT_CKEN_BTGPS					BIT(29)
#define BIT_FEN_BTGPS					BIT(28)
#define BIT_BTCPU_BOOTSEL				BIT(27)
#define BIT_SPI_SPEEDUP				BIT(26)
#define BIT_BTPLL_LDO_MODE				BIT(25)
#define BIT_DEVWAKE_PAD_TYPE_SEL			BIT(24)
#define BIT_CLKREQ_PAD_TYPE_SEL			BIT(23)
#define BIT_WL_RTS_EXT_32K_SEL				BIT(22)
#define BIT_BT_HWROF_EN				BIT(19)
#define BIT_BT_FUNC_EN					BIT(18)
#define BIT_BT_HWPDN_SL				BIT(17)
#define BIT_BT_DISN_EN					BIT(16)
#define BIT_BT_PDN_PULL_EN				BIT(15)
#define BIT_WL_PDN_PULL_EN				BIT(14)
#define BIT_EXTERNAL_REQUEST_PL			BIT(13)
#define BIT_GPIO0_2_3_PULL_LOW_EN			BIT(12)
#define BIT_ISO_BA2PP					BIT(11)
#define BIT_BT_AFE_LDO_EN				BIT(10)
#define BIT_BT_AFE_PLL_EN				BIT(9)
#define BIT_BT_DIG_CLK_EN				BIT(8)
#define BIT_EEPROM_PD					BIT(7)
#define BIT_TESTMOD_PD					BIT(6)
#define BIT_UARTSEL_PD					BIT(5)
#define BIT_BIT_DOP_EHPAD				BIT(4)
#define BIT_WL_HWROF_EN				BIT(3)
#define BIT_WL_FUNC_EN					BIT(2)
#define BIT_WL_HWPDN_SL				BIT(1)
#define BIT_WL_HWPDN_EN				BIT(0)

/* 2 REG_BT_SCAN_MISC			(Offset 0x006C) */

#define BIT_SCAN_BT_PLL_LDO				BIT(3)
#define BIT_SCAN_BT_ADDA_LDO				BIT(2)
#define BIT_SCAN_BT_AFELDO_PC				BIT(1)
#define BIT_SCAN_BT_AFEPLL				BIT(0)

/* 2 REG_SYS_SDIO_CTRL			(Offset 0x0070) */

#define BIT_SW_GNT_WL					BIT(31)
#define BIT_SW_GNT_BT_RFC				BIT(30)
#define BIT_SW_GNT_BT_BB				BIT(29)
#define BIT_SW_CTRL_BTCOEX				BIT(28)
#define BIT_LTE_MUX_CTRL_PATH				BIT(26)
#define BIT_SDIO_ON_HWPDN_EN				BIT(20)
#define BIT_SDIO_INT_POLARITY				BIT(19)
#define BIT_SDIO_INT					BIT(18)
#define BIT_SDIO_OFF_EN				BIT(17)
#define BIT_SDIO_ON_EN					BIT(16)
#define BIT_PCIERR_SUS					BIT(10)
#define BIT_PCI_PLL_ERR				BIT(9)

/* 2 REG_HCI_OPT_CTRL			(Offset 0x0074) */

#define BIT_SHIFT_RFC1_EN				24
#define BIT_MASK_RFC1_EN				0xff
#define BIT_RFC1_EN(x)					(((x) & BIT_MASK_RFC1_EN) << BIT_SHIFT_RFC1_EN)
#define BITS_RFC1_EN					(BIT_MASK_RFC1_EN << BIT_SHIFT_RFC1_EN)
#define BIT_CLEAR_RFC1_EN(x)				((x) & (~BITS_RFC1_EN))
#define BIT_GET_RFC1_EN(x)				(((x) >> BIT_SHIFT_RFC1_EN) & BIT_MASK_RFC1_EN)
#define BIT_SET_RFC1_EN(x, v)				(BIT_CLEAR_RFC1_EN(x) | BIT_RFC1_EN(v))

#define BIT_USB2_ALDO_ACT				BIT(21)
#define BIT_SDIO_SMT					BIT(20)
#define BIT_SDIO_H3L1					BIT(19)
#define BIT_SDIO_PAD_E5				BIT(18)
#define BIT_NO_PWR_SEL					BIT(13)
#define BIT_USB_HOST_PWR_OFF_EN			BIT(12)
#define BIT_SYM_LPS_BLOCK_EN				BIT(11)
#define BIT_USB_LPM_ACT_EN				BIT(10)
#define BIT_USB_LPM_NY					BIT(9)
#define BIT_USB_SUS_DIS				BIT(8)
#define BIT_SDIO_PAD_E2				BIT(7)

#define BIT_SHIFT_SDIO_PAD_E				5
#define BIT_MASK_SDIO_PAD_E				0x3
#define BIT_SDIO_PAD_E(x)				(((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E)
#define BITS_SDIO_PAD_E				(BIT_MASK_SDIO_PAD_E << BIT_SHIFT_SDIO_PAD_E)
#define BIT_CLEAR_SDIO_PAD_E(x)			((x) & (~BITS_SDIO_PAD_E))
#define BIT_GET_SDIO_PAD_E(x)				(((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E)
#define BIT_SET_SDIO_PAD_E(x, v)			(BIT_CLEAR_SDIO_PAD_E(x) | BIT_SDIO_PAD_E(v))

#define BIT_USB_LPPLL_EN				BIT(4)
#define BIT_ROP_SW15					BIT(2)
#define BIT_PCI_CKRDY_OPT				BIT(1)
#define BIT_PCI_VAUX_EN				BIT(0)

/* 2 REG_EFUSE_FW_SECURE_CTRL		(Offset 0x0078) */

#define BIT_EF_SEC_COMP_RESULT				BIT(27)

#define BIT_SHIFT_EF_SEC_COMPARE_DATA			0
#define BIT_MASK_EF_SEC_COMPARE_DATA			0xffff
#define BIT_EF_SEC_COMPARE_DATA(x)			(((x) & BIT_MASK_EF_SEC_COMPARE_DATA) << BIT_SHIFT_EF_SEC_COMPARE_DATA)
#define BITS_EF_SEC_COMPARE_DATA			(BIT_MASK_EF_SEC_COMPARE_DATA << BIT_SHIFT_EF_SEC_COMPARE_DATA)
#define BIT_CLEAR_EF_SEC_COMPARE_DATA(x)		((x) & (~BITS_EF_SEC_COMPARE_DATA))
#define BIT_GET_EF_SEC_COMPARE_DATA(x)			(((x) >> BIT_SHIFT_EF_SEC_COMPARE_DATA) & BIT_MASK_EF_SEC_COMPARE_DATA)
#define BIT_SET_EF_SEC_COMPARE_DATA(x, v)		(BIT_CLEAR_EF_SEC_COMPARE_DATA(x) | BIT_EF_SEC_COMPARE_DATA(v))

/* 2 REG_LDO_SWR_CTRL			(Offset 0x007C) */

#define BIT_R_SYM_CHG_ZCD_INIT_VAL			BIT(28)
#define BIT_R_SYM_ZCD_HW_AUTO_EN			BIT(27)
#define BIT_R_SYM_ZCD_REG_SEL				BIT(26)

#define BIT_SHIFT_AUTO_ZCD_IN_CODE			21
#define BIT_MASK_AUTO_ZCD_IN_CODE			0x1f
#define BIT_AUTO_ZCD_IN_CODE(x)			(((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE)
#define BITS_AUTO_ZCD_IN_CODE				(BIT_MASK_AUTO_ZCD_IN_CODE << BIT_SHIFT_AUTO_ZCD_IN_CODE)
#define BIT_CLEAR_AUTO_ZCD_IN_CODE(x)			((x) & (~BITS_AUTO_ZCD_IN_CODE))
#define BIT_GET_AUTO_ZCD_IN_CODE(x)			(((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE)
#define BIT_SET_AUTO_ZCD_IN_CODE(x, v)			(BIT_CLEAR_AUTO_ZCD_IN_CODE(x) | BIT_AUTO_ZCD_IN_CODE(v))

#define BIT_SHIFT_REG_ZCD_CODE_IN_L			16
#define BIT_MASK_REG_ZCD_CODE_IN_L			0x1f
#define BIT_REG_ZCD_CODE_IN_L(x)			(((x) & BIT_MASK_REG_ZCD_CODE_IN_L) << BIT_SHIFT_REG_ZCD_CODE_IN_L)
#define BITS_REG_ZCD_CODE_IN_L				(BIT_MASK_REG_ZCD_CODE_IN_L << BIT_SHIFT_REG_ZCD_CODE_IN_L)
#define BIT_CLEAR_REG_ZCD_CODE_IN_L(x)			((x) & (~BITS_REG_ZCD_CODE_IN_L))
#define BIT_GET_REG_ZCD_CODE_IN_L(x)			(((x) >> BIT_SHIFT_REG_ZCD_CODE_IN_L) & BIT_MASK_REG_ZCD_CODE_IN_L)
#define BIT_SET_REG_ZCD_CODE_IN_L(x, v)		(BIT_CLEAR_REG_ZCD_CODE_IN_L(x) | BIT_REG_ZCD_CODE_IN_L(v))

/* 2 REG_MCUFW_CTRL				(Offset 0x0080) */

#define BIT_SHIFT_RPWM					24
#define BIT_MASK_RPWM					0xff
#define BIT_RPWM(x)					(((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM)
#define BITS_RPWM					(BIT_MASK_RPWM << BIT_SHIFT_RPWM)
#define BIT_CLEAR_RPWM(x)				((x) & (~BITS_RPWM))
#define BIT_GET_RPWM(x)				(((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM)
#define BIT_SET_RPWM(x, v)				(BIT_CLEAR_RPWM(x) | BIT_RPWM(v))

#define BIT_CPRST					BIT(23)
#define BIT_ANA_PORT_EN				BIT(22)
#define BIT_MAC_PORT_EN				BIT(21)
#define BIT_BOOT_FSPI_EN				BIT(20)
#define BIT_ROM_DLEN					BIT(19)

#define BIT_SHIFT_ROM_PGE				16
#define BIT_MASK_ROM_PGE				0x7
#define BIT_ROM_PGE(x)					(((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE)
#define BITS_ROM_PGE					(BIT_MASK_ROM_PGE << BIT_SHIFT_ROM_PGE)
#define BIT_CLEAR_ROM_PGE(x)				((x) & (~BITS_ROM_PGE))
#define BIT_GET_ROM_PGE(x)				(((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE)
#define BIT_SET_ROM_PGE(x, v)				(BIT_CLEAR_ROM_PGE(x) | BIT_ROM_PGE(v))

#define BIT_FW_INIT_RDY				BIT(15)
#define BIT_FW_DW_RDY					BIT(14)

#define BIT_SHIFT_CPU_CLK_SEL				12
#define BIT_MASK_CPU_CLK_SEL				0x3
#define BIT_CPU_CLK_SEL(x)				(((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL)
#define BITS_CPU_CLK_SEL				(BIT_MASK_CPU_CLK_SEL << BIT_SHIFT_CPU_CLK_SEL)
#define BIT_CLEAR_CPU_CLK_SEL(x)			((x) & (~BITS_CPU_CLK_SEL))
#define BIT_GET_CPU_CLK_SEL(x)				(((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL)
#define BIT_SET_CPU_CLK_SEL(x, v)			(BIT_CLEAR_CPU_CLK_SEL(x) | BIT_CPU_CLK_SEL(v))

#define BIT_ANA_PORT_IDLE				BIT(11)
#define BIT_MAC_PORT_IDLE				BIT(10)
#define BIT_EMEM_CHKSUM_OK				BIT(8)
#define BIT_EMEM_DW_OK					BIT(7)
#define BIT_TOGGLE					BIT(7)
#define BIT_DMEM_CHKSUM_OK				BIT(6)
#define BIT_ACK					BIT(6)
#define BIT_DMEM_DW_OK					BIT(5)
#define BIT_IMEM_CHKSUM_OK				BIT(4)
#define BIT_IMEM_DW_OK					BIT(3)
#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK			BIT(2)
#define BIT_IMEM_BOOT_LOAD_DW_OK			BIT(1)
#define BIT_MCUFWDL_EN					BIT(0)
#define BIT_REQ_PS					BIT(0)

/* 2 REG_MCU_TST_CFG				(Offset 0x0084) */

#define BIT_SHIFT_LBKTST				0
#define BIT_MASK_LBKTST				0xffff
#define BIT_LBKTST(x)					(((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST)
#define BITS_LBKTST					(BIT_MASK_LBKTST << BIT_SHIFT_LBKTST)
#define BIT_CLEAR_LBKTST(x)				((x) & (~BITS_LBKTST))
#define BIT_GET_LBKTST(x)				(((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST)
#define BIT_SET_LBKTST(x, v)				(BIT_CLEAR_LBKTST(x) | BIT_LBKTST(v))

/* 2 REG_SDIO_BUS_CTRL			(Offset 0x10250085) */

#define BIT_HISR_W_CLR_EN				BIT(5)
#define BIT_INT_MASK_DIS				BIT(4)
#define BIT_PAD_CLK_XHGE_EN				BIT(3)
#define BIT_INTER_CLK_EN				BIT(2)
#define BIT_EN_RPT_TXCRC				BIT(1)
#define BIT_DIS_RXDMA_STS				BIT(0)

/* 2 REG_SDIO_HSUS_CTRL			(Offset 0x10250086) */

#define BIT_INTR_CTRL					BIT(4)
#define BIT_SDIO_VOLTAGE				BIT(3)
#define BIT_BYPASS_INIT				BIT(2)
#define BIT_HCI_RESUME_RDY				BIT(1)
#define BIT_HCI_SUS_REQ				BIT(0)

/* 2 REG_HMEBOX_E0_E1			(Offset 0x0088) */

#define BIT_SHIFT_HOST_MSG_E1				16
#define BIT_MASK_HOST_MSG_E1				0xffff
#define BIT_HOST_MSG_E1(x)				(((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1)
#define BITS_HOST_MSG_E1				(BIT_MASK_HOST_MSG_E1 << BIT_SHIFT_HOST_MSG_E1)
#define BIT_CLEAR_HOST_MSG_E1(x)			((x) & (~BITS_HOST_MSG_E1))
#define BIT_GET_HOST_MSG_E1(x)				(((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1)
#define BIT_SET_HOST_MSG_E1(x, v)			(BIT_CLEAR_HOST_MSG_E1(x) | BIT_HOST_MSG_E1(v))

#define BIT_SHIFT_HOST_MSG_E0				0
#define BIT_MASK_HOST_MSG_E0				0xffff
#define BIT_HOST_MSG_E0(x)				(((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0)
#define BITS_HOST_MSG_E0				(BIT_MASK_HOST_MSG_E0 << BIT_SHIFT_HOST_MSG_E0)
#define BIT_CLEAR_HOST_MSG_E0(x)			((x) & (~BITS_HOST_MSG_E0))
#define BIT_GET_HOST_MSG_E0(x)				(((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0)
#define BIT_SET_HOST_MSG_E0(x, v)			(BIT_CLEAR_HOST_MSG_E0(x) | BIT_HOST_MSG_E0(v))

#define BIT_SHIFT_CMDIN_2RESP_TIMER			0
#define BIT_MASK_CMDIN_2RESP_TIMER			0xffff
#define BIT_CMDIN_2RESP_TIMER(x)			(((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER)
#define BITS_CMDIN_2RESP_TIMER				(BIT_MASK_CMDIN_2RESP_TIMER << BIT_SHIFT_CMDIN_2RESP_TIMER)
#define BIT_CLEAR_CMDIN_2RESP_TIMER(x)			((x) & (~BITS_CMDIN_2RESP_TIMER))
#define BIT_GET_CMDIN_2RESP_TIMER(x)			(((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER)
#define BIT_SET_CMDIN_2RESP_TIMER(x, v)		(BIT_CLEAR_CMDIN_2RESP_TIMER(x) | BIT_CMDIN_2RESP_TIMER(v))

/* 2 REG_SDIO_CMD_CRC			(Offset 0x1025008A) */

#define BIT_SHIFT_SDIO_CMD_CRC_V1			0
#define BIT_MASK_SDIO_CMD_CRC_V1			0xff
#define BIT_SDIO_CMD_CRC_V1(x)				(((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1)
#define BITS_SDIO_CMD_CRC_V1				(BIT_MASK_SDIO_CMD_CRC_V1 << BIT_SHIFT_SDIO_CMD_CRC_V1)
#define BIT_CLEAR_SDIO_CMD_CRC_V1(x)			((x) & (~BITS_SDIO_CMD_CRC_V1))
#define BIT_GET_SDIO_CMD_CRC_V1(x)			(((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1)
#define BIT_SET_SDIO_CMD_CRC_V1(x, v)			(BIT_CLEAR_SDIO_CMD_CRC_V1(x) | BIT_SDIO_CMD_CRC_V1(v))

/* 2 REG_HMEBOX_E2_E3			(Offset 0x008C) */

#define BIT_SHIFT_HOST_MSG_E3				16
#define BIT_MASK_HOST_MSG_E3				0xffff
#define BIT_HOST_MSG_E3(x)				(((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3)
#define BITS_HOST_MSG_E3				(BIT_MASK_HOST_MSG_E3 << BIT_SHIFT_HOST_MSG_E3)
#define BIT_CLEAR_HOST_MSG_E3(x)			((x) & (~BITS_HOST_MSG_E3))
#define BIT_GET_HOST_MSG_E3(x)				(((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3)
#define BIT_SET_HOST_MSG_E3(x, v)			(BIT_CLEAR_HOST_MSG_E3(x) | BIT_HOST_MSG_E3(v))

#define BIT_SHIFT_HOST_MSG_E2				0
#define BIT_MASK_HOST_MSG_E2				0xffff
#define BIT_HOST_MSG_E2(x)				(((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2)
#define BITS_HOST_MSG_E2				(BIT_MASK_HOST_MSG_E2 << BIT_SHIFT_HOST_MSG_E2)
#define BIT_CLEAR_HOST_MSG_E2(x)			((x) & (~BITS_HOST_MSG_E2))
#define BIT_GET_HOST_MSG_E2(x)				(((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2)
#define BIT_SET_HOST_MSG_E2(x, v)			(BIT_CLEAR_HOST_MSG_E2(x) | BIT_HOST_MSG_E2(v))

/* 2 REG_WLLPS_CTRL				(Offset 0x0090) */

#define BIT_WLLPSOP_EABM				BIT(31)
#define BIT_WLLPSOP_ACKF				BIT(30)
#define BIT_WLLPSOP_DLDM				BIT(29)
#define BIT_WLLPSOP_ESWR				BIT(28)
#define BIT_WLLPSOP_PWMM				BIT(27)
#define BIT_WLLPSOP_EECK				BIT(26)
#define BIT_WLLPS_LDO_STEP				BIT(25)
#define BIT_WLLPSOP_EXTAL				BIT(24)
#define BIT_WLLPSOP_EXTAL_LPS				BIT(20)
#define BIT_WL_LPS_MEMPM_EN				BIT(19)
#define BIT_WLLPSOP_WPLN				BIT(17)
#define BIT_WLPOF_POWOF				BIT(16)
#define BIT_WL_OPT_PON_DA				BIT(15)
#define BIT_WLLPSOP_WLDO_VOLT				BIT(14)
#define BIT_WLLPSOP_ALDM				BIT(13)
#define BIT_WLLPSOP_LDOM				BIT(12)
#define BIT_WLLPSOP_ELLD				BIT(11)
#define BIT_WLLPSOP_WT_CPU_SLP				BIT(10)
#define BIT_WLLPSOP_SKIP_CG				BIT(9)
#define BIT_WLLPSOP_SD1_ON				BIT(8)
#define BIT_LPSOP_HCIM					BIT(7)
#define BIT_LPSOP_SHCI					BIT(6)
#define BIT_DRV_WLAN_INT_CLR				BIT(1)
#define BIT_WL_LPS_EN					BIT(0)
#define BIT_DRV_WLAN_INT				BIT(0)

/* 2 REG_SDIO_HSIMR				(Offset 0x10250091) */

#define BIT_HISR_MASK					BIT(0)

/* 2 REG_MEM_POW_CTRL			(Offset 0x0094) */

#define BIT_SHIFT_USB_SUS_MEMPM_SEL			22
#define BIT_MASK_USB_SUS_MEMPM_SEL			0x3
#define BIT_USB_SUS_MEMPM_SEL(x)			(((x) & BIT_MASK_USB_SUS_MEMPM_SEL) << BIT_SHIFT_USB_SUS_MEMPM_SEL)
#define BITS_USB_SUS_MEMPM_SEL				(BIT_MASK_USB_SUS_MEMPM_SEL << BIT_SHIFT_USB_SUS_MEMPM_SEL)
#define BIT_CLEAR_USB_SUS_MEMPM_SEL(x)			((x) & (~BITS_USB_SUS_MEMPM_SEL))
#define BIT_GET_USB_SUS_MEMPM_SEL(x)			(((x) >> BIT_SHIFT_USB_SUS_MEMPM_SEL) & BIT_MASK_USB_SUS_MEMPM_SEL)
#define BIT_SET_USB_SUS_MEMPM_SEL(x, v)		(BIT_CLEAR_USB_SUS_MEMPM_SEL(x) | BIT_USB_SUS_MEMPM_SEL(v))

#define BIT_SHIFT_WL_LPS_MEMPM_WLOFF			16
#define BIT_MASK_WL_LPS_MEMPM_WLOFF			0x3f
#define BIT_WL_LPS_MEMPM_WLOFF(x)			(((x) & BIT_MASK_WL_LPS_MEMPM_WLOFF) << BIT_SHIFT_WL_LPS_MEMPM_WLOFF)
#define BITS_WL_LPS_MEMPM_WLOFF			(BIT_MASK_WL_LPS_MEMPM_WLOFF << BIT_SHIFT_WL_LPS_MEMPM_WLOFF)
#define BIT_CLEAR_WL_LPS_MEMPM_WLOFF(x)		((x) & (~BITS_WL_LPS_MEMPM_WLOFF))
#define BIT_GET_WL_LPS_MEMPM_WLOFF(x)			(((x) >> BIT_SHIFT_WL_LPS_MEMPM_WLOFF) & BIT_MASK_WL_LPS_MEMPM_WLOFF)
#define BIT_SET_WL_LPS_MEMPM_WLOFF(x, v)		(BIT_CLEAR_WL_LPS_MEMPM_WLOFF(x) | BIT_WL_LPS_MEMPM_WLOFF(v))

#define BIT_SHIFT_WL_LPS_MEMPM_WLPON			0
#define BIT_MASK_WL_LPS_MEMPM_WLPON			0x3fff
#define BIT_WL_LPS_MEMPM_WLPON(x)			(((x) & BIT_MASK_WL_LPS_MEMPM_WLPON) << BIT_SHIFT_WL_LPS_MEMPM_WLPON)
#define BITS_WL_LPS_MEMPM_WLPON			(BIT_MASK_WL_LPS_MEMPM_WLPON << BIT_SHIFT_WL_LPS_MEMPM_WLPON)
#define BIT_CLEAR_WL_LPS_MEMPM_WLPON(x)		((x) & (~BITS_WL_LPS_MEMPM_WLPON))
#define BIT_GET_WL_LPS_MEMPM_WLPON(x)			(((x) >> BIT_SHIFT_WL_LPS_MEMPM_WLPON) & BIT_MASK_WL_LPS_MEMPM_WLPON)
#define BIT_SET_WL_LPS_MEMPM_WLPON(x, v)		(BIT_CLEAR_WL_LPS_MEMPM_WLPON(x) | BIT_WL_LPS_MEMPM_WLPON(v))

/* 2 REG_GPIO_DEBOUNCE_CTRL			(Offset 0x0098) */

#define BIT_WLGP_DBC1EN				BIT(15)

#define BIT_SHIFT_WLGP_DBC1				8
#define BIT_MASK_WLGP_DBC1				0xf
#define BIT_WLGP_DBC1(x)				(((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1)
#define BITS_WLGP_DBC1					(BIT_MASK_WLGP_DBC1 << BIT_SHIFT_WLGP_DBC1)
#define BIT_CLEAR_WLGP_DBC1(x)				((x) & (~BITS_WLGP_DBC1))
#define BIT_GET_WLGP_DBC1(x)				(((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1)
#define BIT_SET_WLGP_DBC1(x, v)			(BIT_CLEAR_WLGP_DBC1(x) | BIT_WLGP_DBC1(v))

#define BIT_WLGP_DBC0EN				BIT(7)

#define BIT_SHIFT_WLGP_DBC0				0
#define BIT_MASK_WLGP_DBC0				0xf
#define BIT_WLGP_DBC0(x)				(((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0)
#define BITS_WLGP_DBC0					(BIT_MASK_WLGP_DBC0 << BIT_SHIFT_WLGP_DBC0)
#define BIT_CLEAR_WLGP_DBC0(x)				((x) & (~BITS_WLGP_DBC0))
#define BIT_GET_WLGP_DBC0(x)				(((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0)
#define BIT_SET_WLGP_DBC0(x, v)			(BIT_CLEAR_WLGP_DBC0(x) | BIT_WLGP_DBC0(v))

/* 2 REG_RPWM2				(Offset 0x009C) */

#define BIT_SHIFT_RPWM2				16
#define BIT_MASK_RPWM2					0xffff
#define BIT_RPWM2(x)					(((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2)
#define BITS_RPWM2					(BIT_MASK_RPWM2 << BIT_SHIFT_RPWM2)
#define BIT_CLEAR_RPWM2(x)				((x) & (~BITS_RPWM2))
#define BIT_GET_RPWM2(x)				(((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2)
#define BIT_SET_RPWM2(x, v)				(BIT_CLEAR_RPWM2(x) | BIT_RPWM2(v))

/* 2 REG_SYSON_FSM_MON			(Offset 0x00A0) */

#define BIT_SHIFT_FSM_MON_SEL				24
#define BIT_MASK_FSM_MON_SEL				0x7
#define BIT_FSM_MON_SEL(x)				(((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL)
#define BITS_FSM_MON_SEL				(BIT_MASK_FSM_MON_SEL << BIT_SHIFT_FSM_MON_SEL)
#define BIT_CLEAR_FSM_MON_SEL(x)			((x) & (~BITS_FSM_MON_SEL))
#define BIT_GET_FSM_MON_SEL(x)				(((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL)
#define BIT_SET_FSM_MON_SEL(x, v)			(BIT_CLEAR_FSM_MON_SEL(x) | BIT_FSM_MON_SEL(v))

#define BIT_DOP_ELDO_WL				BIT(23)
#define BIT_DOP_ELDO_BT				BIT(22)
#define BIT_FSM_MON_UPD				BIT(15)

#define BIT_SHIFT_FSM_PAR				0
#define BIT_MASK_FSM_PAR				0x7fff
#define BIT_FSM_PAR(x)					(((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR)
#define BITS_FSM_PAR					(BIT_MASK_FSM_PAR << BIT_SHIFT_FSM_PAR)
#define BIT_CLEAR_FSM_PAR(x)				((x) & (~BITS_FSM_PAR))
#define BIT_GET_FSM_PAR(x)				(((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR)
#define BIT_SET_FSM_PAR(x, v)				(BIT_CLEAR_FSM_PAR(x) | BIT_FSM_PAR(v))

/* 2 REG_EXT_HCI_OPT				(Offset 0x00A4) */

#define BIT_SYS_USB_GLITCH_RSM_EN			BIT(10)
#define BIT_BT_UPHY_CTRL_GNT				BIT(9)
#define BIT_WL_UPHY_CTRL_GNT				BIT(8)
#define BIT_BT_UPHY_CTRL_REQ				BIT(7)
#define BIT_WL_UPHY_CTRL_REQ				BIT(6)
#define BIT_HUSB_RSM_DIS				BIT(5)
#define BIT_USB_FORCE_DP				BIT(4)
#define BIT_USB_DP_MODE				BIT(3)

#define BIT_SHIFT_TSFT_SEL_V1				0
#define BIT_MASK_TSFT_SEL_V1				0x7
#define BIT_TSFT_SEL_V1(x)				(((x) & BIT_MASK_TSFT_SEL_V1) << BIT_SHIFT_TSFT_SEL_V1)
#define BITS_TSFT_SEL_V1				(BIT_MASK_TSFT_SEL_V1 << BIT_SHIFT_TSFT_SEL_V1)
#define BIT_CLEAR_TSFT_SEL_V1(x)			((x) & (~BITS_TSFT_SEL_V1))
#define BIT_GET_TSFT_SEL_V1(x)				(((x) >> BIT_SHIFT_TSFT_SEL_V1) & BIT_MASK_TSFT_SEL_V1)
#define BIT_SET_TSFT_SEL_V1(x, v)			(BIT_CLEAR_TSFT_SEL_V1(x) | BIT_TSFT_SEL_V1(v))

/* 2 REG_PMC_DBG_CTRL1			(Offset 0x00A8) */

#define BIT_PMC_WR_OVF					BIT(8)

#define BIT_SHIFT_WLPMC_ERRINT				0
#define BIT_MASK_WLPMC_ERRINT				0xff
#define BIT_WLPMC_ERRINT(x)				(((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT)
#define BITS_WLPMC_ERRINT				(BIT_MASK_WLPMC_ERRINT << BIT_SHIFT_WLPMC_ERRINT)
#define BIT_CLEAR_WLPMC_ERRINT(x)			((x) & (~BITS_WLPMC_ERRINT))
#define BIT_GET_WLPMC_ERRINT(x)			(((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT)
#define BIT_SET_WLPMC_ERRINT(x, v)			(BIT_CLEAR_WLPMC_ERRINT(x) | BIT_WLPMC_ERRINT(v))

/* 2 REG_SCOREBOARD_CTRL			(Offset 0x00AC) */

#define BIT_BT_INT_EN					BIT(31)

#define BIT_SHIFT_RD_WR_WIFI_BT_INFO			0
#define BIT_MASK_RD_WR_WIFI_BT_INFO			0x7fffffffL
#define BIT_RD_WR_WIFI_BT_INFO(x)			(((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO)
#define BITS_RD_WR_WIFI_BT_INFO			(BIT_MASK_RD_WR_WIFI_BT_INFO << BIT_SHIFT_RD_WR_WIFI_BT_INFO)
#define BIT_CLEAR_RD_WR_WIFI_BT_INFO(x)		((x) & (~BITS_RD_WR_WIFI_BT_INFO))
#define BIT_GET_RD_WR_WIFI_BT_INFO(x)			(((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO)
#define BIT_SET_RD_WR_WIFI_BT_INFO(x, v)		(BIT_CLEAR_RD_WR_WIFI_BT_INFO(x) | BIT_RD_WR_WIFI_BT_INFO(v))

/* 2 REG_HIMR0				(Offset 0x00B0) */

#define BIT_PSTIMEOUT2_MSK				BIT(31)
#define BIT_PSTIMEOUT1_MSK				BIT(30)
#define BIT_PSTIMEOUT_MSK				BIT(29)
#define BIT_GTINT4_MSK					BIT(28)
#define BIT_GTINT3_MSK					BIT(27)
#define BIT_TXBCN0ERR_MSK				BIT(26)
#define BIT_TXBCN0OK_MSK				BIT(25)
#define BIT_TSF_BIT32_TOGGLE_MSK			BIT(24)
#define BIT_TXBCN7ERR_MSK				BIT(23)
#define BIT_TXBCN6ERR_MSK				BIT(22)
#define BIT_TXBCN5ERR_MSK				BIT(21)
#define BIT_BCNDMAINT0_MSK				BIT(20)
#define BIT_BCNDMAINT_P4_MSK				BIT(19)
#define BIT_BCNDMAINT_P3_MSK				BIT(18)
#define BIT_TXBCN4ERR_MSK				BIT(16)
#define BIT_HSISR_IND_ON_INT_MSK			BIT(15)
#define BIT_BCNDMAINT_P1_MSK				BIT(14)
#define BIT_BCNDMAINT_P2_MSK				BIT(13)
#define BIT_CTWEND_MSK					BIT(12)
#define BIT_HISR1_IND_INT_MSK				BIT(11)
#define BIT_C2HCMD_MSK					BIT(10)
#define BIT_CPWM2_MSK					BIT(9)
#define BIT_CPWM_MSK					BIT(8)
#define BIT_TXBCN3ERR_MSK				BIT(7)
#define BIT_TXBCN7OK_MSK				BIT(6)
#define BIT_TXBCN6OK_MSK				BIT(5)
#define BIT_TXBCN5OK_MSK				BIT(4)
#define BIT_TXBCN4OK_MSK				BIT(3)
#define BIT_TXBCN3OK_MSK				BIT(2)
#define BIT_TXBCN2OK_MSK				BIT(1)
#define BIT_TXBCN1OK_MSK				BIT(0)

/* 2 REG_HISR0				(Offset 0x00B4) */

#define BIT_PSTIMEOUT2					BIT(31)
#define BIT_PSTIMEOUT1					BIT(30)
#define BIT_PSTIMEOUT					BIT(29)
#define BIT_GTINT4					BIT(28)
#define BIT_GTINT3					BIT(27)
#define BIT_TXBCN0ERR					BIT(26)
#define BIT_TXBCN0OK					BIT(25)
#define BIT_TSF_BIT32_TOGGLE				BIT(24)
#define BIT_TXBCN7ERR					BIT(23)
#define BIT_TXBCN6ERR					BIT(22)
#define BIT_TXBCN5ERR					BIT(21)
#define BIT_BCNDMAINT0					BIT(20)
#define BIT_BCNDMAINT_P4				BIT(19)
#define BIT_BCNDMAINT_P3				BIT(18)
#define BIT_TXBCN4ERR					BIT(16)
#define BIT_HSISR_IND_ON_INT				BIT(15)
#define BIT_BCNDMAINT_P1				BIT(14)
#define BIT_BCNDMAINT_P2				BIT(13)
#define BIT_CTWEND					BIT(12)
#define BIT_HISR1_IND_INT				BIT(11)
#define BIT_C2HCMD					BIT(10)
#define BIT_CPWM2					BIT(9)
#define BIT_CPWM					BIT(8)
#define BIT_TXBCN3ERR					BIT(7)
#define BIT_TXBCN7OK					BIT(6)
#define BIT_TXBCN6OK					BIT(5)
#define BIT_TXBCN5OK					BIT(4)
#define BIT_TXBCN4OK					BIT(3)
#define BIT_TXBCN3OK					BIT(2)
#define BIT_TXBCN2OK					BIT(1)
#define BIT_TXBCN1OK					BIT(0)

/* 2 REG_HIMR1				(Offset 0x00B8) */

#define BIT_WDT_PLATFORM_INT_IMR			BIT(31)
#define BIT_TXBCN2ERR_IMR				BIT(30)
#define BIT_BTON_STS_UPDATE_INT_IMR			BIT(29)
#define BIT_WDT_CPU_INT_IMR				BIT(28)
#define BIT_BCNDMAINT7_IMR				BIT(27)
#define BIT_BCNDMAINT6_IMR				BIT(26)
#define BIT_BCNDMAINT5_IMR				BIT(25)
#define BIT_BCNDMAINT4_IMR				BIT(24)
#define BIT_BCNDMAINT3_IMR				BIT(23)
#define BIT_BCNDMAINT2_IMR				BIT(22)
#define BIT_BCNDMAINT1_IMR				BIT(21)
#define BIT_TXBCN1ERR_IMR				BIT(20)
#define BIT_ATIMEND7__IMR				BIT(19)
#define BIT_ATIMEND6__IMR				BIT(18)
#define BIT_ATIMEND5_IMR				BIT(17)
#define BIT_ATIMEND4_IMR				BIT(16)
#define BIT_ATIMEND3_IMR				BIT(15)
#define BIT_ATIMEND2_IMR				BIT(14)
#define BIT_ATIMEND1_IMR				BIT(13)
#define BIT_ATIMEND_IMR				BIT(12)
#define BIT_TXERR_INT_IMR				BIT(11)
#define BIT_RXERR_INT_IMR				BIT(10)
#define BIT_TXFOVW_IMR					BIT(9)
#define BIT_FOVW_IMR					BIT(8)
#define BIT_DDMA0_LP_INT_IMR				BIT(7)
#define BIT_CPUMGQ_ERLY_TIMER_INT_IMR			BIT(6)
#define BIT_CPU_MGQ_TXDONE_INT_IMR			BIT(5)
#define BIT_PS_TIMER_C_INT_IMR				BIT(4)
#define BIT_PS_TIMER_B_INT_IMR				BIT(3)
#define BIT_PS_TIMER_A_INT_IMR				BIT(2)
#define BIT_CPUMGQ_TX_TIMER_INT_IMR			BIT(1)
#define BIT_DDMA0_HP_INT_IMR				BIT(0)

/* 2 REG_HISR1				(Offset 0x00BC) */

#define BIT_WDT_PLATFORM_INT_ISR			BIT(31)
#define BIT_TXBCN2ERR_ISR				BIT(30)
#define BIT_BTON_STS_UPDATE_INT_ISR			BIT(29)
#define BIT_WDT_CPU_INT_ISR				BIT(28)
#define BIT_BCNDMAINT7_ISR				BIT(27)
#define BIT_BCNDMAINT6_ISR				BIT(26)
#define BIT_BCNDMAINT5_ISR				BIT(25)
#define BIT_BCNDMAINT4_ISR				BIT(24)
#define BIT_BCNDMAINT3_ISR				BIT(23)
#define BIT_BCNDMAINT2_ISR				BIT(22)
#define BIT_BCNDMAINT1_ISR				BIT(21)
#define BIT_TXBCN1ERR_ISR				BIT(20)
#define BIT_ATIMEND7_ISR				BIT(19)
#define BIT_ATIMEND6_ISR				BIT(18)
#define BIT_ATIMEND5_ISR				BIT(17)
#define BIT_ATIMEND4_ISR				BIT(16)
#define BIT_ATIMEND3_ISR				BIT(15)
#define BIT_ATIMEND2_ISR				BIT(14)
#define BIT_ATIMEND1_ISR				BIT(13)
#define BIT_ATIMEND_ISR				BIT(12)
#define BIT_TXERR_INT_ISR				BIT(11)
#define BIT_RXERR_INT_ISR				BIT(10)
#define BIT_TXFOVW_ISR					BIT(9)
#define BIT_FOVW_ISR					BIT(8)
#define BIT_DDMA0_LP_INT_ISR				BIT(7)
#define BIT_CPUMGQ_ERLY_TIMER_INT_ISR			BIT(6)
#define BIT_CPU_MGQ_TXDONE_INT_ISR			BIT(5)
#define BIT_PS_TIMER_C_INT_ISR				BIT(4)
#define BIT_PS_TIMER_B_INT_ISR				BIT(3)
#define BIT_PS_TIMER_A_INT_ISR				BIT(2)
#define BIT_CPUMGQ_TX_TIMER_INT_ISR			BIT(1)
#define BIT_DDMA0_HP_INT_ISR				BIT(0)

/* 2 REG_DBG_PORT_SEL			(Offset 0x00C0) */

#define BIT_SHIFT_DEBUG_ST				0
#define BIT_MASK_DEBUG_ST				0xffffffffL
#define BIT_DEBUG_ST(x)				(((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST)
#define BITS_DEBUG_ST					(BIT_MASK_DEBUG_ST << BIT_SHIFT_DEBUG_ST)
#define BIT_CLEAR_DEBUG_ST(x)				((x) & (~BITS_DEBUG_ST))
#define BIT_GET_DEBUG_ST(x)				(((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST)
#define BIT_SET_DEBUG_ST(x, v)				(BIT_CLEAR_DEBUG_ST(x) | BIT_DEBUG_ST(v))

#define BIT_SDIO_PAGE_ERR				BIT(0)

/* 2 REG_SDIO_CMD_ERRCNT			(Offset 0x102500C2) */

#define BIT_SHIFT_CMD_CRC_ERR_CNT			0
#define BIT_MASK_CMD_CRC_ERR_CNT			0xff
#define BIT_CMD_CRC_ERR_CNT(x)				(((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT)
#define BITS_CMD_CRC_ERR_CNT				(BIT_MASK_CMD_CRC_ERR_CNT << BIT_SHIFT_CMD_CRC_ERR_CNT)
#define BIT_CLEAR_CMD_CRC_ERR_CNT(x)			((x) & (~BITS_CMD_CRC_ERR_CNT))
#define BIT_GET_CMD_CRC_ERR_CNT(x)			(((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT)
#define BIT_SET_CMD_CRC_ERR_CNT(x, v)			(BIT_CLEAR_CMD_CRC_ERR_CNT(x) | BIT_CMD_CRC_ERR_CNT(v))

/* 2 REG_SDIO_DATA_ERRCNT			(Offset 0x102500C3) */

#define BIT_SHIFT_DATA_CRC_ERR_CNT			0
#define BIT_MASK_DATA_CRC_ERR_CNT			0xff
#define BIT_DATA_CRC_ERR_CNT(x)			(((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT)
#define BITS_DATA_CRC_ERR_CNT				(BIT_MASK_DATA_CRC_ERR_CNT << BIT_SHIFT_DATA_CRC_ERR_CNT)
#define BIT_CLEAR_DATA_CRC_ERR_CNT(x)			((x) & (~BITS_DATA_CRC_ERR_CNT))
#define BIT_GET_DATA_CRC_ERR_CNT(x)			(((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT)
#define BIT_SET_DATA_CRC_ERR_CNT(x, v)			(BIT_CLEAR_DATA_CRC_ERR_CNT(x) | BIT_DATA_CRC_ERR_CNT(v))

/* 2 REG_EEPROM_PIN_CTRL			(Offset 0x00C4) */

#define BIT_SYM_FORCE_SWR_PC_EN			BIT(9)
#define BIT_SYM_HCIAPC_EN				BIT(8)
#define BIT_B15V_EN					BIT(7)
#define BIT_EESK_IOSEL					BIT(6)
#define BIT_EESK_DATA_O				BIT(5)
#define BIT_EESK_DATA_I				BIT(4)
#define BIT_EECS_IOSEL					BIT(2)
#define BIT_EECS_DATA_O				BIT(1)
#define BIT_EECS_DATA_I				BIT(0)

#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT			0
#define BIT_MASK_SDIO_CMD_ERR_CONTENT			0xffffffffffL
#define BIT_SDIO_CMD_ERR_CONTENT(x)			(((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT)
#define BITS_SDIO_CMD_ERR_CONTENT			(BIT_MASK_SDIO_CMD_ERR_CONTENT << BIT_SHIFT_SDIO_CMD_ERR_CONTENT)
#define BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x)		((x) & (~BITS_SDIO_CMD_ERR_CONTENT))
#define BIT_GET_SDIO_CMD_ERR_CONTENT(x)		(((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & BIT_MASK_SDIO_CMD_ERR_CONTENT)
#define BIT_SET_SDIO_CMD_ERR_CONTENT(x, v)		(BIT_CLEAR_SDIO_CMD_ERR_CONTENT(x) | BIT_SDIO_CMD_ERR_CONTENT(v))

/* 2 REG_SDIO_CRC_ERR_IDX			(Offset 0x102500C9) */

#define BIT_D3_CRC_ERR					BIT(4)
#define BIT_D2_CRC_ERR					BIT(3)
#define BIT_D1_CRC_ERR					BIT(2)
#define BIT_D0_CRC_ERR					BIT(1)
#define BIT_CMD_CRC_ERR				BIT(0)

/* 2 REG_SDIO_DATA_CRC			(Offset 0x102500CA) */

#define BIT_SHIFT_SDIO_DATA_CRC			0
#define BIT_MASK_SDIO_DATA_CRC				0xffff
#define BIT_SDIO_DATA_CRC(x)				(((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC)
#define BITS_SDIO_DATA_CRC				(BIT_MASK_SDIO_DATA_CRC << BIT_SHIFT_SDIO_DATA_CRC)
#define BIT_CLEAR_SDIO_DATA_CRC(x)			((x) & (~BITS_SDIO_DATA_CRC))
#define BIT_GET_SDIO_DATA_CRC(x)			(((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC)
#define BIT_SET_SDIO_DATA_CRC(x, v)			(BIT_CLEAR_SDIO_DATA_CRC(x) | BIT_SDIO_DATA_CRC(v))

/* 2 REG_PMC_DBG_CTRL2			(Offset 0x00CC) */

#define BIT_SHIFT_EFUSE_BURN_GNT			24
#define BIT_MASK_EFUSE_BURN_GNT			0xff
#define BIT_EFUSE_BURN_GNT(x)				(((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT)
#define BITS_EFUSE_BURN_GNT				(BIT_MASK_EFUSE_BURN_GNT << BIT_SHIFT_EFUSE_BURN_GNT)
#define BIT_CLEAR_EFUSE_BURN_GNT(x)			((x) & (~BITS_EFUSE_BURN_GNT))
#define BIT_GET_EFUSE_BURN_GNT(x)			(((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT)
#define BIT_SET_EFUSE_BURN_GNT(x, v)			(BIT_CLEAR_EFUSE_BURN_GNT(x) | BIT_EFUSE_BURN_GNT(v))

#define BIT_SHIFT_EFUSE_SCAN_END			16
#define BIT_MASK_EFUSE_SCAN_END			0xff
#define BIT_EFUSE_SCAN_END(x)				(((x) & BIT_MASK_EFUSE_SCAN_END) << BIT_SHIFT_EFUSE_SCAN_END)
#define BITS_EFUSE_SCAN_END				(BIT_MASK_EFUSE_SCAN_END << BIT_SHIFT_EFUSE_SCAN_END)
#define BIT_CLEAR_EFUSE_SCAN_END(x)			((x) & (~BITS_EFUSE_SCAN_END))
#define BIT_GET_EFUSE_SCAN_END(x)			(((x) >> BIT_SHIFT_EFUSE_SCAN_END) & BIT_MASK_EFUSE_SCAN_END)
#define BIT_SET_EFUSE_SCAN_END(x, v)			(BIT_CLEAR_EFUSE_SCAN_END(x) | BIT_EFUSE_SCAN_END(v))

#define BIT_STOP_WL_PMC				BIT(9)
#define BIT_STOP_SYM_PMC				BIT(8)
#define BIT_EN_BT_WR					BIT(6)
#define BIT_REG_RST_WLPMC				BIT(5)
#define BIT_REG_RST_PD12N				BIT(4)
#define BIT_SYSON_DIS_WLREG_WRMSK			BIT(3)
#define BIT_SYSON_DIS_PMCREG_WRMSK			BIT(2)
#define BIT_TRANS_FIFO_UNDERFLOW			BIT(1)

#define BIT_SHIFT_SYSON_REG_ARB			0
#define BIT_MASK_SYSON_REG_ARB				0x3
#define BIT_SYSON_REG_ARB(x)				(((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB)
#define BITS_SYSON_REG_ARB				(BIT_MASK_SYSON_REG_ARB << BIT_SHIFT_SYSON_REG_ARB)
#define BIT_CLEAR_SYSON_REG_ARB(x)			((x) & (~BITS_SYSON_REG_ARB))
#define BIT_GET_SYSON_REG_ARB(x)			(((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB)
#define BIT_SET_SYSON_REG_ARB(x, v)			(BIT_CLEAR_SYSON_REG_ARB(x) | BIT_SYSON_REG_ARB(v))

#define BIT_TRANS_FIFO_OVERFLOW			BIT(0)

/* 2 REG_BIST_CTRL				(Offset 0x00D0) */

#define BIT_BIST_RPT_SEL_4				BIT(31)
#define BIT_BIST_DRF_FAIL				BIT(28)
#define BIT_BIST_DRF_DONE				BIT(27)
#define BIT_BIST_NORMAL_FAIL				BIT(26)
#define BIT_BIST_NORMAL_DONE				BIT(25)
#define BIT_BIST_START_PAUSE				BIT(24)

#define BIT_SHIFT_BIST_RPT_SEL_3_TO_0			20
#define BIT_MASK_BIST_RPT_SEL_3_TO_0			0xf
#define BIT_BIST_RPT_SEL_3_TO_0(x)			(((x) & BIT_MASK_BIST_RPT_SEL_3_TO_0) << BIT_SHIFT_BIST_RPT_SEL_3_TO_0)
#define BITS_BIST_RPT_SEL_3_TO_0			(BIT_MASK_BIST_RPT_SEL_3_TO_0 << BIT_SHIFT_BIST_RPT_SEL_3_TO_0)
#define BIT_CLEAR_BIST_RPT_SEL_3_TO_0(x)		((x) & (~BITS_BIST_RPT_SEL_3_TO_0))
#define BIT_GET_BIST_RPT_SEL_3_TO_0(x)			(((x) >> BIT_SHIFT_BIST_RPT_SEL_3_TO_0) & BIT_MASK_BIST_RPT_SEL_3_TO_0)
#define BIT_SET_BIST_RPT_SEL_3_TO_0(x, v)		(BIT_CLEAR_BIST_RPT_SEL_3_TO_0(x) | BIT_BIST_RPT_SEL_3_TO_0(v))

#define BIT_BIST_DIS_BT				BIT(17)
#define BIT_BIST_PHY_CLK_STOP				BIT(7)
#define BIT_BIST_DYN_READ_EN				BIT(6)
#define BIT_BIST_RESUME_PS				BIT(5)
#define BIT_BIST_RESUME				BIT(4)
#define BIT_BIST_DRF					BIT(3)
#define BIT_BIST_NORMAL				BIT(2)
#define BIT_BIST_RSTN					BIT(1)
#define BIT_BIST_CLK_EN				BIT(0)

/* 2 REG_BIST_RPT				(Offset 0x00D4) */

#define BIT_MBIST_SPUS_BT				BIT(14)
#define BIT_MBIST_FAIL_BT				BIT(13)
#define BIT_MBIST_DONE_BT				BIT(12)
#define BIT_MBIST_SPUS_WL				BIT(2)
#define BIT_MBIST_FAIL_WL				BIT(1)
#define BIT_MBIST_DONE_WL				BIT(0)

/* 2 REG_MEM_CTRL				(Offset 0x00D8) */

#define BIT_SHIFT_LP_LPS_LDO_STEP_DN			28
#define BIT_MASK_LP_LPS_LDO_STEP_DN			0xf
#define BIT_LP_LPS_LDO_STEP_DN(x)			(((x) & BIT_MASK_LP_LPS_LDO_STEP_DN) << BIT_SHIFT_LP_LPS_LDO_STEP_DN)
#define BITS_LP_LPS_LDO_STEP_DN			(BIT_MASK_LP_LPS_LDO_STEP_DN << BIT_SHIFT_LP_LPS_LDO_STEP_DN)
#define BIT_CLEAR_LP_LPS_LDO_STEP_DN(x)		((x) & (~BITS_LP_LPS_LDO_STEP_DN))
#define BIT_GET_LP_LPS_LDO_STEP_DN(x)			(((x) >> BIT_SHIFT_LP_LPS_LDO_STEP_DN) & BIT_MASK_LP_LPS_LDO_STEP_DN)
#define BIT_SET_LP_LPS_LDO_STEP_DN(x, v)		(BIT_CLEAR_LP_LPS_LDO_STEP_DN(x) | BIT_LP_LPS_LDO_STEP_DN(v))

#define BIT_SHIFT_LP_LPS_LDO_STEP_DN_AON		24
#define BIT_MASK_LP_LPS_LDO_STEP_DN_AON		0xf
#define BIT_LP_LPS_LDO_STEP_DN_AON(x)			(((x) & BIT_MASK_LP_LPS_LDO_STEP_DN_AON) << BIT_SHIFT_LP_LPS_LDO_STEP_DN_AON)
#define BITS_LP_LPS_LDO_STEP_DN_AON			(BIT_MASK_LP_LPS_LDO_STEP_DN_AON << BIT_SHIFT_LP_LPS_LDO_STEP_DN_AON)
#define BIT_CLEAR_LP_LPS_LDO_STEP_DN_AON(x)		((x) & (~BITS_LP_LPS_LDO_STEP_DN_AON))
#define BIT_GET_LP_LPS_LDO_STEP_DN_AON(x)		(((x) >> BIT_SHIFT_LP_LPS_LDO_STEP_DN_AON) & BIT_MASK_LP_LPS_LDO_STEP_DN_AON)
#define BIT_SET_LP_LPS_LDO_STEP_DN_AON(x, v)		(BIT_CLEAR_LP_LPS_LDO_STEP_DN_AON(x) | BIT_LP_LPS_LDO_STEP_DN_AON(v))

#define BIT_SHIFT_LP_LPS_LDO_STEP_DN_WL		20
#define BIT_MASK_LP_LPS_LDO_STEP_DN_WL			0xf
#define BIT_LP_LPS_LDO_STEP_DN_WL(x)			(((x) & BIT_MASK_LP_LPS_LDO_STEP_DN_WL) << BIT_SHIFT_LP_LPS_LDO_STEP_DN_WL)
#define BITS_LP_LPS_LDO_STEP_DN_WL			(BIT_MASK_LP_LPS_LDO_STEP_DN_WL << BIT_SHIFT_LP_LPS_LDO_STEP_DN_WL)
#define BIT_CLEAR_LP_LPS_LDO_STEP_DN_WL(x)		((x) & (~BITS_LP_LPS_LDO_STEP_DN_WL))
#define BIT_GET_LP_LPS_LDO_STEP_DN_WL(x)		(((x) >> BIT_SHIFT_LP_LPS_LDO_STEP_DN_WL) & BIT_MASK_LP_LPS_LDO_STEP_DN_WL)
#define BIT_SET_LP_LPS_LDO_STEP_DN_WL(x, v)		(BIT_CLEAR_LP_LPS_LDO_STEP_DN_WL(x) | BIT_LP_LPS_LDO_STEP_DN_WL(v))

#define BIT_SHIFT_LP_LDO_HCI_STEP_DOWN			16
#define BIT_MASK_LP_LDO_HCI_STEP_DOWN			0xf
#define BIT_LP_LDO_HCI_STEP_DOWN(x)			(((x) & BIT_MASK_LP_LDO_HCI_STEP_DOWN) << BIT_SHIFT_LP_LDO_HCI_STEP_DOWN)
#define BITS_LP_LDO_HCI_STEP_DOWN			(BIT_MASK_LP_LDO_HCI_STEP_DOWN << BIT_SHIFT_LP_LDO_HCI_STEP_DOWN)
#define BIT_CLEAR_LP_LDO_HCI_STEP_DOWN(x)		((x) & (~BITS_LP_LDO_HCI_STEP_DOWN))
#define BIT_GET_LP_LDO_HCI_STEP_DOWN(x)		(((x) >> BIT_SHIFT_LP_LDO_HCI_STEP_DOWN) & BIT_MASK_LP_LDO_HCI_STEP_DOWN)
#define BIT_SET_LP_LDO_HCI_STEP_DOWN(x, v)		(BIT_CLEAR_LP_LDO_HCI_STEP_DOWN(x) | BIT_LP_LDO_HCI_STEP_DOWN(v))

#define BIT_RTSEL_RF					BIT(15)
#define BIT_TURBO_RF					BIT(14)

#define BIT_SHIFT_TSEL_RF				12
#define BIT_MASK_TSEL_RF				0x3
#define BIT_TSEL_RF(x)					(((x) & BIT_MASK_TSEL_RF) << BIT_SHIFT_TSEL_RF)
#define BITS_TSEL_RF					(BIT_MASK_TSEL_RF << BIT_SHIFT_TSEL_RF)
#define BIT_CLEAR_TSEL_RF(x)				((x) & (~BITS_TSEL_RF))
#define BIT_GET_TSEL_RF(x)				(((x) >> BIT_SHIFT_TSEL_RF) & BIT_MASK_TSEL_RF)
#define BIT_SET_TSEL_RF(x, v)				(BIT_CLEAR_TSEL_RF(x) | BIT_TSEL_RF(v))

#define BIT_SHIFT_MEM_WTSEL				10
#define BIT_MASK_MEM_WTSEL				0x3
#define BIT_MEM_WTSEL(x)				(((x) & BIT_MASK_MEM_WTSEL) << BIT_SHIFT_MEM_WTSEL)
#define BITS_MEM_WTSEL					(BIT_MASK_MEM_WTSEL << BIT_SHIFT_MEM_WTSEL)
#define BIT_CLEAR_MEM_WTSEL(x)				((x) & (~BITS_MEM_WTSEL))
#define BIT_GET_MEM_WTSEL(x)				(((x) >> BIT_SHIFT_MEM_WTSEL) & BIT_MASK_MEM_WTSEL)
#define BIT_SET_MEM_WTSEL(x, v)			(BIT_CLEAR_MEM_WTSEL(x) | BIT_MEM_WTSEL(v))

#define BIT_SHIFT_MEM_RTSEL				8
#define BIT_MASK_MEM_RTSEL				0x3
#define BIT_MEM_RTSEL(x)				(((x) & BIT_MASK_MEM_RTSEL) << BIT_SHIFT_MEM_RTSEL)
#define BITS_MEM_RTSEL					(BIT_MASK_MEM_RTSEL << BIT_SHIFT_MEM_RTSEL)
#define BIT_CLEAR_MEM_RTSEL(x)				((x) & (~BITS_MEM_RTSEL))
#define BIT_GET_MEM_RTSEL(x)				(((x) >> BIT_SHIFT_MEM_RTSEL) & BIT_MASK_MEM_RTSEL)
#define BIT_SET_MEM_RTSEL(x, v)			(BIT_CLEAR_MEM_RTSEL(x) | BIT_MEM_RTSEL(v))

#define BIT_SHIFT_EMA_ARM				5
#define BIT_MASK_EMA_ARM				0x7
#define BIT_EMA_ARM(x)					(((x) & BIT_MASK_EMA_ARM) << BIT_SHIFT_EMA_ARM)
#define BITS_EMA_ARM					(BIT_MASK_EMA_ARM << BIT_SHIFT_EMA_ARM)
#define BIT_CLEAR_EMA_ARM(x)				((x) & (~BITS_EMA_ARM))
#define BIT_GET_EMA_ARM(x)				(((x) >> BIT_SHIFT_EMA_ARM) & BIT_MASK_EMA_ARM)
#define BIT_SET_EMA_ARM(x, v)				(BIT_CLEAR_EMA_ARM(x) | BIT_EMA_ARM(v))

#define BIT_HCI_MEMPM_EN				BIT(4)
#define BIT_KEN_ARM					BIT(2)
#define BIT_WL_PON_MEM_PD				BIT(1)
#define BIT_WL_MEM_PD					BIT(0)

/* 2 REG_SCAN_CTRL				(Offset 0x00DC) */

#define BIT_SHIFT_SCAN_CTRL				0
#define BIT_MASK_SCAN_CTRL				0xffffffffL
#define BIT_SCAN_CTRL(x)				(((x) & BIT_MASK_SCAN_CTRL) << BIT_SHIFT_SCAN_CTRL)
#define BITS_SCAN_CTRL					(BIT_MASK_SCAN_CTRL << BIT_SHIFT_SCAN_CTRL)
#define BIT_CLEAR_SCAN_CTRL(x)				((x) & (~BITS_SCAN_CTRL))
#define BIT_GET_SCAN_CTRL(x)				(((x) >> BIT_SHIFT_SCAN_CTRL) & BIT_MASK_SCAN_CTRL)
#define BIT_SET_SCAN_CTRL(x, v)			(BIT_CLEAR_SCAN_CTRL(x) | BIT_SCAN_CTRL(v))

/* 2 REG_USB_SIE_INTF			(Offset 0x00E0) */

#define BIT_RD_SEL					BIT(31)
#define BIT_USB_SIE_INTF_WE				BIT(30)
#define BIT_USB_SIE_INTF_BYIOREG			BIT(29)
#define BIT_USB_SIE_INTF_BYBUF				BIT(28)

#define BIT_SHIFT_USB_SIE_INTF_ADDR			16
#define BIT_MASK_USB_SIE_INTF_ADDR			0x1ff
#define BIT_USB_SIE_INTF_ADDR(x)			(((x) & BIT_MASK_USB_SIE_INTF_ADDR) << BIT_SHIFT_USB_SIE_INTF_ADDR)
#define BITS_USB_SIE_INTF_ADDR				(BIT_MASK_USB_SIE_INTF_ADDR << BIT_SHIFT_USB_SIE_INTF_ADDR)
#define BIT_CLEAR_USB_SIE_INTF_ADDR(x)			((x) & (~BITS_USB_SIE_INTF_ADDR))
#define BIT_GET_USB_SIE_INTF_ADDR(x)			(((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR) & BIT_MASK_USB_SIE_INTF_ADDR)
#define BIT_SET_USB_SIE_INTF_ADDR(x, v)		(BIT_CLEAR_USB_SIE_INTF_ADDR(x) | BIT_USB_SIE_INTF_ADDR(v))

#define BIT_SHIFT_USB_SIE_INTF_RD			8
#define BIT_MASK_USB_SIE_INTF_RD			0xff
#define BIT_USB_SIE_INTF_RD(x)				(((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD)
#define BITS_USB_SIE_INTF_RD				(BIT_MASK_USB_SIE_INTF_RD << BIT_SHIFT_USB_SIE_INTF_RD)
#define BIT_CLEAR_USB_SIE_INTF_RD(x)			((x) & (~BITS_USB_SIE_INTF_RD))
#define BIT_GET_USB_SIE_INTF_RD(x)			(((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD)
#define BIT_SET_USB_SIE_INTF_RD(x, v)			(BIT_CLEAR_USB_SIE_INTF_RD(x) | BIT_USB_SIE_INTF_RD(v))

#define BIT_SHIFT_USB_SIE_INTF_WD			0
#define BIT_MASK_USB_SIE_INTF_WD			0xff
#define BIT_USB_SIE_INTF_WD(x)				(((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD)
#define BITS_USB_SIE_INTF_WD				(BIT_MASK_USB_SIE_INTF_WD << BIT_SHIFT_USB_SIE_INTF_WD)
#define BIT_CLEAR_USB_SIE_INTF_WD(x)			((x) & (~BITS_USB_SIE_INTF_WD))
#define BIT_GET_USB_SIE_INTF_WD(x)			(((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD)
#define BIT_SET_USB_SIE_INTF_WD(x, v)			(BIT_CLEAR_USB_SIE_INTF_WD(x) | BIT_USB_SIE_INTF_WD(v))

/* 2 REG_MAC_CLK_PHS_CTRL			(Offset 0x00E4) */

#define BIT_CLK_GEN_MODE				BIT(17)
#define BIT_CLK_GEN_ONE_SHOT				BIT(16)

#define BIT_SHIFT_SEC_CLK_PHASE			8
#define BIT_MASK_SEC_CLK_PHASE				0xf
#define BIT_SEC_CLK_PHASE(x)				(((x) & BIT_MASK_SEC_CLK_PHASE) << BIT_SHIFT_SEC_CLK_PHASE)
#define BITS_SEC_CLK_PHASE				(BIT_MASK_SEC_CLK_PHASE << BIT_SHIFT_SEC_CLK_PHASE)
#define BIT_CLEAR_SEC_CLK_PHASE(x)			((x) & (~BITS_SEC_CLK_PHASE))
#define BIT_GET_SEC_CLK_PHASE(x)			(((x) >> BIT_SHIFT_SEC_CLK_PHASE) & BIT_MASK_SEC_CLK_PHASE)
#define BIT_SET_SEC_CLK_PHASE(x, v)			(BIT_CLEAR_SEC_CLK_PHASE(x) | BIT_SEC_CLK_PHASE(v))

#define BIT_SHIFT_MAC_CLK_PHASE			0
#define BIT_MASK_MAC_CLK_PHASE				0x1f
#define BIT_MAC_CLK_PHASE(x)				(((x) & BIT_MASK_MAC_CLK_PHASE) << BIT_SHIFT_MAC_CLK_PHASE)
#define BITS_MAC_CLK_PHASE				(BIT_MASK_MAC_CLK_PHASE << BIT_SHIFT_MAC_CLK_PHASE)
#define BIT_CLEAR_MAC_CLK_PHASE(x)			((x) & (~BITS_MAC_CLK_PHASE))
#define BIT_GET_MAC_CLK_PHASE(x)			(((x) >> BIT_SHIFT_MAC_CLK_PHASE) & BIT_MASK_MAC_CLK_PHASE)
#define BIT_SET_MAC_CLK_PHASE(x, v)			(BIT_CLEAR_MAC_CLK_PHASE(x) | BIT_MAC_CLK_PHASE(v))

/* 2 REG_XTAL_AAC_CFG			(Offset 0x00EC) */

#define BIT_EN_XTAL_AAC				BIT(31)
#define BIT_AAC_EN_XTAL_HPM				BIT(30)
#define BIT_XTAL_AAC_READY				BIT(29)
#define BIT_AAC_TIMEOUT_ERR				BIT(28)
#define BIT_RO_XTAL_AAC_READY				BIT(7)

#define BIT_SHIFT_RO_XTAL_AAC_PK_SEL			5
#define BIT_MASK_RO_XTAL_AAC_PK_SEL			0x3
#define BIT_RO_XTAL_AAC_PK_SEL(x)			(((x) & BIT_MASK_RO_XTAL_AAC_PK_SEL) << BIT_SHIFT_RO_XTAL_AAC_PK_SEL)
#define BITS_RO_XTAL_AAC_PK_SEL			(BIT_MASK_RO_XTAL_AAC_PK_SEL << BIT_SHIFT_RO_XTAL_AAC_PK_SEL)
#define BIT_CLEAR_RO_XTAL_AAC_PK_SEL(x)		((x) & (~BITS_RO_XTAL_AAC_PK_SEL))
#define BIT_GET_RO_XTAL_AAC_PK_SEL(x)			(((x) >> BIT_SHIFT_RO_XTAL_AAC_PK_SEL) & BIT_MASK_RO_XTAL_AAC_PK_SEL)
#define BIT_SET_RO_XTAL_AAC_PK_SEL(x, v)		(BIT_CLEAR_RO_XTAL_AAC_PK_SEL(x) | BIT_RO_XTAL_AAC_PK_SEL(v))

#define BIT_SHIFT_RO_XTAL_AAC_GM_OUT			0
#define BIT_MASK_RO_XTAL_AAC_GM_OUT			0x1f
#define BIT_RO_XTAL_AAC_GM_OUT(x)			(((x) & BIT_MASK_RO_XTAL_AAC_GM_OUT) << BIT_SHIFT_RO_XTAL_AAC_GM_OUT)
#define BITS_RO_XTAL_AAC_GM_OUT			(BIT_MASK_RO_XTAL_AAC_GM_OUT << BIT_SHIFT_RO_XTAL_AAC_GM_OUT)
#define BIT_CLEAR_RO_XTAL_AAC_GM_OUT(x)		((x) & (~BITS_RO_XTAL_AAC_GM_OUT))
#define BIT_GET_RO_XTAL_AAC_GM_OUT(x)			(((x) >> BIT_SHIFT_RO_XTAL_AAC_GM_OUT) & BIT_MASK_RO_XTAL_AAC_GM_OUT)
#define BIT_SET_RO_XTAL_AAC_GM_OUT(x, v)		(BIT_CLEAR_RO_XTAL_AAC_GM_OUT(x) | BIT_RO_XTAL_AAC_GM_OUT(v))

/* 2 REG_SYS_CFG1				(Offset 0x00F0) */

#define BIT_SHIFT_TRP_ICFG				28
#define BIT_MASK_TRP_ICFG				0xf
#define BIT_TRP_ICFG(x)				(((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG)
#define BITS_TRP_ICFG					(BIT_MASK_TRP_ICFG << BIT_SHIFT_TRP_ICFG)
#define BIT_CLEAR_TRP_ICFG(x)				((x) & (~BITS_TRP_ICFG))
#define BIT_GET_TRP_ICFG(x)				(((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG)
#define BIT_SET_TRP_ICFG(x, v)				(BIT_CLEAR_TRP_ICFG(x) | BIT_TRP_ICFG(v))

#define BIT_RF_TYPE_ID					BIT(27)
#define BIT_BD_HCI_SEL					BIT(26)
#define BIT_BD_PKG_SEL					BIT(25)
#define BIT_SPSLDO_SEL					BIT(24)
#define BIT_RTL_ID					BIT(23)
#define BIT_PAD_HWPD_IDN				BIT(22)
#define BIT_UART_SEL					BIT(21)
#define BIT_TESTMODE					BIT(20)

#define BIT_SHIFT_VENDOR_ID				16
#define BIT_MASK_VENDOR_ID				0xf
#define BIT_VENDOR_ID(x)				(((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)
#define BITS_VENDOR_ID					(BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID)
#define BIT_CLEAR_VENDOR_ID(x)				((x) & (~BITS_VENDOR_ID))
#define BIT_GET_VENDOR_ID(x)				(((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)
#define BIT_SET_VENDOR_ID(x, v)			(BIT_CLEAR_VENDOR_ID(x) | BIT_VENDOR_ID(v))

#define BIT_SHIFT_CHIP_VER				12
#define BIT_MASK_CHIP_VER				0xf
#define BIT_CHIP_VER(x)				(((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)
#define BITS_CHIP_VER					(BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER)
#define BIT_CLEAR_CHIP_VER(x)				((x) & (~BITS_CHIP_VER))
#define BIT_GET_CHIP_VER(x)				(((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)
#define BIT_SET_CHIP_VER(x, v)				(BIT_CLEAR_CHIP_VER(x) | BIT_CHIP_VER(v))

#define BIT_TEST_MODE_SEL				BIT(11)
#define BIT_BD_MAC1					BIT(10)
#define BIT_XTAL_CLK_CHANGE_OK				BIT(9)
#define BIT_SIC_IDLE					BIT(8)
#define BIT_SW_OFFLOAD_EN				BIT(7)
#define BIT_OCP_SHUTDN					BIT(6)
#define BIT_V15_VLD					BIT(5)
#define BIT_PCIRSTB					BIT(4)
#define BIT_PCLK_VLD					BIT(3)
#define BIT_UCLK_VLD					BIT(2)
#define BIT_ACLK_VLD					BIT(1)
#define BIT_XCLK_VLD					BIT(0)

/* 2 REG_SYS_STATUS1				(Offset 0x00F4) */

#define BIT_SHIFT_RF_RL_ID				28
#define BIT_MASK_RF_RL_ID				0xf
#define BIT_RF_RL_ID(x)				(((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID)
#define BITS_RF_RL_ID					(BIT_MASK_RF_RL_ID << BIT_SHIFT_RF_RL_ID)
#define BIT_CLEAR_RF_RL_ID(x)				((x) & (~BITS_RF_RL_ID))
#define BIT_GET_RF_RL_ID(x)				(((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID)
#define BIT_SET_RF_RL_ID(x, v)				(BIT_CLEAR_RF_RL_ID(x) | BIT_RF_RL_ID(v))

#define BIT_BT_LPSEN					BIT(27)
#define BIT_WL_LPSEN					BIT(26)

#define BIT_SHIFT_SW_ICFG				20
#define BIT_MASK_SW_ICFG				0xf
#define BIT_SW_ICFG(x)					(((x) & BIT_MASK_SW_ICFG) << BIT_SHIFT_SW_ICFG)
#define BITS_SW_ICFG					(BIT_MASK_SW_ICFG << BIT_SHIFT_SW_ICFG)
#define BIT_CLEAR_SW_ICFG(x)				((x) & (~BITS_SW_ICFG))
#define BIT_GET_SW_ICFG(x)				(((x) >> BIT_SHIFT_SW_ICFG) & BIT_MASK_SW_ICFG)
#define BIT_SET_SW_ICFG(x, v)				(BIT_CLEAR_SW_ICFG(x) | BIT_SW_ICFG(v))

#define BIT_TEST_MOD_EN				BIT(19)

#define BIT_SHIFT_SEL_0XC0				16
#define BIT_MASK_SEL_0XC0				0x3
#define BIT_SEL_0XC0(x)				(((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0)
#define BITS_SEL_0XC0					(BIT_MASK_SEL_0XC0 << BIT_SHIFT_SEL_0XC0)
#define BIT_CLEAR_SEL_0XC0(x)				((x) & (~BITS_SEL_0XC0))
#define BIT_GET_SEL_0XC0(x)				(((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0)
#define BIT_SET_SEL_0XC0(x, v)				(BIT_CLEAR_SEL_0XC0(x) | BIT_SEL_0XC0(v))

#define BIT_USB_OPERATION_MODE				BIT(10)
#define BIT_BT_PDN					BIT(9)
#define BIT_AUTO_WLPON					BIT(8)
#define BIT_WL_MODE					BIT(7)
#define BIT_PKG_SEL_HCI				BIT(6)

#define BIT_SHIFT_HCI_SEL				4
#define BIT_MASK_HCI_SEL				0x3
#define BIT_HCI_SEL(x)					(((x) & BIT_MASK_HCI_SEL) << BIT_SHIFT_HCI_SEL)
#define BITS_HCI_SEL					(BIT_MASK_HCI_SEL << BIT_SHIFT_HCI_SEL)
#define BIT_CLEAR_HCI_SEL(x)				((x) & (~BITS_HCI_SEL))
#define BIT_GET_HCI_SEL(x)				(((x) >> BIT_SHIFT_HCI_SEL) & BIT_MASK_HCI_SEL)
#define BIT_SET_HCI_SEL(x, v)				(BIT_CLEAR_HCI_SEL(x) | BIT_HCI_SEL(v))

#define BIT_SHIFT_PAD_HCI_SEL				2
#define BIT_MASK_PAD_HCI_SEL				0x3
#define BIT_PAD_HCI_SEL(x)				(((x) & BIT_MASK_PAD_HCI_SEL) << BIT_SHIFT_PAD_HCI_SEL)
#define BITS_PAD_HCI_SEL				(BIT_MASK_PAD_HCI_SEL << BIT_SHIFT_PAD_HCI_SEL)
#define BIT_CLEAR_PAD_HCI_SEL(x)			((x) & (~BITS_PAD_HCI_SEL))
#define BIT_GET_PAD_HCI_SEL(x)				(((x) >> BIT_SHIFT_PAD_HCI_SEL) & BIT_MASK_PAD_HCI_SEL)
#define BIT_SET_PAD_HCI_SEL(x, v)			(BIT_CLEAR_PAD_HCI_SEL(x) | BIT_PAD_HCI_SEL(v))

#define BIT_SHIFT_EFS_HCI_SEL				0
#define BIT_MASK_EFS_HCI_SEL				0x3
#define BIT_EFS_HCI_SEL(x)				(((x) & BIT_MASK_EFS_HCI_SEL) << BIT_SHIFT_EFS_HCI_SEL)
#define BITS_EFS_HCI_SEL				(BIT_MASK_EFS_HCI_SEL << BIT_SHIFT_EFS_HCI_SEL)
#define BIT_CLEAR_EFS_HCI_SEL(x)			((x) & (~BITS_EFS_HCI_SEL))
#define BIT_GET_EFS_HCI_SEL(x)				(((x) >> BIT_SHIFT_EFS_HCI_SEL) & BIT_MASK_EFS_HCI_SEL)
#define BIT_SET_EFS_HCI_SEL(x, v)			(BIT_CLEAR_EFS_HCI_SEL(x) | BIT_EFS_HCI_SEL(v))

/* 2 REG_SYS_STATUS2				(Offset 0x00F8) */

#define BIT_XTAL_DETECT_EN				BIT(26)
#define BIT_XTAL_DETECT_RDY				BIT(25)
#define BIT_32K_OK					BIT(24)
#define BIT_SIO_ALDN					BIT(19)
#define BIT_USB_ALDN					BIT(18)
#define BIT_PCI_ALDN					BIT(17)
#define BIT_SYS_ALDN					BIT(16)

#define BIT_SHIFT_EPVID1				8
#define BIT_MASK_EPVID1				0xff
#define BIT_EPVID1(x)					(((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1)
#define BITS_EPVID1					(BIT_MASK_EPVID1 << BIT_SHIFT_EPVID1)
#define BIT_CLEAR_EPVID1(x)				((x) & (~BITS_EPVID1))
#define BIT_GET_EPVID1(x)				(((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1)
#define BIT_SET_EPVID1(x, v)				(BIT_CLEAR_EPVID1(x) | BIT_EPVID1(v))

#define BIT_SHIFT_EPVID0				0
#define BIT_MASK_EPVID0				0xff
#define BIT_EPVID0(x)					(((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0)
#define BITS_EPVID0					(BIT_MASK_EPVID0 << BIT_SHIFT_EPVID0)
#define BIT_CLEAR_EPVID0(x)				((x) & (~BITS_EPVID0))
#define BIT_GET_EPVID0(x)				(((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0)
#define BIT_SET_EPVID0(x, v)				(BIT_CLEAR_EPVID0(x) | BIT_EPVID0(v))

/* 2 REG_SYS_CFG2				(Offset 0x00FC) */

#define BIT_SHIFT_HW_ID				0
#define BIT_MASK_HW_ID					0xff
#define BIT_HW_ID(x)					(((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID)
#define BITS_HW_ID					(BIT_MASK_HW_ID << BIT_SHIFT_HW_ID)
#define BIT_CLEAR_HW_ID(x)				((x) & (~BITS_HW_ID))
#define BIT_GET_HW_ID(x)				(((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID)
#define BIT_SET_HW_ID(x, v)				(BIT_CLEAR_HW_ID(x) | BIT_HW_ID(v))

/* 2 REG_CR					(Offset 0x0100) */

#define BIT_DMACLBK					BIT(28)
#define BIT_NO_TBUF					BIT(27)
#define BIT_DMALBK					BIT(26)
#define BIT_NO_TXPHY					BIT(25)
#define BIT_DIGLBK					BIT(24)

#define BIT_SHIFT_NETYPE1				18
#define BIT_MASK_NETYPE1				0x3
#define BIT_NETYPE1(x)					(((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1)
#define BITS_NETYPE1					(BIT_MASK_NETYPE1 << BIT_SHIFT_NETYPE1)
#define BIT_CLEAR_NETYPE1(x)				((x) & (~BITS_NETYPE1))
#define BIT_GET_NETYPE1(x)				(((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1)
#define BIT_SET_NETYPE1(x, v)				(BIT_CLEAR_NETYPE1(x) | BIT_NETYPE1(v))

#define BIT_SHIFT_NETYPE0				16
#define BIT_MASK_NETYPE0				0x3
#define BIT_NETYPE0(x)					(((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0)
#define BITS_NETYPE0					(BIT_MASK_NETYPE0 << BIT_SHIFT_NETYPE0)
#define BIT_CLEAR_NETYPE0(x)				((x) & (~BITS_NETYPE0))
#define BIT_GET_NETYPE0(x)				(((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0)
#define BIT_SET_NETYPE0(x, v)				(BIT_CLEAR_NETYPE0(x) | BIT_NETYPE0(v))

#define BIT_I2C_MAILBOX_EN				BIT(12)
#define BIT_CAL32TM_EN					BIT(10)
#define BIT_MAC_SEC_EN					BIT(9)
#define BIT_ENSWBCN					BIT(8)
#define BIT_MACRXEN					BIT(7)
#define BIT_MACTXEN					BIT(6)
#define BIT_SCHEDULE_EN				BIT(5)
#define BIT_PROTOCOL_EN				BIT(4)
#define BIT_RXDMA_EN					BIT(3)
#define BIT_TXDMA_EN					BIT(2)
#define BIT_HCI_RXDMA_EN				BIT(1)
#define BIT_HCI_TXDMA_EN				BIT(0)

/* 2 REG_PG_SIZE				(Offset 0x0104) */

#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL			16
#define BIT_MASK_PKT_BUFF_ACCESS_CTRL			0xff
#define BIT_PKT_BUFF_ACCESS_CTRL(x)			(((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL)
#define BITS_PKT_BUFF_ACCESS_CTRL			(BIT_MASK_PKT_BUFF_ACCESS_CTRL << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL)
#define BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x)		((x) & (~BITS_PKT_BUFF_ACCESS_CTRL))
#define BIT_GET_PKT_BUFF_ACCESS_CTRL(x)		(((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & BIT_MASK_PKT_BUFF_ACCESS_CTRL)
#define BIT_SET_PKT_BUFF_ACCESS_CTRL(x, v)		(BIT_CLEAR_PKT_BUFF_ACCESS_CTRL(x) | BIT_PKT_BUFF_ACCESS_CTRL(v))

#define BIT_IRAM_DIS					BIT(8)

#define BIT_SHIFT_TXPKT_PGSZ				4
#define BIT_MASK_TXPKT_PGSZ				0xf
#define BIT_TXPKT_PGSZ(x)				(((x) & BIT_MASK_TXPKT_PGSZ) << BIT_SHIFT_TXPKT_PGSZ)
#define BITS_TXPKT_PGSZ				(BIT_MASK_TXPKT_PGSZ << BIT_SHIFT_TXPKT_PGSZ)
#define BIT_CLEAR_TXPKT_PGSZ(x)			((x) & (~BITS_TXPKT_PGSZ))
#define BIT_GET_TXPKT_PGSZ(x)				(((x) >> BIT_SHIFT_TXPKT_PGSZ) & BIT_MASK_TXPKT_PGSZ)
#define BIT_SET_TXPKT_PGSZ(x, v)			(BIT_CLEAR_TXPKT_PGSZ(x) | BIT_TXPKT_PGSZ(v))

#define BIT_SHIFT_RXPKT_PGSZ				0
#define BIT_MASK_RXPKT_PGSZ				0xf
#define BIT_RXPKT_PGSZ(x)				(((x) & BIT_MASK_RXPKT_PGSZ) << BIT_SHIFT_RXPKT_PGSZ)
#define BITS_RXPKT_PGSZ				(BIT_MASK_RXPKT_PGSZ << BIT_SHIFT_RXPKT_PGSZ)
#define BIT_CLEAR_RXPKT_PGSZ(x)			((x) & (~BITS_RXPKT_PGSZ))
#define BIT_GET_RXPKT_PGSZ(x)				(((x) >> BIT_SHIFT_RXPKT_PGSZ) & BIT_MASK_RXPKT_PGSZ)
#define BIT_SET_RXPKT_PGSZ(x, v)			(BIT_CLEAR_RXPKT_PGSZ(x) | BIT_RXPKT_PGSZ(v))

/* 2 REG_TSF_CLK_STATE			(Offset 0x0108) */

#define BIT_CLK_TSF_IS32K				BIT(15)

/* 2 REG_TXDMA_PQ_MAP			(Offset 0x010C) */

#define BIT_SHIFT_TXDMA_CMQ_MAP			16
#define BIT_MASK_TXDMA_CMQ_MAP				0x3
#define BIT_TXDMA_CMQ_MAP(x)				(((x) & BIT_MASK_TXDMA_CMQ_MAP) << BIT_SHIFT_TXDMA_CMQ_MAP)
#define BITS_TXDMA_CMQ_MAP				(BIT_MASK_TXDMA_CMQ_MAP << BIT_SHIFT_TXDMA_CMQ_MAP)
#define BIT_CLEAR_TXDMA_CMQ_MAP(x)			((x) & (~BITS_TXDMA_CMQ_MAP))
#define BIT_GET_TXDMA_CMQ_MAP(x)			(((x) >> BIT_SHIFT_TXDMA_CMQ_MAP) & BIT_MASK_TXDMA_CMQ_MAP)
#define BIT_SET_TXDMA_CMQ_MAP(x, v)			(BIT_CLEAR_TXDMA_CMQ_MAP(x) | BIT_TXDMA_CMQ_MAP(v))

#define BIT_SHIFT_TXDMA_HIQ_MAP			14
#define BIT_MASK_TXDMA_HIQ_MAP				0x3
#define BIT_TXDMA_HIQ_MAP(x)				(((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)
#define BITS_TXDMA_HIQ_MAP				(BIT_MASK_TXDMA_HIQ_MAP << BIT_SHIFT_TXDMA_HIQ_MAP)
#define BIT_CLEAR_TXDMA_HIQ_MAP(x)			((x) & (~BITS_TXDMA_HIQ_MAP))
#define BIT_GET_TXDMA_HIQ_MAP(x)			(((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP)
#define BIT_SET_TXDMA_HIQ_MAP(x, v)			(BIT_CLEAR_TXDMA_HIQ_MAP(x) | BIT_TXDMA_HIQ_MAP(v))

#define BIT_SHIFT_TXDMA_MGQ_MAP			12
#define BIT_MASK_TXDMA_MGQ_MAP				0x3
#define BIT_TXDMA_MGQ_MAP(x)				(((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)
#define BITS_TXDMA_MGQ_MAP				(BIT_MASK_TXDMA_MGQ_MAP << BIT_SHIFT_TXDMA_MGQ_MAP)
#define BIT_CLEAR_TXDMA_MGQ_MAP(x)			((x) & (~BITS_TXDMA_MGQ_MAP))
#define BIT_GET_TXDMA_MGQ_MAP(x)			(((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP)
#define BIT_SET_TXDMA_MGQ_MAP(x, v)			(BIT_CLEAR_TXDMA_MGQ_MAP(x) | BIT_TXDMA_MGQ_MAP(v))

#define BIT_SHIFT_TXDMA_BKQ_MAP			10
#define BIT_MASK_TXDMA_BKQ_MAP				0x3
#define BIT_TXDMA_BKQ_MAP(x)				(((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)
#define BITS_TXDMA_BKQ_MAP				(BIT_MASK_TXDMA_BKQ_MAP << BIT_SHIFT_TXDMA_BKQ_MAP)
#define BIT_CLEAR_TXDMA_BKQ_MAP(x)			((x) & (~BITS_TXDMA_BKQ_MAP))
#define BIT_GET_TXDMA_BKQ_MAP(x)			(((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP)
#define BIT_SET_TXDMA_BKQ_MAP(x, v)			(BIT_CLEAR_TXDMA_BKQ_MAP(x) | BIT_TXDMA_BKQ_MAP(v))

#define BIT_SHIFT_TXDMA_BEQ_MAP			8
#define BIT_MASK_TXDMA_BEQ_MAP				0x3
#define BIT_TXDMA_BEQ_MAP(x)				(((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)
#define BITS_TXDMA_BEQ_MAP				(BIT_MASK_TXDMA_BEQ_MAP << BIT_SHIFT_TXDMA_BEQ_MAP)
#define BIT_CLEAR_TXDMA_BEQ_MAP(x)			((x) & (~BITS_TXDMA_BEQ_MAP))
#define BIT_GET_TXDMA_BEQ_MAP(x)			(((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP)
#define BIT_SET_TXDMA_BEQ_MAP(x, v)			(BIT_CLEAR_TXDMA_BEQ_MAP(x) | BIT_TXDMA_BEQ_MAP(v))

#define BIT_SHIFT_TXDMA_VIQ_MAP			6
#define BIT_MASK_TXDMA_VIQ_MAP				0x3
#define BIT_TXDMA_VIQ_MAP(x)				(((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)
#define BITS_TXDMA_VIQ_MAP				(BIT_MASK_TXDMA_VIQ_MAP << BIT_SHIFT_TXDMA_VIQ_MAP)
#define BIT_CLEAR_TXDMA_VIQ_MAP(x)			((x) & (~BITS_TXDMA_VIQ_MAP))
#define BIT_GET_TXDMA_VIQ_MAP(x)			(((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP)
#define BIT_SET_TXDMA_VIQ_MAP(x, v)			(BIT_CLEAR_TXDMA_VIQ_MAP(x) | BIT_TXDMA_VIQ_MAP(v))

#define BIT_SHIFT_TXDMA_VOQ_MAP			4
#define BIT_MASK_TXDMA_VOQ_MAP				0x3
#define BIT_TXDMA_VOQ_MAP(x)				(((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)
#define BITS_TXDMA_VOQ_MAP				(BIT_MASK_TXDMA_VOQ_MAP << BIT_SHIFT_TXDMA_VOQ_MAP)
#define BIT_CLEAR_TXDMA_VOQ_MAP(x)			((x) & (~BITS_TXDMA_VOQ_MAP))
#define BIT_GET_TXDMA_VOQ_MAP(x)			(((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP)
#define BIT_SET_TXDMA_VOQ_MAP(x, v)			(BIT_CLEAR_TXDMA_VOQ_MAP(x) | BIT_TXDMA_VOQ_MAP(v))

#define BIT_RXDMA_AGG_EN				BIT(2)
#define BIT_ENSHFT					BIT(1)
#define BIT_RXDMA_BW_EN				BIT(0)

/* 2 REG_TRXFF_BNDY				(Offset 0x0114) */

#define BIT_SHIFT_RXPKT0ENDADDR			16
#define BIT_MASK_RXPKT0ENDADDR				0xffff
#define BIT_RXPKT0ENDADDR(x)				(((x) & BIT_MASK_RXPKT0ENDADDR) << BIT_SHIFT_RXPKT0ENDADDR)
#define BITS_RXPKT0ENDADDR				(BIT_MASK_RXPKT0ENDADDR << BIT_SHIFT_RXPKT0ENDADDR)
#define BIT_CLEAR_RXPKT0ENDADDR(x)			((x) & (~BITS_RXPKT0ENDADDR))
#define BIT_GET_RXPKT0ENDADDR(x)			(((x) >> BIT_SHIFT_RXPKT0ENDADDR) & BIT_MASK_RXPKT0ENDADDR)
#define BIT_SET_RXPKT0ENDADDR(x, v)			(BIT_CLEAR_RXPKT0ENDADDR(x) | BIT_RXPKT0ENDADDR(v))

#define BIT_SHIFT_RXFFOVFL_RSV				8
#define BIT_MASK_RXFFOVFL_RSV				0xf
#define BIT_RXFFOVFL_RSV(x)				(((x) & BIT_MASK_RXFFOVFL_RSV) << BIT_SHIFT_RXFFOVFL_RSV)
#define BITS_RXFFOVFL_RSV				(BIT_MASK_RXFFOVFL_RSV << BIT_SHIFT_RXFFOVFL_RSV)
#define BIT_CLEAR_RXFFOVFL_RSV(x)			((x) & (~BITS_RXFFOVFL_RSV))
#define BIT_GET_RXFFOVFL_RSV(x)			(((x) >> BIT_SHIFT_RXFFOVFL_RSV) & BIT_MASK_RXFFOVFL_RSV)
#define BIT_SET_RXFFOVFL_RSV(x, v)			(BIT_CLEAR_RXFFOVFL_RSV(x) | BIT_RXFFOVFL_RSV(v))

#define BIT_SHIFT_TXPKT_PGBNDY				0
#define BIT_MASK_TXPKT_PGBNDY				0xff
#define BIT_TXPKT_PGBNDY(x)				(((x) & BIT_MASK_TXPKT_PGBNDY) << BIT_SHIFT_TXPKT_PGBNDY)
#define BITS_TXPKT_PGBNDY				(BIT_MASK_TXPKT_PGBNDY << BIT_SHIFT_TXPKT_PGBNDY)
#define BIT_CLEAR_TXPKT_PGBNDY(x)			((x) & (~BITS_TXPKT_PGBNDY))
#define BIT_GET_TXPKT_PGBNDY(x)			(((x) >> BIT_SHIFT_TXPKT_PGBNDY) & BIT_MASK_TXPKT_PGBNDY)
#define BIT_SET_TXPKT_PGBNDY(x, v)			(BIT_CLEAR_TXPKT_PGBNDY(x) | BIT_TXPKT_PGBNDY(v))

/* 2 REG_PTA_I2C_MBOX			(Offset 0x0118) */

#define BIT_SHIFT_I2C_M_STATUS				8
#define BIT_MASK_I2C_M_STATUS				0xf
#define BIT_I2C_M_STATUS(x)				(((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS)
#define BITS_I2C_M_STATUS				(BIT_MASK_I2C_M_STATUS << BIT_SHIFT_I2C_M_STATUS)
#define BIT_CLEAR_I2C_M_STATUS(x)			((x) & (~BITS_I2C_M_STATUS))
#define BIT_GET_I2C_M_STATUS(x)			(((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS)
#define BIT_SET_I2C_M_STATUS(x, v)			(BIT_CLEAR_I2C_M_STATUS(x) | BIT_I2C_M_STATUS(v))

#define BIT_SHIFT_I2C_M_BUS_GNT_FW			4
#define BIT_MASK_I2C_M_BUS_GNT_FW			0x7
#define BIT_I2C_M_BUS_GNT_FW(x)			(((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW)
#define BITS_I2C_M_BUS_GNT_FW				(BIT_MASK_I2C_M_BUS_GNT_FW << BIT_SHIFT_I2C_M_BUS_GNT_FW)
#define BIT_CLEAR_I2C_M_BUS_GNT_FW(x)			((x) & (~BITS_I2C_M_BUS_GNT_FW))
#define BIT_GET_I2C_M_BUS_GNT_FW(x)			(((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW)
#define BIT_SET_I2C_M_BUS_GNT_FW(x, v)			(BIT_CLEAR_I2C_M_BUS_GNT_FW(x) | BIT_I2C_M_BUS_GNT_FW(v))

#define BIT_I2C_GNT_FW					BIT(3)

#define BIT_SHIFT_I2C_M_SPEED				1
#define BIT_MASK_I2C_M_SPEED				0x3
#define BIT_I2C_M_SPEED(x)				(((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED)
#define BITS_I2C_M_SPEED				(BIT_MASK_I2C_M_SPEED << BIT_SHIFT_I2C_M_SPEED)
#define BIT_CLEAR_I2C_M_SPEED(x)			((x) & (~BITS_I2C_M_SPEED))
#define BIT_GET_I2C_M_SPEED(x)				(((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED)
#define BIT_SET_I2C_M_SPEED(x, v)			(BIT_CLEAR_I2C_M_SPEED(x) | BIT_I2C_M_SPEED(v))

#define BIT_I2C_M_UNLOCK				BIT(0)

/* 2 REG_RXFF_PTR				(Offset 0x011C) */

#define BIT_SHIFT_RXFF0_RDPTR				16
#define BIT_MASK_RXFF0_RDPTR				0xffff
#define BIT_RXFF0_RDPTR(x)				(((x) & BIT_MASK_RXFF0_RDPTR) << BIT_SHIFT_RXFF0_RDPTR)
#define BITS_RXFF0_RDPTR				(BIT_MASK_RXFF0_RDPTR << BIT_SHIFT_RXFF0_RDPTR)
#define BIT_CLEAR_RXFF0_RDPTR(x)			((x) & (~BITS_RXFF0_RDPTR))
#define BIT_GET_RXFF0_RDPTR(x)				(((x) >> BIT_SHIFT_RXFF0_RDPTR) & BIT_MASK_RXFF0_RDPTR)
#define BIT_SET_RXFF0_RDPTR(x, v)			(BIT_CLEAR_RXFF0_RDPTR(x) | BIT_RXFF0_RDPTR(v))

#define BIT_SHIFT_RXFF0_WTPTR				0
#define BIT_MASK_RXFF0_WTPTR				0xffff
#define BIT_RXFF0_WTPTR(x)				(((x) & BIT_MASK_RXFF0_WTPTR) << BIT_SHIFT_RXFF0_WTPTR)
#define BITS_RXFF0_WTPTR				(BIT_MASK_RXFF0_WTPTR << BIT_SHIFT_RXFF0_WTPTR)
#define BIT_CLEAR_RXFF0_WTPTR(x)			((x) & (~BITS_RXFF0_WTPTR))
#define BIT_GET_RXFF0_WTPTR(x)				(((x) >> BIT_SHIFT_RXFF0_WTPTR) & BIT_MASK_RXFF0_WTPTR)
#define BIT_SET_RXFF0_WTPTR(x, v)			(BIT_CLEAR_RXFF0_WTPTR(x) | BIT_RXFF0_WTPTR(v))

/* 2 REG_FE1IMR				(Offset 0x0120) */

#define BIT_NOT_BEACON_INT_EN				BIT(31)
#define BIT_FWFF_FULL_INT_EN				BIT(30)
#define BIT_BB_STOP_RX_INT_EN				BIT(29)
#define BIT_FS_RXDMA2_DONE_INT_EN			BIT(28)
#define BIT_RXPCLP_CHKOK_INT_EN			BIT(27)
#define BIT_FS_RXDONE1_INT_EN				BIT(26)
#define BIT_FS_RX_BCN_P4_INT_EN			BIT(25)
#define BIT_FS_RX_BCN_P3_INT_EN			BIT(24)
#define BIT_FS_RX_BCN_P2_INT_EN			BIT(23)
#define BIT_FS_RX_BCN_P1_INT_EN			BIT(22)
#define BIT_FS_RX_BCN_P0_INT_EN			BIT(21)
#define BIT_FS_RX_UMD0_INT_EN				BIT(20)
#define BIT_FS_RX_UMD1_INT_EN				BIT(19)
#define BIT_FS_RX_BMD0_INT_EN				BIT(18)
#define BIT_FS_RX_BMD1_INT_EN				BIT(17)
#define BIT_FS_RXDONE0_INT_EN				BIT(16)
#define BIT_FS_WWLAN_INT_EN				BIT(15)
#define BIT_FS_SOUND_DONE_INT_EN			BIT(14)
#define BIT_FS_LP_STBY_INT_EN				BIT(13)
#define BIT_FS_TRL_MTR_INT_EN				BIT(12)
#define BIT_FS_BF1_PRETO_INT_EN			BIT(11)
#define BIT_FS_BF0_PRETO_INT_EN			BIT(10)
#define BIT_FS_PTCL_RELEASE_MACID_INT_EN		BIT(9)
#define BIT_PRETXERR_HANDLE_FSIMR			BIT(8)
#define BIT_FS_WLACTOFF_INT_EN				BIT(5)
#define BIT_FS_WLACTON_INT_EN				BIT(4)
#define BIT_FS_BCN_RX_INT_EN				BIT(3)
#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN		BIT(2)
#define BIT_TRPC_TO_INT_EN				BIT(1)
#define BIT_BIT_RPC_O_T_INT_EN				BIT(0)

/* 2 REG_FE1ISR				(Offset 0x0124) */

#define BIT_NOT_BEACON_INT				BIT(31)
#define BIT_CPWM_TOGGLING				BIT(31)
#define BIT_FWFF_FULL_INT				BIT(30)
#define BIT_BB_STOP_RX_INT				BIT(29)
#define BIT_FS_RXDMA2_DONE_INT				BIT(28)
#define BIT_RXPLCP_CHKOK_INT				BIT(27)
#define BIT_FS_RXDONE1_INT				BIT(26)
#define BIT_FS_RX_BCN_P4_INT				BIT(25)
#define BIT_FS_RX_BCN_P3_INT				BIT(24)

#define BIT_SHIFT_CPWM_MOD				24
#define BIT_MASK_CPWM_MOD				0x7f
#define BIT_CPWM_MOD(x)				(((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD)
#define BITS_CPWM_MOD					(BIT_MASK_CPWM_MOD << BIT_SHIFT_CPWM_MOD)
#define BIT_CLEAR_CPWM_MOD(x)				((x) & (~BITS_CPWM_MOD))
#define BIT_GET_CPWM_MOD(x)				(((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD)
#define BIT_SET_CPWM_MOD(x, v)				(BIT_CLEAR_CPWM_MOD(x) | BIT_CPWM_MOD(v))

#define BIT_FS_RX_BCN_P2_INT				BIT(23)
#define BIT_FS_RX_BCN_P1_INT				BIT(22)
#define BIT_FS_RX_BCN_P0_INT				BIT(21)
#define BIT_FS_RX_UMD0_INT				BIT(20)
#define BIT_FS_RX_UMD1_INT				BIT(19)
#define BIT_FS_RX_BMD0_INT				BIT(18)
#define BIT_FS_RX_BMD1_INT				BIT(17)
#define BIT_FS_RXDONE0_INT				BIT(16)
#define BIT_FS_WWLAN_INT				BIT(15)
#define BIT_FS_SOUND_DONE_INT				BIT(14)
#define BIT_FS_LP_STBY_INT				BIT(13)
#define BIT_FS_TRL_MTR_INT				BIT(12)
#define BIT_FS_BF1_PRETO_INT				BIT(11)
#define BIT_FS_BF0_PRETO_INT				BIT(10)
#define BIT_FS_PTCL_RELEASE_MACID_INT			BIT(9)
#define BIT_PRETXERR_HANDLE_FSISR			BIT(8)
#define BIT_FS_WLACTOFF_INT				BIT(5)
#define BIT_FS_WLACTON_INT				BIT(4)
#define BIT_FS_BCN_RX_INT				BIT(3)
#define BIT_FS_REG_MAILBOX_TO_I2C_INT			BIT(2)
#define BIT_FS_TRPC_TO_INT				BIT(1)
#define BIT_FS_RPC_O_T_INT				BIT(0)

/* 2 REG_FWIMR				(Offset 0x0130) */

#define BIT_FS_TXBCNOK_MB7_INT_EN			BIT(31)
#define BIT_FS_TXBCNOK_MB6_INT_EN			BIT(30)
#define BIT_FS_TXBCNOK_MB5_INT_EN			BIT(29)
#define BIT_FS_TXBCNOK_MB4_INT_EN			BIT(28)
#define BIT_FS_TXBCNOK_MB3_INT_EN			BIT(27)
#define BIT_FS_TXBCNOK_MB2_INT_EN			BIT(26)
#define BIT_FS_TXBCNOK_MB1_INT_EN			BIT(25)
#define BIT_FS_TXBCNOK_MB0_INT_EN			BIT(24)
#define BIT_FS_TXBCNERR_MB7_INT_EN			BIT(23)
#define BIT_FS_TXBCNERR_MB6_INT_EN			BIT(22)
#define BIT_FS_TXBCNERR_MB5_INT_EN			BIT(21)
#define BIT_FS_TXBCNERR_MB4_INT_EN			BIT(20)
#define BIT_FS_TXBCNERR_MB3_INT_EN			BIT(19)
#define BIT_FS_TXBCNERR_MB2_INT_EN			BIT(18)
#define BIT_FS_TXBCNERR_MB1_INT_EN			BIT(17)
#define BIT_FS_TXBCNERR_MB0_INT_EN			BIT(16)
#define BIT_CPUMGN_POLLED_PKT_DONE_INT_EN		BIT(15)
#define BIT_FS_INT_IPSEC_EN				BIT(14)
#define BIT_FS_MGNTQ_FF_RELEASE_INT_EN			BIT(13)
#define BIT_FS_MGNTQFF_TO_INT_EN			BIT(12)
#define BIT_FS_CPUMGQ_ERR_INT_EN			BIT(11)
#define BIT_FS_HIOE_INT_EN				BIT(10)
#define BIT_FS_DDMA0_LP_INT_EN				BIT(9)
#define BIT_FS_DDMA0_HP_INT_EN				BIT(8)
#define BIT_FS_TRXRPT_INT_EN				BIT(7)
#define BIT_FS_C2H_W_READY_INT_EN			BIT(6)
#define BIT_FS_HRCV_INT_EN				BIT(5)
#define BIT_FS_H2CCMD_INT_EN				BIT(4)
#define BIT_FS_TXPKTIN_P0_INT_EN			BIT(3)
#define BIT_FS_ERRORHDL_INT_EN				BIT(2)
#define BIT_FS_TXCCX_INT_EN				BIT(1)
#define BIT_FS_TXCLOSE_INT_EN				BIT(0)

/* 2 REG_FWISR				(Offset 0x0134) */

#define BIT_FS_TXBCNOK_MB7_INT				BIT(31)
#define BIT_FS_TXBCNOK_MB6_INT				BIT(30)
#define BIT_FS_TXBCNOK_MB5_INT				BIT(29)
#define BIT_FS_TXBCNOK_MB4_INT				BIT(28)
#define BIT_FS_TXBCNOK_MB3_INT				BIT(27)
#define BIT_FS_TXBCNOK_MB2_INT				BIT(26)
#define BIT_FS_TXBCNOK_MB1_INT				BIT(25)
#define BIT_FS_TXBCNOK_MB0_INT				BIT(24)
#define BIT_FS_TXBCNERR_MB7_INT			BIT(23)
#define BIT_FS_TXBCNERR_MB6_INT			BIT(22)
#define BIT_FS_TXBCNERR_MB5_INT			BIT(21)
#define BIT_FS_TXBCNERR_MB4_INT			BIT(20)
#define BIT_FS_TXBCNERR_MB3_INT			BIT(19)
#define BIT_FS_TXBCNERR_MB2_INT			BIT(18)
#define BIT_FS_TXBCNERR_MB1_INT			BIT(17)
#define BIT_FS_TXBCNERR_MB0_INT			BIT(16)
#define BIT_CPUMGN_POLLED_PKT_DONE_INT			BIT(15)
#define BIT_FS_INT_IPSEC				BIT(14)
#define BIT_FS_MGNTQ_FF_RELEASE_INT			BIT(13)
#define BIT_FS_MGNTQFF_TO_INT				BIT(12)
#define BIT_FS_CPUMGQ_ERR_INT				BIT(11)
#define BIT_FS_HIOE_INT				BIT(10)
#define BIT_FS_DDMA0_LP_INT				BIT(9)
#define BIT_FS_DDMA0_HP_INT				BIT(8)
#define BIT_FS_TRXRPT_INT				BIT(7)
#define BIT_FS_C2H_W_READY_INT				BIT(6)
#define BIT_FS_HRCV_INT				BIT(5)
#define BIT_FS_H2CCMD_INT				BIT(4)
#define BIT_FS_TXPKTIN_P0_INT				BIT(3)
#define BIT_FS_ERRORHDL_INT				BIT(2)
#define BIT_FS_TXCCX_INT				BIT(1)
#define BIT_FS_TXCLOSE_INT				BIT(0)

/* 2 REG_FTIMR				(Offset 0x0138) */

#define BIT_PS_TIMER_C_EARLY_INT_EN			BIT(23)
#define BIT_PS_TIMER_B_EARLY_INT_EN			BIT(22)
#define BIT_PS_TIMER_A_EARLY_INT_EN			BIT(21)
#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN		BIT(20)
#define BIT_PS_TIMER_C_INT_EN				BIT(19)
#define BIT_PS_TIMER_B_INT_EN				BIT(18)
#define BIT_PS_TIMER_A_INT_EN				BIT(17)
#define BIT_CPUMGQ_TX_TIMER_INT_EN			BIT(16)
#define BIT_FS_PS_TIMEOUT2_EN				BIT(15)
#define BIT_FS_PS_TIMEOUT1_EN				BIT(14)
#define BIT_FS_PS_TIMEOUT0_EN				BIT(13)
#define BIT_FS_GTINT6_EN				BIT(6)
#define BIT_FS_GTINT5_EN				BIT(5)
#define BIT_FS_GTINT4_EN				BIT(4)
#define BIT_FS_GTINT3_EN				BIT(3)
#define BIT_FS_GTINT2_EN				BIT(2)
#define BIT_FS_GTINT1_EN				BIT(1)
#define BIT_FS_GTINT0_EN				BIT(0)

/* 2 REG_FTISR				(Offset 0x013C) */

#define BIT_PS_TIMER_C_EARLY_INT			BIT(23)
#define BIT_PS_TIMER_B_EARLY_INT			BIT(22)
#define BIT_PS_TIMER_A_EARLY_INT			BIT(21)
#define BIT_CPUMGQ_TX_TIMER_EARLY_INT			BIT(20)
#define BIT_PS_TIMER_C_INT				BIT(19)
#define BIT_PS_TIMER_B_INT				BIT(18)
#define BIT_PS_TIMER_A_INT				BIT(17)
#define BIT_CPUMGQ_TX_TIMER_INT			BIT(16)
#define BIT_FS_PS_TIMEOUT2_INT				BIT(15)
#define BIT_FS_PS_TIMEOUT1_INT				BIT(14)
#define BIT_FS_PS_TIMEOUT0_INT				BIT(13)
#define BIT_FS_GTINT6_INT				BIT(6)
#define BIT_FS_GTINT5_INT				BIT(5)
#define BIT_FS_GTINT4_INT				BIT(4)
#define BIT_FS_GTINT3_INT				BIT(3)
#define BIT_FS_GTINT2_INT				BIT(2)
#define BIT_FS_GTINT1_INT				BIT(1)
#define BIT_FS_GTINT0_INT				BIT(0)

/* 2 REG_PKTBUF_DBG_CTRL			(Offset 0x0140) */

#define BIT_SHIFT_PKTBUF_WRITE_EN			24
#define BIT_MASK_PKTBUF_WRITE_EN			0xff
#define BIT_PKTBUF_WRITE_EN(x)				(((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN)
#define BITS_PKTBUF_WRITE_EN				(BIT_MASK_PKTBUF_WRITE_EN << BIT_SHIFT_PKTBUF_WRITE_EN)
#define BIT_CLEAR_PKTBUF_WRITE_EN(x)			((x) & (~BITS_PKTBUF_WRITE_EN))
#define BIT_GET_PKTBUF_WRITE_EN(x)			(((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN)
#define BIT_SET_PKTBUF_WRITE_EN(x, v)			(BIT_CLEAR_PKTBUF_WRITE_EN(x) | BIT_PKTBUF_WRITE_EN(v))

#define BIT_TXPKT_BUF_READ_EN				BIT(23)
#define BIT_TXRPT_BUF_READ_EN				BIT(20)
#define BIT_RXPKT_BUF_READ_EN				BIT(16)
#define BIT_FIFO_DBG_EXT				BIT(13)

#define BIT_SHIFT_FIFO_DBG_AD				0
#define BIT_MASK_FIFO_DBG_AD				0x1fff
#define BIT_FIFO_DBG_AD(x)				(((x) & BIT_MASK_FIFO_DBG_AD) << BIT_SHIFT_FIFO_DBG_AD)
#define BITS_FIFO_DBG_AD				(BIT_MASK_FIFO_DBG_AD << BIT_SHIFT_FIFO_DBG_AD)
#define BIT_CLEAR_FIFO_DBG_AD(x)			((x) & (~BITS_FIFO_DBG_AD))
#define BIT_GET_FIFO_DBG_AD(x)				(((x) >> BIT_SHIFT_FIFO_DBG_AD) & BIT_MASK_FIFO_DBG_AD)
#define BIT_SET_FIFO_DBG_AD(x, v)			(BIT_CLEAR_FIFO_DBG_AD(x) | BIT_FIFO_DBG_AD(v))

/* 2 REG_PKTBUF_DBG_DATA_L			(Offset 0x0144) */

#define BIT_SHIFT_PKTBUF_DBG_DATA_L			0
#define BIT_MASK_PKTBUF_DBG_DATA_L			0xffffffffL
#define BIT_PKTBUF_DBG_DATA_L(x)			(((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L)
#define BITS_PKTBUF_DBG_DATA_L				(BIT_MASK_PKTBUF_DBG_DATA_L << BIT_SHIFT_PKTBUF_DBG_DATA_L)
#define BIT_CLEAR_PKTBUF_DBG_DATA_L(x)			((x) & (~BITS_PKTBUF_DBG_DATA_L))
#define BIT_GET_PKTBUF_DBG_DATA_L(x)			(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L)
#define BIT_SET_PKTBUF_DBG_DATA_L(x, v)		(BIT_CLEAR_PKTBUF_DBG_DATA_L(x) | BIT_PKTBUF_DBG_DATA_L(v))

/* 2 REG_PKTBUF_DBG_DATA_H			(Offset 0x0148) */

#define BIT_SHIFT_PKTBUF_DBG_DATA__H			0
#define BIT_MASK_PKTBUF_DBG_DATA__H			0xffffffffL
#define BIT_PKTBUF_DBG_DATA__H(x)			(((x) & BIT_MASK_PKTBUF_DBG_DATA__H) << BIT_SHIFT_PKTBUF_DBG_DATA__H)
#define BITS_PKTBUF_DBG_DATA__H			(BIT_MASK_PKTBUF_DBG_DATA__H << BIT_SHIFT_PKTBUF_DBG_DATA__H)
#define BIT_CLEAR_PKTBUF_DBG_DATA__H(x)		((x) & (~BITS_PKTBUF_DBG_DATA__H))
#define BIT_GET_PKTBUF_DBG_DATA__H(x)			(((x) >> BIT_SHIFT_PKTBUF_DBG_DATA__H) & BIT_MASK_PKTBUF_DBG_DATA__H)
#define BIT_SET_PKTBUF_DBG_DATA__H(x, v)		(BIT_CLEAR_PKTBUF_DBG_DATA__H(x) | BIT_PKTBUF_DBG_DATA__H(v))

/* 2 REG_CPWM2				(Offset 0x014C) */

#define BIT_SHIFT_L0S_TO_RCVY_NUM			16
#define BIT_MASK_L0S_TO_RCVY_NUM			0xff
#define BIT_L0S_TO_RCVY_NUM(x)				(((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM)
#define BITS_L0S_TO_RCVY_NUM				(BIT_MASK_L0S_TO_RCVY_NUM << BIT_SHIFT_L0S_TO_RCVY_NUM)
#define BIT_CLEAR_L0S_TO_RCVY_NUM(x)			((x) & (~BITS_L0S_TO_RCVY_NUM))
#define BIT_GET_L0S_TO_RCVY_NUM(x)			(((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM)
#define BIT_SET_L0S_TO_RCVY_NUM(x, v)			(BIT_CLEAR_L0S_TO_RCVY_NUM(x) | BIT_L0S_TO_RCVY_NUM(v))

#define BIT_CPWM2_TOGGLING				BIT(15)

#define BIT_SHIFT_CPWM2_MOD				0
#define BIT_MASK_CPWM2_MOD				0x7fff
#define BIT_CPWM2_MOD(x)				(((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD)
#define BITS_CPWM2_MOD					(BIT_MASK_CPWM2_MOD << BIT_SHIFT_CPWM2_MOD)
#define BIT_CLEAR_CPWM2_MOD(x)				((x) & (~BITS_CPWM2_MOD))
#define BIT_GET_CPWM2_MOD(x)				(((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD)
#define BIT_SET_CPWM2_MOD(x, v)			(BIT_CLEAR_CPWM2_MOD(x) | BIT_CPWM2_MOD(v))

/* 2 REG_TC0_CTRL				(Offset 0x0150) */

#define BIT_TC0INT_EN					BIT(26)
#define BIT_TC0MODE					BIT(25)
#define BIT_TC0EN					BIT(24)

#define BIT_SHIFT_TC0DATA				0
#define BIT_MASK_TC0DATA				0xffffff
#define BIT_TC0DATA(x)					(((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA)
#define BITS_TC0DATA					(BIT_MASK_TC0DATA << BIT_SHIFT_TC0DATA)
#define BIT_CLEAR_TC0DATA(x)				((x) & (~BITS_TC0DATA))
#define BIT_GET_TC0DATA(x)				(((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA)
#define BIT_SET_TC0DATA(x, v)				(BIT_CLEAR_TC0DATA(x) | BIT_TC0DATA(v))

/* 2 REG_TC1_CTRL				(Offset 0x0154) */

#define BIT_TC1INT_EN					BIT(26)
#define BIT_TC1MODE					BIT(25)
#define BIT_TC1EN					BIT(24)

#define BIT_SHIFT_TC1DATA				0
#define BIT_MASK_TC1DATA				0xffffff
#define BIT_TC1DATA(x)					(((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA)
#define BITS_TC1DATA					(BIT_MASK_TC1DATA << BIT_SHIFT_TC1DATA)
#define BIT_CLEAR_TC1DATA(x)				((x) & (~BITS_TC1DATA))
#define BIT_GET_TC1DATA(x)				(((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA)
#define BIT_SET_TC1DATA(x, v)				(BIT_CLEAR_TC1DATA(x) | BIT_TC1DATA(v))

/* 2 REG_TC2_CTRL				(Offset 0x0158) */

#define BIT_TC2INT_EN					BIT(26)
#define BIT_TC2MODE					BIT(25)
#define BIT_TC2EN					BIT(24)

#define BIT_SHIFT_TC2DATA				0
#define BIT_MASK_TC2DATA				0xffffff
#define BIT_TC2DATA(x)					(((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA)
#define BITS_TC2DATA					(BIT_MASK_TC2DATA << BIT_SHIFT_TC2DATA)
#define BIT_CLEAR_TC2DATA(x)				((x) & (~BITS_TC2DATA))
#define BIT_GET_TC2DATA(x)				(((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA)
#define BIT_SET_TC2DATA(x, v)				(BIT_CLEAR_TC2DATA(x) | BIT_TC2DATA(v))

/* 2 REG_TC3_CTRL				(Offset 0x015C) */

#define BIT_TC3INT_EN					BIT(26)
#define BIT_TC3MODE					BIT(25)
#define BIT_TC3EN					BIT(24)

#define BIT_SHIFT_TC3DATA				0
#define BIT_MASK_TC3DATA				0xffffff
#define BIT_TC3DATA(x)					(((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA)
#define BITS_TC3DATA					(BIT_MASK_TC3DATA << BIT_SHIFT_TC3DATA)
#define BIT_CLEAR_TC3DATA(x)				((x) & (~BITS_TC3DATA))
#define BIT_GET_TC3DATA(x)				(((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA)
#define BIT_SET_TC3DATA(x, v)				(BIT_CLEAR_TC3DATA(x) | BIT_TC3DATA(v))

/* 2 REG_TC4_CTRL				(Offset 0x0160) */

#define BIT_TC4INT_EN					BIT(26)
#define BIT_TC4MODE					BIT(25)
#define BIT_TC4EN					BIT(24)

#define BIT_SHIFT_TC4DATA				0
#define BIT_MASK_TC4DATA				0xffffff
#define BIT_TC4DATA(x)					(((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA)
#define BITS_TC4DATA					(BIT_MASK_TC4DATA << BIT_SHIFT_TC4DATA)
#define BIT_CLEAR_TC4DATA(x)				((x) & (~BITS_TC4DATA))
#define BIT_GET_TC4DATA(x)				(((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA)
#define BIT_SET_TC4DATA(x, v)				(BIT_CLEAR_TC4DATA(x) | BIT_TC4DATA(v))

/* 2 REG_TCUNIT_BASE				(Offset 0x0164) */

#define BIT_SHIFT_TC_UNIT_BASE				0
#define BIT_MASK_TC_UNIT_BASE				0x3fff
#define BIT_TC_UNIT_BASE(x)				(((x) & BIT_MASK_TC_UNIT_BASE) << BIT_SHIFT_TC_UNIT_BASE)
#define BITS_TC_UNIT_BASE				(BIT_MASK_TC_UNIT_BASE << BIT_SHIFT_TC_UNIT_BASE)
#define BIT_CLEAR_TC_UNIT_BASE(x)			((x) & (~BITS_TC_UNIT_BASE))
#define BIT_GET_TC_UNIT_BASE(x)			(((x) >> BIT_SHIFT_TC_UNIT_BASE) & BIT_MASK_TC_UNIT_BASE)
#define BIT_SET_TC_UNIT_BASE(x, v)			(BIT_CLEAR_TC_UNIT_BASE(x) | BIT_TC_UNIT_BASE(v))

/* 2 REG_TC5_CTRL				(Offset 0x0168) */

#define BIT_TC50INT_EN					BIT(26)
#define BIT_TC5MODE					BIT(25)
#define BIT_TC5EN					BIT(24)

#define BIT_SHIFT_TC5DATA				0
#define BIT_MASK_TC5DATA				0xffffff
#define BIT_TC5DATA(x)					(((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA)
#define BITS_TC5DATA					(BIT_MASK_TC5DATA << BIT_SHIFT_TC5DATA)
#define BIT_CLEAR_TC5DATA(x)				((x) & (~BITS_TC5DATA))
#define BIT_GET_TC5DATA(x)				(((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA)
#define BIT_SET_TC5DATA(x, v)				(BIT_CLEAR_TC5DATA(x) | BIT_TC5DATA(v))

/* 2 REG_TC6_CTRL				(Offset 0x016C) */

#define BIT_TC60INT_EN					BIT(26)
#define BIT_TC6MODE					BIT(25)
#define BIT_TC6EN					BIT(24)

#define BIT_SHIFT_TC6DATA				0
#define BIT_MASK_TC6DATA				0xffffff
#define BIT_TC6DATA(x)					(((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA)
#define BITS_TC6DATA					(BIT_MASK_TC6DATA << BIT_SHIFT_TC6DATA)
#define BIT_CLEAR_TC6DATA(x)				((x) & (~BITS_TC6DATA))
#define BIT_GET_TC6DATA(x)				(((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA)
#define BIT_SET_TC6DATA(x, v)				(BIT_CLEAR_TC6DATA(x) | BIT_TC6DATA(v))

/* 2 REG_MBIST_DRF_FAIL_V1			(Offset 0x0170) */

#define BIT_SHIFT_8051_MBIST_FAIL			26
#define BIT_MASK_8051_MBIST_FAIL			0x7
#define BIT_8051_MBIST_FAIL(x)				(((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL)
#define BITS_8051_MBIST_FAIL				(BIT_MASK_8051_MBIST_FAIL << BIT_SHIFT_8051_MBIST_FAIL)
#define BIT_CLEAR_8051_MBIST_FAIL(x)			((x) & (~BITS_8051_MBIST_FAIL))
#define BIT_GET_8051_MBIST_FAIL(x)			(((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL)
#define BIT_SET_8051_MBIST_FAIL(x, v)			(BIT_CLEAR_8051_MBIST_FAIL(x) | BIT_8051_MBIST_FAIL(v))

#define BIT_SHIFT_USB_MBIST_FAIL			24
#define BIT_MASK_USB_MBIST_FAIL			0x3
#define BIT_USB_MBIST_FAIL(x)				(((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL)
#define BITS_USB_MBIST_FAIL				(BIT_MASK_USB_MBIST_FAIL << BIT_SHIFT_USB_MBIST_FAIL)
#define BIT_CLEAR_USB_MBIST_FAIL(x)			((x) & (~BITS_USB_MBIST_FAIL))
#define BIT_GET_USB_MBIST_FAIL(x)			(((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL)
#define BIT_SET_USB_MBIST_FAIL(x, v)			(BIT_CLEAR_USB_MBIST_FAIL(x) | BIT_USB_MBIST_FAIL(v))

#define BIT_SHIFT_PCIE_MBIST_FAIL			16
#define BIT_MASK_PCIE_MBIST_FAIL			0x3f
#define BIT_PCIE_MBIST_FAIL(x)				(((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL)
#define BITS_PCIE_MBIST_FAIL				(BIT_MASK_PCIE_MBIST_FAIL << BIT_SHIFT_PCIE_MBIST_FAIL)
#define BIT_CLEAR_PCIE_MBIST_FAIL(x)			((x) & (~BITS_PCIE_MBIST_FAIL))
#define BIT_GET_PCIE_MBIST_FAIL(x)			(((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL)
#define BIT_SET_PCIE_MBIST_FAIL(x, v)			(BIT_CLEAR_PCIE_MBIST_FAIL(x) | BIT_PCIE_MBIST_FAIL(v))

#define BIT_SHIFT_MAC_MBIST_FAIL			0
#define BIT_MASK_MAC_MBIST_FAIL			0x3fff
#define BIT_MAC_MBIST_FAIL(x)				(((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL)
#define BITS_MAC_MBIST_FAIL				(BIT_MASK_MAC_MBIST_FAIL << BIT_SHIFT_MAC_MBIST_FAIL)
#define BIT_CLEAR_MAC_MBIST_FAIL(x)			((x) & (~BITS_MAC_MBIST_FAIL))
#define BIT_GET_MAC_MBIST_FAIL(x)			(((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL)
#define BIT_SET_MAC_MBIST_FAIL(x, v)			(BIT_CLEAR_MAC_MBIST_FAIL(x) | BIT_MAC_MBIST_FAIL(v))

/* 2 REG_MBIST_START_PAUSE_V1		(Offset 0x0174) */

#define BIT_SHIFT_8051_MBIST_START_PAUSE		26
#define BIT_MASK_8051_MBIST_START_PAUSE		0x7
#define BIT_8051_MBIST_START_PAUSE(x)			(((x) & BIT_MASK_8051_MBIST_START_PAUSE) << BIT_SHIFT_8051_MBIST_START_PAUSE)
#define BITS_8051_MBIST_START_PAUSE			(BIT_MASK_8051_MBIST_START_PAUSE << BIT_SHIFT_8051_MBIST_START_PAUSE)
#define BIT_CLEAR_8051_MBIST_START_PAUSE(x)		((x) & (~BITS_8051_MBIST_START_PAUSE))
#define BIT_GET_8051_MBIST_START_PAUSE(x)		(((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) & BIT_MASK_8051_MBIST_START_PAUSE)
#define BIT_SET_8051_MBIST_START_PAUSE(x, v)		(BIT_CLEAR_8051_MBIST_START_PAUSE(x) | BIT_8051_MBIST_START_PAUSE(v))

#define BIT_SHIFT_USB_MBIST_START_PAUSE		24
#define BIT_MASK_USB_MBIST_START_PAUSE			0x3
#define BIT_USB_MBIST_START_PAUSE(x)			(((x) & BIT_MASK_USB_MBIST_START_PAUSE) << BIT_SHIFT_USB_MBIST_START_PAUSE)
#define BITS_USB_MBIST_START_PAUSE			(BIT_MASK_USB_MBIST_START_PAUSE << BIT_SHIFT_USB_MBIST_START_PAUSE)
#define BIT_CLEAR_USB_MBIST_START_PAUSE(x)		((x) & (~BITS_USB_MBIST_START_PAUSE))
#define BIT_GET_USB_MBIST_START_PAUSE(x)		(((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) & BIT_MASK_USB_MBIST_START_PAUSE)
#define BIT_SET_USB_MBIST_START_PAUSE(x, v)		(BIT_CLEAR_USB_MBIST_START_PAUSE(x) | BIT_USB_MBIST_START_PAUSE(v))

#define BIT_SHIFT_PCIE_MBIST_START_PAUSE		16
#define BIT_MASK_PCIE_MBIST_START_PAUSE		0x3f
#define BIT_PCIE_MBIST_START_PAUSE(x)			(((x) & BIT_MASK_PCIE_MBIST_START_PAUSE) << BIT_SHIFT_PCIE_MBIST_START_PAUSE)
#define BITS_PCIE_MBIST_START_PAUSE			(BIT_MASK_PCIE_MBIST_START_PAUSE << BIT_SHIFT_PCIE_MBIST_START_PAUSE)
#define BIT_CLEAR_PCIE_MBIST_START_PAUSE(x)		((x) & (~BITS_PCIE_MBIST_START_PAUSE))
#define BIT_GET_PCIE_MBIST_START_PAUSE(x)		(((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) & BIT_MASK_PCIE_MBIST_START_PAUSE)
#define BIT_SET_PCIE_MBIST_START_PAUSE(x, v)		(BIT_CLEAR_PCIE_MBIST_START_PAUSE(x) | BIT_PCIE_MBIST_START_PAUSE(v))

#define BIT_SHIFT_MAC_MBIST_START_PAUSE		0
#define BIT_MASK_MAC_MBIST_START_PAUSE			0xfff
#define BIT_MAC_MBIST_START_PAUSE(x)			(((x) & BIT_MASK_MAC_MBIST_START_PAUSE) << BIT_SHIFT_MAC_MBIST_START_PAUSE)
#define BITS_MAC_MBIST_START_PAUSE			(BIT_MASK_MAC_MBIST_START_PAUSE << BIT_SHIFT_MAC_MBIST_START_PAUSE)
#define BIT_CLEAR_MAC_MBIST_START_PAUSE(x)		((x) & (~BITS_MAC_MBIST_START_PAUSE))
#define BIT_GET_MAC_MBIST_START_PAUSE(x)		(((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) & BIT_MASK_MAC_MBIST_START_PAUSE)
#define BIT_SET_MAC_MBIST_START_PAUSE(x, v)		(BIT_CLEAR_MAC_MBIST_START_PAUSE(x) | BIT_MAC_MBIST_START_PAUSE(v))

/* 2 REG_MBIST_DONE_V1			(Offset 0x0178) */

#define BIT_SHIFT_8051_MBIST_DONE			26
#define BIT_MASK_8051_MBIST_DONE			0x7
#define BIT_8051_MBIST_DONE(x)				(((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE)
#define BITS_8051_MBIST_DONE				(BIT_MASK_8051_MBIST_DONE << BIT_SHIFT_8051_MBIST_DONE)
#define BIT_CLEAR_8051_MBIST_DONE(x)			((x) & (~BITS_8051_MBIST_DONE))
#define BIT_GET_8051_MBIST_DONE(x)			(((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE)
#define BIT_SET_8051_MBIST_DONE(x, v)			(BIT_CLEAR_8051_MBIST_DONE(x) | BIT_8051_MBIST_DONE(v))

#define BIT_SHIFT_USB_MBIST_DONE			24
#define BIT_MASK_USB_MBIST_DONE			0x3
#define BIT_USB_MBIST_DONE(x)				(((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE)
#define BITS_USB_MBIST_DONE				(BIT_MASK_USB_MBIST_DONE << BIT_SHIFT_USB_MBIST_DONE)
#define BIT_CLEAR_USB_MBIST_DONE(x)			((x) & (~BITS_USB_MBIST_DONE))
#define BIT_GET_USB_MBIST_DONE(x)			(((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE)
#define BIT_SET_USB_MBIST_DONE(x, v)			(BIT_CLEAR_USB_MBIST_DONE(x) | BIT_USB_MBIST_DONE(v))

#define BIT_SHIFT_PCIE_MBIST_DONE			16
#define BIT_MASK_PCIE_MBIST_DONE			0x3f
#define BIT_PCIE_MBIST_DONE(x)				(((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE)
#define BITS_PCIE_MBIST_DONE				(BIT_MASK_PCIE_MBIST_DONE << BIT_SHIFT_PCIE_MBIST_DONE)
#define BIT_CLEAR_PCIE_MBIST_DONE(x)			((x) & (~BITS_PCIE_MBIST_DONE))
#define BIT_GET_PCIE_MBIST_DONE(x)			(((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE)
#define BIT_SET_PCIE_MBIST_DONE(x, v)			(BIT_CLEAR_PCIE_MBIST_DONE(x) | BIT_PCIE_MBIST_DONE(v))

#define BIT_SHIFT_MAC_MBIST_DONE			0
#define BIT_MASK_MAC_MBIST_DONE			0xfff
#define BIT_MAC_MBIST_DONE(x)				(((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE)
#define BITS_MAC_MBIST_DONE				(BIT_MASK_MAC_MBIST_DONE << BIT_SHIFT_MAC_MBIST_DONE)
#define BIT_CLEAR_MAC_MBIST_DONE(x)			((x) & (~BITS_MAC_MBIST_DONE))
#define BIT_GET_MAC_MBIST_DONE(x)			(((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE)
#define BIT_SET_MAC_MBIST_DONE(x, v)			(BIT_CLEAR_MAC_MBIST_DONE(x) | BIT_MAC_MBIST_DONE(v))

/* 2 REG_MBIST_FAIL_NRML_V1			(Offset 0x017C) */

#define BIT_SHIFT_8051_MBIST_NMRL_FAIL			26
#define BIT_MASK_8051_MBIST_NMRL_FAIL			0x7
#define BIT_8051_MBIST_NMRL_FAIL(x)			(((x) & BIT_MASK_8051_MBIST_NMRL_FAIL) << BIT_SHIFT_8051_MBIST_NMRL_FAIL)
#define BITS_8051_MBIST_NMRL_FAIL			(BIT_MASK_8051_MBIST_NMRL_FAIL << BIT_SHIFT_8051_MBIST_NMRL_FAIL)
#define BIT_CLEAR_8051_MBIST_NMRL_FAIL(x)		((x) & (~BITS_8051_MBIST_NMRL_FAIL))
#define BIT_GET_8051_MBIST_NMRL_FAIL(x)		(((x) >> BIT_SHIFT_8051_MBIST_NMRL_FAIL) & BIT_MASK_8051_MBIST_NMRL_FAIL)
#define BIT_SET_8051_MBIST_NMRL_FAIL(x, v)		(BIT_CLEAR_8051_MBIST_NMRL_FAIL(x) | BIT_8051_MBIST_NMRL_FAIL(v))

#define BIT_SHIFT_USB_MBIST_NMRL_FAIL			24
#define BIT_MASK_USB_MBIST_NMRL_FAIL			0x3
#define BIT_USB_MBIST_NMRL_FAIL(x)			(((x) & BIT_MASK_USB_MBIST_NMRL_FAIL) << BIT_SHIFT_USB_MBIST_NMRL_FAIL)
#define BITS_USB_MBIST_NMRL_FAIL			(BIT_MASK_USB_MBIST_NMRL_FAIL << BIT_SHIFT_USB_MBIST_NMRL_FAIL)
#define BIT_CLEAR_USB_MBIST_NMRL_FAIL(x)		((x) & (~BITS_USB_MBIST_NMRL_FAIL))
#define BIT_GET_USB_MBIST_NMRL_FAIL(x)			(((x) >> BIT_SHIFT_USB_MBIST_NMRL_FAIL) & BIT_MASK_USB_MBIST_NMRL_FAIL)
#define BIT_SET_USB_MBIST_NMRL_FAIL(x, v)		(BIT_CLEAR_USB_MBIST_NMRL_FAIL(x) | BIT_USB_MBIST_NMRL_FAIL(v))

#define BIT_SHIFT_PCIE_MBIST_NMRL_FAIL			16
#define BIT_MASK_PCIE_MBIST_NMRL_FAIL			0x3f
#define BIT_PCIE_MBIST_NMRL_FAIL(x)			(((x) & BIT_MASK_PCIE_MBIST_NMRL_FAIL) << BIT_SHIFT_PCIE_MBIST_NMRL_FAIL)
#define BITS_PCIE_MBIST_NMRL_FAIL			(BIT_MASK_PCIE_MBIST_NMRL_FAIL << BIT_SHIFT_PCIE_MBIST_NMRL_FAIL)
#define BIT_CLEAR_PCIE_MBIST_NMRL_FAIL(x)		((x) & (~BITS_PCIE_MBIST_NMRL_FAIL))
#define BIT_GET_PCIE_MBIST_NMRL_FAIL(x)		(((x) >> BIT_SHIFT_PCIE_MBIST_NMRL_FAIL) & BIT_MASK_PCIE_MBIST_NMRL_FAIL)
#define BIT_SET_PCIE_MBIST_NMRL_FAIL(x, v)		(BIT_CLEAR_PCIE_MBIST_NMRL_FAIL(x) | BIT_PCIE_MBIST_NMRL_FAIL(v))

#define BIT_SHIFT_MAC_MBIST_NMRL_FAIL			0
#define BIT_MASK_MAC_MBIST_NMRL_FAIL			0x3fff
#define BIT_MAC_MBIST_NMRL_FAIL(x)			(((x) & BIT_MASK_MAC_MBIST_NMRL_FAIL) << BIT_SHIFT_MAC_MBIST_NMRL_FAIL)
#define BITS_MAC_MBIST_NMRL_FAIL			(BIT_MASK_MAC_MBIST_NMRL_FAIL << BIT_SHIFT_MAC_MBIST_NMRL_FAIL)
#define BIT_CLEAR_MAC_MBIST_NMRL_FAIL(x)		((x) & (~BITS_MAC_MBIST_NMRL_FAIL))
#define BIT_GET_MAC_MBIST_NMRL_FAIL(x)			(((x) >> BIT_SHIFT_MAC_MBIST_NMRL_FAIL) & BIT_MASK_MAC_MBIST_NMRL_FAIL)
#define BIT_SET_MAC_MBIST_NMRL_FAIL(x, v)		(BIT_CLEAR_MAC_MBIST_NMRL_FAIL(x) | BIT_MAC_MBIST_NMRL_FAIL(v))

/* 2 REG_AES_DECRPT_DATA			(Offset 0x0180) */

#define BIT_SHIFT_IPS_CFG_ADDR				0
#define BIT_MASK_IPS_CFG_ADDR				0xff
#define BIT_IPS_CFG_ADDR(x)				(((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR)
#define BITS_IPS_CFG_ADDR				(BIT_MASK_IPS_CFG_ADDR << BIT_SHIFT_IPS_CFG_ADDR)
#define BIT_CLEAR_IPS_CFG_ADDR(x)			((x) & (~BITS_IPS_CFG_ADDR))
#define BIT_GET_IPS_CFG_ADDR(x)			(((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR)
#define BIT_SET_IPS_CFG_ADDR(x, v)			(BIT_CLEAR_IPS_CFG_ADDR(x) | BIT_IPS_CFG_ADDR(v))

/* 2 REG_AES_DECRPT_CFG			(Offset 0x0184) */

#define BIT_SHIFT_IPS_CFGWD				0
#define BIT_MASK_IPS_CFGWD				0xffffffffL
#define BIT_IPS_CFGWD(x)				(((x) & BIT_MASK_IPS_CFGWD) << BIT_SHIFT_IPS_CFGWD)
#define BITS_IPS_CFGWD					(BIT_MASK_IPS_CFGWD << BIT_SHIFT_IPS_CFGWD)
#define BIT_CLEAR_IPS_CFGWD(x)				((x) & (~BITS_IPS_CFGWD))
#define BIT_GET_IPS_CFGWD(x)				(((x) >> BIT_SHIFT_IPS_CFGWD) & BIT_MASK_IPS_CFGWD)
#define BIT_SET_IPS_CFGWD(x, v)			(BIT_CLEAR_IPS_CFGWD(x) | BIT_IPS_CFGWD(v))

#define BIT_SHIFT_MACREG_READ_BIST_RPT			0
#define BIT_MASK_MACREG_READ_BIST_RPT			0xffffffffL
#define BIT_MACREG_READ_BIST_RPT(x)			(((x) & BIT_MASK_MACREG_READ_BIST_RPT) << BIT_SHIFT_MACREG_READ_BIST_RPT)
#define BITS_MACREG_READ_BIST_RPT			(BIT_MASK_MACREG_READ_BIST_RPT << BIT_SHIFT_MACREG_READ_BIST_RPT)
#define BIT_CLEAR_MACREG_READ_BIST_RPT(x)		((x) & (~BITS_MACREG_READ_BIST_RPT))
#define BIT_GET_MACREG_READ_BIST_RPT(x)		(((x) >> BIT_SHIFT_MACREG_READ_BIST_RPT) & BIT_MASK_MACREG_READ_BIST_RPT)
#define BIT_SET_MACREG_READ_BIST_RPT(x, v)		(BIT_CLEAR_MACREG_READ_BIST_RPT(x) | BIT_MACREG_READ_BIST_RPT(v))

/* 2 REG_MACCLKFRQ				(Offset 0x018C) */

#define BIT_SHIFT_MACCLK_FREQ_L32			0
#define BIT_MASK_MACCLK_FREQ_L32			0xffffffffL
#define BIT_MACCLK_FREQ_L32(x)				(((x) & BIT_MASK_MACCLK_FREQ_L32) << BIT_SHIFT_MACCLK_FREQ_L32)
#define BITS_MACCLK_FREQ_L32				(BIT_MASK_MACCLK_FREQ_L32 << BIT_SHIFT_MACCLK_FREQ_L32)
#define BIT_CLEAR_MACCLK_FREQ_L32(x)			((x) & (~BITS_MACCLK_FREQ_L32))
#define BIT_GET_MACCLK_FREQ_L32(x)			(((x) >> BIT_SHIFT_MACCLK_FREQ_L32) & BIT_MASK_MACCLK_FREQ_L32)
#define BIT_SET_MACCLK_FREQ_L32(x, v)			(BIT_CLEAR_MACCLK_FREQ_L32(x) | BIT_MACCLK_FREQ_L32(v))

/* 2 REG_TMETER				(Offset 0x0190) */

#define BIT_SHIFT_NCO_OUTCLK_FRQ			12
#define BIT_MASK_NCO_OUTCLK_FRQ			0xfffff
#define BIT_NCO_OUTCLK_FRQ(x)				(((x) & BIT_MASK_NCO_OUTCLK_FRQ) << BIT_SHIFT_NCO_OUTCLK_FRQ)
#define BITS_NCO_OUTCLK_FRQ				(BIT_MASK_NCO_OUTCLK_FRQ << BIT_SHIFT_NCO_OUTCLK_FRQ)
#define BIT_CLEAR_NCO_OUTCLK_FRQ(x)			((x) & (~BITS_NCO_OUTCLK_FRQ))
#define BIT_GET_NCO_OUTCLK_FRQ(x)			(((x) >> BIT_SHIFT_NCO_OUTCLK_FRQ) & BIT_MASK_NCO_OUTCLK_FRQ)
#define BIT_SET_NCO_OUTCLK_FRQ(x, v)			(BIT_CLEAR_NCO_OUTCLK_FRQ(x) | BIT_NCO_OUTCLK_FRQ(v))

#define BIT_SHIFT_MACCLK_FRQ_HIGH10			0
#define BIT_MASK_MACCLK_FRQ_HIGH10			0x3ff
#define BIT_MACCLK_FRQ_HIGH10(x)			(((x) & BIT_MASK_MACCLK_FRQ_HIGH10) << BIT_SHIFT_MACCLK_FRQ_HIGH10)
#define BITS_MACCLK_FRQ_HIGH10				(BIT_MASK_MACCLK_FRQ_HIGH10 << BIT_SHIFT_MACCLK_FRQ_HIGH10)
#define BIT_CLEAR_MACCLK_FRQ_HIGH10(x)			((x) & (~BITS_MACCLK_FRQ_HIGH10))
#define BIT_GET_MACCLK_FRQ_HIGH10(x)			(((x) >> BIT_SHIFT_MACCLK_FRQ_HIGH10) & BIT_MASK_MACCLK_FRQ_HIGH10)
#define BIT_SET_MACCLK_FRQ_HIGH10(x, v)		(BIT_CLEAR_MACCLK_FRQ_HIGH10(x) | BIT_MACCLK_FRQ_HIGH10(v))

/* 2 REG_OSC_32K_CTRL			(Offset 0x0194) */

#define BIT_RDY_32K_CLK				BIT(12)

#define BIT_SHIFT_MONITOR_CYCLE_LOG2			8
#define BIT_MASK_MONITOR_CYCLE_LOG2			0xf
#define BIT_MONITOR_CYCLE_LOG2(x)			(((x) & BIT_MASK_MONITOR_CYCLE_LOG2) << BIT_SHIFT_MONITOR_CYCLE_LOG2)
#define BITS_MONITOR_CYCLE_LOG2			(BIT_MASK_MONITOR_CYCLE_LOG2 << BIT_SHIFT_MONITOR_CYCLE_LOG2)
#define BIT_CLEAR_MONITOR_CYCLE_LOG2(x)		((x) & (~BITS_MONITOR_CYCLE_LOG2))
#define BIT_GET_MONITOR_CYCLE_LOG2(x)			(((x) >> BIT_SHIFT_MONITOR_CYCLE_LOG2) & BIT_MASK_MONITOR_CYCLE_LOG2)
#define BIT_SET_MONITOR_CYCLE_LOG2(x, v)		(BIT_CLEAR_MONITOR_CYCLE_LOG2(x) | BIT_MONITOR_CYCLE_LOG2(v))

/* 2 REG_32K_CAL_REG0			(Offset 0x0198) */

#define BIT_SHIFT_FREQ_UNREGCLK			8
#define BIT_MASK_FREQ_UNREGCLK				0xffffff
#define BIT_FREQ_UNREGCLK(x)				(((x) & BIT_MASK_FREQ_UNREGCLK) << BIT_SHIFT_FREQ_UNREGCLK)
#define BITS_FREQ_UNREGCLK				(BIT_MASK_FREQ_UNREGCLK << BIT_SHIFT_FREQ_UNREGCLK)
#define BIT_CLEAR_FREQ_UNREGCLK(x)			((x) & (~BITS_FREQ_UNREGCLK))
#define BIT_GET_FREQ_UNREGCLK(x)			(((x) >> BIT_SHIFT_FREQ_UNREGCLK) & BIT_MASK_FREQ_UNREGCLK)
#define BIT_SET_FREQ_UNREGCLK(x, v)			(BIT_CLEAR_FREQ_UNREGCLK(x) | BIT_FREQ_UNREGCLK(v))

#define BIT_CAL32K_DBGMOD				BIT(7)

#define BIT_SHIFT_NCO_THRS				0
#define BIT_MASK_NCO_THRS				0x7f
#define BIT_NCO_THRS(x)				(((x) & BIT_MASK_NCO_THRS) << BIT_SHIFT_NCO_THRS)
#define BITS_NCO_THRS					(BIT_MASK_NCO_THRS << BIT_SHIFT_NCO_THRS)
#define BIT_CLEAR_NCO_THRS(x)				((x) & (~BITS_NCO_THRS))
#define BIT_GET_NCO_THRS(x)				(((x) >> BIT_SHIFT_NCO_THRS) & BIT_MASK_NCO_THRS)
#define BIT_SET_NCO_THRS(x, v)				(BIT_CLEAR_NCO_THRS(x) | BIT_NCO_THRS(v))

/* 2 REG_32K_XTAL_CR				(Offset 0x019C) */

#define BIT_SHIFT_XTAL_DIV_FREQ			0
#define BIT_MASK_XTAL_DIV_FREQ				0xffff
#define BIT_XTAL_DIV_FREQ(x)				(((x) & BIT_MASK_XTAL_DIV_FREQ) << BIT_SHIFT_XTAL_DIV_FREQ)
#define BITS_XTAL_DIV_FREQ				(BIT_MASK_XTAL_DIV_FREQ << BIT_SHIFT_XTAL_DIV_FREQ)
#define BIT_CLEAR_XTAL_DIV_FREQ(x)			((x) & (~BITS_XTAL_DIV_FREQ))
#define BIT_GET_XTAL_DIV_FREQ(x)			(((x) >> BIT_SHIFT_XTAL_DIV_FREQ) & BIT_MASK_XTAL_DIV_FREQ)
#define BIT_SET_XTAL_DIV_FREQ(x, v)			(BIT_CLEAR_XTAL_DIV_FREQ(x) | BIT_XTAL_DIV_FREQ(v))

/* 2 REG_C2HEVT				(Offset 0x01A0) */

#define BIT_SHIFT_C2HEVT_MSG_V1			0
#define BIT_MASK_C2HEVT_MSG_V1				0xffffffffL
#define BIT_C2HEVT_MSG_V1(x)				(((x) & BIT_MASK_C2HEVT_MSG_V1) << BIT_SHIFT_C2HEVT_MSG_V1)
#define BITS_C2HEVT_MSG_V1				(BIT_MASK_C2HEVT_MSG_V1 << BIT_SHIFT_C2HEVT_MSG_V1)
#define BIT_CLEAR_C2HEVT_MSG_V1(x)			((x) & (~BITS_C2HEVT_MSG_V1))
#define BIT_GET_C2HEVT_MSG_V1(x)			(((x) >> BIT_SHIFT_C2HEVT_MSG_V1) & BIT_MASK_C2HEVT_MSG_V1)
#define BIT_SET_C2HEVT_MSG_V1(x, v)			(BIT_CLEAR_C2HEVT_MSG_V1(x) | BIT_C2HEVT_MSG_V1(v))

/* 2 REG_C2HEVT_1				(Offset 0x01A4) */

#define BIT_SHIFT_C2HEVT_MSG_1				0
#define BIT_MASK_C2HEVT_MSG_1				0xffffffffL
#define BIT_C2HEVT_MSG_1(x)				(((x) & BIT_MASK_C2HEVT_MSG_1) << BIT_SHIFT_C2HEVT_MSG_1)
#define BITS_C2HEVT_MSG_1				(BIT_MASK_C2HEVT_MSG_1 << BIT_SHIFT_C2HEVT_MSG_1)
#define BIT_CLEAR_C2HEVT_MSG_1(x)			((x) & (~BITS_C2HEVT_MSG_1))
#define BIT_GET_C2HEVT_MSG_1(x)			(((x) >> BIT_SHIFT_C2HEVT_MSG_1) & BIT_MASK_C2HEVT_MSG_1)
#define BIT_SET_C2HEVT_MSG_1(x, v)			(BIT_CLEAR_C2HEVT_MSG_1(x) | BIT_C2HEVT_MSG_1(v))

/* 2 REG_C2HEVT_2				(Offset 0x01A8) */

#define BIT_SHIFT_C2HEVT_MSG_2				0
#define BIT_MASK_C2HEVT_MSG_2				0xffffffffL
#define BIT_C2HEVT_MSG_2(x)				(((x) & BIT_MASK_C2HEVT_MSG_2) << BIT_SHIFT_C2HEVT_MSG_2)
#define BITS_C2HEVT_MSG_2				(BIT_MASK_C2HEVT_MSG_2 << BIT_SHIFT_C2HEVT_MSG_2)
#define BIT_CLEAR_C2HEVT_MSG_2(x)			((x) & (~BITS_C2HEVT_MSG_2))
#define BIT_GET_C2HEVT_MSG_2(x)			(((x) >> BIT_SHIFT_C2HEVT_MSG_2) & BIT_MASK_C2HEVT_MSG_2)
#define BIT_SET_C2HEVT_MSG_2(x, v)			(BIT_CLEAR_C2HEVT_MSG_2(x) | BIT_C2HEVT_MSG_2(v))

/* 2 REG_C2HEVT_3				(Offset 0x01AC) */

#define BIT_SHIFT_C2HEVT_MSG_3				0
#define BIT_MASK_C2HEVT_MSG_3				0xffffffffL
#define BIT_C2HEVT_MSG_3(x)				(((x) & BIT_MASK_C2HEVT_MSG_3) << BIT_SHIFT_C2HEVT_MSG_3)
#define BITS_C2HEVT_MSG_3				(BIT_MASK_C2HEVT_MSG_3 << BIT_SHIFT_C2HEVT_MSG_3)
#define BIT_CLEAR_C2HEVT_MSG_3(x)			((x) & (~BITS_C2HEVT_MSG_3))
#define BIT_GET_C2HEVT_MSG_3(x)			(((x) >> BIT_SHIFT_C2HEVT_MSG_3) & BIT_MASK_C2HEVT_MSG_3)
#define BIT_SET_C2HEVT_MSG_3(x, v)			(BIT_CLEAR_C2HEVT_MSG_3(x) | BIT_C2HEVT_MSG_3(v))

/* 2 REG_HW_IOE_CR				(Offset 0x01B0) */

#define BIT_HIOE_ACTIVE				BIT(31)
#define BIT_HIOE_RESTORE_REQ				BIT(25)
#define BIT_HIOE_BACKUP_REQ				BIT(24)

#define BIT_SHIFT_HIOE_END_ADDR			12
#define BIT_MASK_HIOE_END_ADDR				0xfff
#define BIT_HIOE_END_ADDR(x)				(((x) & BIT_MASK_HIOE_END_ADDR) << BIT_SHIFT_HIOE_END_ADDR)
#define BITS_HIOE_END_ADDR				(BIT_MASK_HIOE_END_ADDR << BIT_SHIFT_HIOE_END_ADDR)
#define BIT_CLEAR_HIOE_END_ADDR(x)			((x) & (~BITS_HIOE_END_ADDR))
#define BIT_GET_HIOE_END_ADDR(x)			(((x) >> BIT_SHIFT_HIOE_END_ADDR) & BIT_MASK_HIOE_END_ADDR)
#define BIT_SET_HIOE_END_ADDR(x, v)			(BIT_CLEAR_HIOE_END_ADDR(x) | BIT_HIOE_END_ADDR(v))

#define BIT_SHIFT_HIOE_STR_ADDR			0
#define BIT_MASK_HIOE_STR_ADDR				0xfff
#define BIT_HIOE_STR_ADDR(x)				(((x) & BIT_MASK_HIOE_STR_ADDR) << BIT_SHIFT_HIOE_STR_ADDR)
#define BITS_HIOE_STR_ADDR				(BIT_MASK_HIOE_STR_ADDR << BIT_SHIFT_HIOE_STR_ADDR)
#define BIT_CLEAR_HIOE_STR_ADDR(x)			((x) & (~BITS_HIOE_STR_ADDR))
#define BIT_GET_HIOE_STR_ADDR(x)			(((x) >> BIT_SHIFT_HIOE_STR_ADDR) & BIT_MASK_HIOE_STR_ADDR)
#define BIT_SET_HIOE_STR_ADDR(x, v)			(BIT_CLEAR_HIOE_STR_ADDR(x) | BIT_HIOE_STR_ADDR(v))

/* 2 REG_BB_RFC_ATR				(Offset 0x01B4) */

#define BIT_SHIFT_PHYRE_CNT				25
#define BIT_MASK_PHYRE_CNT				0xf
#define BIT_PHYRE_CNT(x)				(((x) & BIT_MASK_PHYRE_CNT) << BIT_SHIFT_PHYRE_CNT)
#define BITS_PHYRE_CNT					(BIT_MASK_PHYRE_CNT << BIT_SHIFT_PHYRE_CNT)
#define BIT_CLEAR_PHYRE_CNT(x)				((x) & (~BITS_PHYRE_CNT))
#define BIT_GET_PHYRE_CNT(x)				(((x) >> BIT_SHIFT_PHYRE_CNT) & BIT_MASK_PHYRE_CNT)
#define BIT_SET_PHYRE_CNT(x, v)			(BIT_CLEAR_PHYRE_CNT(x) | BIT_PHYRE_CNT(v))

#define BIT_SHIFT_TXBUF_WKCAM_OFFSET			12
#define BIT_MASK_TXBUF_WKCAM_OFFSET			0x1fff
#define BIT_TXBUF_WKCAM_OFFSET(x)			(((x) & BIT_MASK_TXBUF_WKCAM_OFFSET) << BIT_SHIFT_TXBUF_WKCAM_OFFSET)
#define BITS_TXBUF_WKCAM_OFFSET			(BIT_MASK_TXBUF_WKCAM_OFFSET << BIT_SHIFT_TXBUF_WKCAM_OFFSET)
#define BIT_CLEAR_TXBUF_WKCAM_OFFSET(x)		((x) & (~BITS_TXBUF_WKCAM_OFFSET))
#define BIT_GET_TXBUF_WKCAM_OFFSET(x)			(((x) >> BIT_SHIFT_TXBUF_WKCAM_OFFSET) & BIT_MASK_TXBUF_WKCAM_OFFSET)
#define BIT_SET_TXBUF_WKCAM_OFFSET(x, v)		(BIT_CLEAR_TXBUF_WKCAM_OFFSET(x) | BIT_TXBUF_WKCAM_OFFSET(v))

#define BIT_SHIFT_PHYRD_WAIT_CNT			8
#define BIT_MASK_PHYRD_WAIT_CNT			0xf
#define BIT_PHYRD_WAIT_CNT(x)				(((x) & BIT_MASK_PHYRD_WAIT_CNT) << BIT_SHIFT_PHYRD_WAIT_CNT)
#define BITS_PHYRD_WAIT_CNT				(BIT_MASK_PHYRD_WAIT_CNT << BIT_SHIFT_PHYRD_WAIT_CNT)
#define BIT_CLEAR_PHYRD_WAIT_CNT(x)			((x) & (~BITS_PHYRD_WAIT_CNT))
#define BIT_GET_PHYRD_WAIT_CNT(x)			(((x) >> BIT_SHIFT_PHYRD_WAIT_CNT) & BIT_MASK_PHYRD_WAIT_CNT)
#define BIT_SET_PHYRD_WAIT_CNT(x, v)			(BIT_CLEAR_PHYRD_WAIT_CNT(x) | BIT_PHYRD_WAIT_CNT(v))

#define BIT_SHIFT_PHYWR_HOLD_CNT			4
#define BIT_MASK_PHYWR_HOLD_CNT			0xf
#define BIT_PHYWR_HOLD_CNT(x)				(((x) & BIT_MASK_PHYWR_HOLD_CNT) << BIT_SHIFT_PHYWR_HOLD_CNT)
#define BITS_PHYWR_HOLD_CNT				(BIT_MASK_PHYWR_HOLD_CNT << BIT_SHIFT_PHYWR_HOLD_CNT)
#define BIT_CLEAR_PHYWR_HOLD_CNT(x)			((x) & (~BITS_PHYWR_HOLD_CNT))
#define BIT_GET_PHYWR_HOLD_CNT(x)			(((x) >> BIT_SHIFT_PHYWR_HOLD_CNT) & BIT_MASK_PHYWR_HOLD_CNT)
#define BIT_SET_PHYWR_HOLD_CNT(x, v)			(BIT_CLEAR_PHYWR_HOLD_CNT(x) | BIT_PHYWR_HOLD_CNT(v))

#define BIT_SHIFT_PHYWR_SETUP_CNT			0
#define BIT_MASK_PHYWR_SETUP_CNT			0xf
#define BIT_PHYWR_SETUP_CNT(x)				(((x) & BIT_MASK_PHYWR_SETUP_CNT) << BIT_SHIFT_PHYWR_SETUP_CNT)
#define BITS_PHYWR_SETUP_CNT				(BIT_MASK_PHYWR_SETUP_CNT << BIT_SHIFT_PHYWR_SETUP_CNT)
#define BIT_CLEAR_PHYWR_SETUP_CNT(x)			((x) & (~BITS_PHYWR_SETUP_CNT))
#define BIT_GET_PHYWR_SETUP_CNT(x)			(((x) >> BIT_SHIFT_PHYWR_SETUP_CNT) & BIT_MASK_PHYWR_SETUP_CNT)
#define BIT_SET_PHYWR_SETUP_CNT(x, v)			(BIT_CLEAR_PHYWR_SETUP_CNT(x) | BIT_PHYWR_SETUP_CNT(v))

/* 2 REG_SW_DEFINED_PAGE1			(Offset 0x01B8) */

#define BIT_SHIFT_SW_DEFINED_PAGE1_V1			0
#define BIT_MASK_SW_DEFINED_PAGE1_V1			0xffffffffL
#define BIT_SW_DEFINED_PAGE1_V1(x)			(((x) & BIT_MASK_SW_DEFINED_PAGE1_V1) << BIT_SHIFT_SW_DEFINED_PAGE1_V1)
#define BITS_SW_DEFINED_PAGE1_V1			(BIT_MASK_SW_DEFINED_PAGE1_V1 << BIT_SHIFT_SW_DEFINED_PAGE1_V1)
#define BIT_CLEAR_SW_DEFINED_PAGE1_V1(x)		((x) & (~BITS_SW_DEFINED_PAGE1_V1))
#define BIT_GET_SW_DEFINED_PAGE1_V1(x)			(((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1) & BIT_MASK_SW_DEFINED_PAGE1_V1)
#define BIT_SET_SW_DEFINED_PAGE1_V1(x, v)		(BIT_CLEAR_SW_DEFINED_PAGE1_V1(x) | BIT_SW_DEFINED_PAGE1_V1(v))

/* 2 REG_SW_DEFINED_PAGE2			(Offset 0x01BC) */

#define BIT_SHIFT_SW_DEFINED_PAGE2			0
#define BIT_MASK_SW_DEFINED_PAGE2			0xffffffffL
#define BIT_SW_DEFINED_PAGE2(x)			(((x) & BIT_MASK_SW_DEFINED_PAGE2) << BIT_SHIFT_SW_DEFINED_PAGE2)
#define BITS_SW_DEFINED_PAGE2				(BIT_MASK_SW_DEFINED_PAGE2 << BIT_SHIFT_SW_DEFINED_PAGE2)
#define BIT_CLEAR_SW_DEFINED_PAGE2(x)			((x) & (~BITS_SW_DEFINED_PAGE2))
#define BIT_GET_SW_DEFINED_PAGE2(x)			(((x) >> BIT_SHIFT_SW_DEFINED_PAGE2) & BIT_MASK_SW_DEFINED_PAGE2)
#define BIT_SET_SW_DEFINED_PAGE2(x, v)			(BIT_CLEAR_SW_DEFINED_PAGE2(x) | BIT_SW_DEFINED_PAGE2(v))

/* 2 REG_MCUTST_I				(Offset 0x01C0) */

#define BIT_SHIFT_MCUDMSG_I				0
#define BIT_MASK_MCUDMSG_I				0xffffffffL
#define BIT_MCUDMSG_I(x)				(((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I)
#define BITS_MCUDMSG_I					(BIT_MASK_MCUDMSG_I << BIT_SHIFT_MCUDMSG_I)
#define BIT_CLEAR_MCUDMSG_I(x)				((x) & (~BITS_MCUDMSG_I))
#define BIT_GET_MCUDMSG_I(x)				(((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I)
#define BIT_SET_MCUDMSG_I(x, v)			(BIT_CLEAR_MCUDMSG_I(x) | BIT_MCUDMSG_I(v))

/* 2 REG_MCUTST_II				(Offset 0x01C4) */

#define BIT_SHIFT_MCUDMSG_II				0
#define BIT_MASK_MCUDMSG_II				0xffffffffL
#define BIT_MCUDMSG_II(x)				(((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II)
#define BITS_MCUDMSG_II				(BIT_MASK_MCUDMSG_II << BIT_SHIFT_MCUDMSG_II)
#define BIT_CLEAR_MCUDMSG_II(x)			((x) & (~BITS_MCUDMSG_II))
#define BIT_GET_MCUDMSG_II(x)				(((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II)
#define BIT_SET_MCUDMSG_II(x, v)			(BIT_CLEAR_MCUDMSG_II(x) | BIT_MCUDMSG_II(v))

/* 2 REG_FMETHR				(Offset 0x01C8) */

#define BIT_FWMSG_INTPS				BIT(31)

#define BIT_SHIFT_FW_MSG				0
#define BIT_MASK_FW_MSG				0xffffffffL
#define BIT_FW_MSG(x)					(((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG)
#define BITS_FW_MSG					(BIT_MASK_FW_MSG << BIT_SHIFT_FW_MSG)
#define BIT_CLEAR_FW_MSG(x)				((x) & (~BITS_FW_MSG))
#define BIT_GET_FW_MSG(x)				(((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG)
#define BIT_SET_FW_MSG(x, v)				(BIT_CLEAR_FW_MSG(x) | BIT_FW_MSG(v))

/* 2 REG_HMETFR				(Offset 0x01CC) */

#define BIT_SHIFT_HRCV_MSG				24
#define BIT_MASK_HRCV_MSG				0xff
#define BIT_HRCV_MSG(x)				(((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG)
#define BITS_HRCV_MSG					(BIT_MASK_HRCV_MSG << BIT_SHIFT_HRCV_MSG)
#define BIT_CLEAR_HRCV_MSG(x)				((x) & (~BITS_HRCV_MSG))
#define BIT_GET_HRCV_MSG(x)				(((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG)
#define BIT_SET_HRCV_MSG(x, v)				(BIT_CLEAR_HRCV_MSG(x) | BIT_HRCV_MSG(v))

#define BIT_H3MSG_VLD					BIT(3)
#define BIT_H2MSG_VLD					BIT(2)
#define BIT_H1MSG_VLD					BIT(1)
#define BIT_H0MSG_VLD					BIT(0)

/* 2 REG_HMEBOX0				(Offset 0x01D0) */

#define BIT_SHIFT_HOST_MSG_0				0
#define BIT_MASK_HOST_MSG_0				0xffffffffL
#define BIT_HOST_MSG_0(x)				(((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0)
#define BITS_HOST_MSG_0				(BIT_MASK_HOST_MSG_0 << BIT_SHIFT_HOST_MSG_0)
#define BIT_CLEAR_HOST_MSG_0(x)			((x) & (~BITS_HOST_MSG_0))
#define BIT_GET_HOST_MSG_0(x)				(((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0)
#define BIT_SET_HOST_MSG_0(x, v)			(BIT_CLEAR_HOST_MSG_0(x) | BIT_HOST_MSG_0(v))

/* 2 REG_HMEBOX1				(Offset 0x01D4) */

#define BIT_SHIFT_HOST_MSG_1				0
#define BIT_MASK_HOST_MSG_1				0xffffffffL
#define BIT_HOST_MSG_1(x)				(((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1)
#define BITS_HOST_MSG_1				(BIT_MASK_HOST_MSG_1 << BIT_SHIFT_HOST_MSG_1)
#define BIT_CLEAR_HOST_MSG_1(x)			((x) & (~BITS_HOST_MSG_1))
#define BIT_GET_HOST_MSG_1(x)				(((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1)
#define BIT_SET_HOST_MSG_1(x, v)			(BIT_CLEAR_HOST_MSG_1(x) | BIT_HOST_MSG_1(v))

/* 2 REG_HMEBOX2				(Offset 0x01D8) */

#define BIT_SHIFT_HOST_MSG_2				0
#define BIT_MASK_HOST_MSG_2				0xffffffffL
#define BIT_HOST_MSG_2(x)				(((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2)
#define BITS_HOST_MSG_2				(BIT_MASK_HOST_MSG_2 << BIT_SHIFT_HOST_MSG_2)
#define BIT_CLEAR_HOST_MSG_2(x)			((x) & (~BITS_HOST_MSG_2))
#define BIT_GET_HOST_MSG_2(x)				(((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2)
#define BIT_SET_HOST_MSG_2(x, v)			(BIT_CLEAR_HOST_MSG_2(x) | BIT_HOST_MSG_2(v))

/* 2 REG_HMEBOX3				(Offset 0x01DC) */

#define BIT_SHIFT_HOST_MSG_3				0
#define BIT_MASK_HOST_MSG_3				0xffffffffL
#define BIT_HOST_MSG_3(x)				(((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3)
#define BITS_HOST_MSG_3				(BIT_MASK_HOST_MSG_3 << BIT_SHIFT_HOST_MSG_3)
#define BIT_CLEAR_HOST_MSG_3(x)			((x) & (~BITS_HOST_MSG_3))
#define BIT_GET_HOST_MSG_3(x)				(((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3)
#define BIT_SET_HOST_MSG_3(x, v)			(BIT_CLEAR_HOST_MSG_3(x) | BIT_HOST_MSG_3(v))

/* 2 REG_LLT_IND_ACCESS			(Offset 0x01E0) */

#define BIT_SHIFT_LLTE_RWM				30
#define BIT_MASK_LLTE_RWM				0x3
#define BIT_LLTE_RWM(x)				(((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM)
#define BITS_LLTE_RWM					(BIT_MASK_LLTE_RWM << BIT_SHIFT_LLTE_RWM)
#define BIT_CLEAR_LLTE_RWM(x)				((x) & (~BITS_LLTE_RWM))
#define BIT_GET_LLTE_RWM(x)				(((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM)
#define BIT_SET_LLTE_RWM(x, v)				(BIT_CLEAR_LLTE_RWM(x) | BIT_LLTE_RWM(v))

#define BIT_SHIFT_LLTINI_PWM_RDATA			16
#define BIT_MASK_LLTINI_PWM_RDATA			0xff
#define BIT_LLTINI_PWM_RDATA(x)			(((x) & BIT_MASK_LLTINI_PWM_RDATA) << BIT_SHIFT_LLTINI_PWM_RDATA)
#define BITS_LLTINI_PWM_RDATA				(BIT_MASK_LLTINI_PWM_RDATA << BIT_SHIFT_LLTINI_PWM_RDATA)
#define BIT_CLEAR_LLTINI_PWM_RDATA(x)			((x) & (~BITS_LLTINI_PWM_RDATA))
#define BIT_GET_LLTINI_PWM_RDATA(x)			(((x) >> BIT_SHIFT_LLTINI_PWM_RDATA) & BIT_MASK_LLTINI_PWM_RDATA)
#define BIT_SET_LLTINI_PWM_RDATA(x, v)			(BIT_CLEAR_LLTINI_PWM_RDATA(x) | BIT_LLTINI_PWM_RDATA(v))

#define BIT_SHIFT_LLTINI_ADDR				8
#define BIT_MASK_LLTINI_ADDR				0xff
#define BIT_LLTINI_ADDR(x)				(((x) & BIT_MASK_LLTINI_ADDR) << BIT_SHIFT_LLTINI_ADDR)
#define BITS_LLTINI_ADDR				(BIT_MASK_LLTINI_ADDR << BIT_SHIFT_LLTINI_ADDR)
#define BIT_CLEAR_LLTINI_ADDR(x)			((x) & (~BITS_LLTINI_ADDR))
#define BIT_GET_LLTINI_ADDR(x)				(((x) >> BIT_SHIFT_LLTINI_ADDR) & BIT_MASK_LLTINI_ADDR)
#define BIT_SET_LLTINI_ADDR(x, v)			(BIT_CLEAR_LLTINI_ADDR(x) | BIT_LLTINI_ADDR(v))

#define BIT_SHIFT_LLTINI_HCI_RDATA			0
#define BIT_MASK_LLTINI_HCI_RDATA			0xff
#define BIT_LLTINI_HCI_RDATA(x)			(((x) & BIT_MASK_LLTINI_HCI_RDATA) << BIT_SHIFT_LLTINI_HCI_RDATA)
#define BITS_LLTINI_HCI_RDATA				(BIT_MASK_LLTINI_HCI_RDATA << BIT_SHIFT_LLTINI_HCI_RDATA)
#define BIT_CLEAR_LLTINI_HCI_RDATA(x)			((x) & (~BITS_LLTINI_HCI_RDATA))
#define BIT_GET_LLTINI_HCI_RDATA(x)			(((x) >> BIT_SHIFT_LLTINI_HCI_RDATA) & BIT_MASK_LLTINI_HCI_RDATA)
#define BIT_SET_LLTINI_HCI_RDATA(x, v)			(BIT_CLEAR_LLTINI_HCI_RDATA(x) | BIT_LLTINI_HCI_RDATA(v))

/* 2 REG_GENTST				(Offset 0x01E4) */

#define BIT_SHIFT_GENTST				0
#define BIT_MASK_GENTST				0xffffffffL
#define BIT_GENTST(x)					(((x) & BIT_MASK_GENTST) << BIT_SHIFT_GENTST)
#define BITS_GENTST					(BIT_MASK_GENTST << BIT_SHIFT_GENTST)
#define BIT_CLEAR_GENTST(x)				((x) & (~BITS_GENTST))
#define BIT_GET_GENTST(x)				(((x) >> BIT_SHIFT_GENTST) & BIT_MASK_GENTST)
#define BIT_SET_GENTST(x, v)				(BIT_CLEAR_GENTST(x) | BIT_GENTST(v))

/* 2 REG_BB_ACCESS_CTRL			(Offset 0x01E8) */

#define BIT_SHIFT_BB_WRITE_READ			30
#define BIT_MASK_BB_WRITE_READ				0x3
#define BIT_BB_WRITE_READ(x)				(((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ)
#define BITS_BB_WRITE_READ				(BIT_MASK_BB_WRITE_READ << BIT_SHIFT_BB_WRITE_READ)
#define BIT_CLEAR_BB_WRITE_READ(x)			((x) & (~BITS_BB_WRITE_READ))
#define BIT_GET_BB_WRITE_READ(x)			(((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ)
#define BIT_SET_BB_WRITE_READ(x, v)			(BIT_CLEAR_BB_WRITE_READ(x) | BIT_BB_WRITE_READ(v))

#define BIT_SHIFT_BB_WRITE_EN_V1			16
#define BIT_MASK_BB_WRITE_EN_V1			0xf
#define BIT_BB_WRITE_EN_V1(x)				(((x) & BIT_MASK_BB_WRITE_EN_V1) << BIT_SHIFT_BB_WRITE_EN_V1)
#define BITS_BB_WRITE_EN_V1				(BIT_MASK_BB_WRITE_EN_V1 << BIT_SHIFT_BB_WRITE_EN_V1)
#define BIT_CLEAR_BB_WRITE_EN_V1(x)			((x) & (~BITS_BB_WRITE_EN_V1))
#define BIT_GET_BB_WRITE_EN_V1(x)			(((x) >> BIT_SHIFT_BB_WRITE_EN_V1) & BIT_MASK_BB_WRITE_EN_V1)
#define BIT_SET_BB_WRITE_EN_V1(x, v)			(BIT_CLEAR_BB_WRITE_EN_V1(x) | BIT_BB_WRITE_EN_V1(v))

#define BIT_SHIFT_BB_ADDR_V1				2
#define BIT_MASK_BB_ADDR_V1				0x1fff
#define BIT_BB_ADDR_V1(x)				(((x) & BIT_MASK_BB_ADDR_V1) << BIT_SHIFT_BB_ADDR_V1)
#define BITS_BB_ADDR_V1				(BIT_MASK_BB_ADDR_V1 << BIT_SHIFT_BB_ADDR_V1)
#define BIT_CLEAR_BB_ADDR_V1(x)			((x) & (~BITS_BB_ADDR_V1))
#define BIT_GET_BB_ADDR_V1(x)				(((x) >> BIT_SHIFT_BB_ADDR_V1) & BIT_MASK_BB_ADDR_V1)
#define BIT_SET_BB_ADDR_V1(x, v)			(BIT_CLEAR_BB_ADDR_V1(x) | BIT_BB_ADDR_V1(v))

#define BIT_BB_ERRACC					BIT(0)

/* 2 REG_BB_ACCESS_DATA			(Offset 0x01EC) */

#define BIT_SHIFT_BB_DATA				0
#define BIT_MASK_BB_DATA				0xffffffffL
#define BIT_BB_DATA(x)					(((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA)
#define BITS_BB_DATA					(BIT_MASK_BB_DATA << BIT_SHIFT_BB_DATA)
#define BIT_CLEAR_BB_DATA(x)				((x) & (~BITS_BB_DATA))
#define BIT_GET_BB_DATA(x)				(((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA)
#define BIT_SET_BB_DATA(x, v)				(BIT_CLEAR_BB_DATA(x) | BIT_BB_DATA(v))

/* 2 REG_HMEBOX_E0				(Offset 0x01F0) */

#define BIT_SHIFT_HMEBOX_E0				0
#define BIT_MASK_HMEBOX_E0				0xffffffffL
#define BIT_HMEBOX_E0(x)				(((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0)
#define BITS_HMEBOX_E0					(BIT_MASK_HMEBOX_E0 << BIT_SHIFT_HMEBOX_E0)
#define BIT_CLEAR_HMEBOX_E0(x)				((x) & (~BITS_HMEBOX_E0))
#define BIT_GET_HMEBOX_E0(x)				(((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0)
#define BIT_SET_HMEBOX_E0(x, v)			(BIT_CLEAR_HMEBOX_E0(x) | BIT_HMEBOX_E0(v))

/* 2 REG_HMEBOX_E1				(Offset 0x01F4) */

#define BIT_SHIFT_HMEBOX_E1				0
#define BIT_MASK_HMEBOX_E1				0xffffffffL
#define BIT_HMEBOX_E1(x)				(((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1)
#define BITS_HMEBOX_E1					(BIT_MASK_HMEBOX_E1 << BIT_SHIFT_HMEBOX_E1)
#define BIT_CLEAR_HMEBOX_E1(x)				((x) & (~BITS_HMEBOX_E1))
#define BIT_GET_HMEBOX_E1(x)				(((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1)
#define BIT_SET_HMEBOX_E1(x, v)			(BIT_CLEAR_HMEBOX_E1(x) | BIT_HMEBOX_E1(v))

/* 2 REG_HMEBOX_E2				(Offset 0x01F8) */

#define BIT_SHIFT_HMEBOX_E2				0
#define BIT_MASK_HMEBOX_E2				0xffffffffL
#define BIT_HMEBOX_E2(x)				(((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2)
#define BITS_HMEBOX_E2					(BIT_MASK_HMEBOX_E2 << BIT_SHIFT_HMEBOX_E2)
#define BIT_CLEAR_HMEBOX_E2(x)				((x) & (~BITS_HMEBOX_E2))
#define BIT_GET_HMEBOX_E2(x)				(((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2)
#define BIT_SET_HMEBOX_E2(x, v)			(BIT_CLEAR_HMEBOX_E2(x) | BIT_HMEBOX_E2(v))

/* 2 REG_HMEBOX_E3				(Offset 0x01FC) */

#define BIT_SHIFT_HMEBOX_E3				0
#define BIT_MASK_HMEBOX_E3				0xffffffffL
#define BIT_HMEBOX_E3(x)				(((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3)
#define BITS_HMEBOX_E3					(BIT_MASK_HMEBOX_E3 << BIT_SHIFT_HMEBOX_E3)
#define BIT_CLEAR_HMEBOX_E3(x)				((x) & (~BITS_HMEBOX_E3))
#define BIT_GET_HMEBOX_E3(x)				(((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3)
#define BIT_SET_HMEBOX_E3(x, v)			(BIT_CLEAR_HMEBOX_E3(x) | BIT_HMEBOX_E3(v))

/* 2 REG_FIFOPAGE_INFO			(Offset 0x0204) */

#define BIT_SHIFT_TXPKTNUM				24
#define BIT_MASK_TXPKTNUM				0xff
#define BIT_TXPKTNUM(x)				(((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
#define BITS_TXPKTNUM					(BIT_MASK_TXPKTNUM << BIT_SHIFT_TXPKTNUM)
#define BIT_CLEAR_TXPKTNUM(x)				((x) & (~BITS_TXPKTNUM))
#define BIT_GET_TXPKTNUM(x)				(((x) >> BIT_SHIFT_TXPKTNUM) & BIT_MASK_TXPKTNUM)
#define BIT_SET_TXPKTNUM(x, v)				(BIT_CLEAR_TXPKTNUM(x) | BIT_TXPKTNUM(v))

#define BIT_SHIFT_PUBQ_AVAL_PG				16
#define BIT_MASK_PUBQ_AVAL_PG				0xff
#define BIT_PUBQ_AVAL_PG(x)				(((x) & BIT_MASK_PUBQ_AVAL_PG) << BIT_SHIFT_PUBQ_AVAL_PG)
#define BITS_PUBQ_AVAL_PG				(BIT_MASK_PUBQ_AVAL_PG << BIT_SHIFT_PUBQ_AVAL_PG)
#define BIT_CLEAR_PUBQ_AVAL_PG(x)			((x) & (~BITS_PUBQ_AVAL_PG))
#define BIT_GET_PUBQ_AVAL_PG(x)			(((x) >> BIT_SHIFT_PUBQ_AVAL_PG) & BIT_MASK_PUBQ_AVAL_PG)
#define BIT_SET_PUBQ_AVAL_PG(x, v)			(BIT_CLEAR_PUBQ_AVAL_PG(x) | BIT_PUBQ_AVAL_PG(v))

#define BIT_SHIFT_LPQ_AVAL_PG				8
#define BIT_MASK_LPQ_AVAL_PG				0xff
#define BIT_LPQ_AVAL_PG(x)				(((x) & BIT_MASK_LPQ_AVAL_PG) << BIT_SHIFT_LPQ_AVAL_PG)
#define BITS_LPQ_AVAL_PG				(BIT_MASK_LPQ_AVAL_PG << BIT_SHIFT_LPQ_AVAL_PG)
#define BIT_CLEAR_LPQ_AVAL_PG(x)			((x) & (~BITS_LPQ_AVAL_PG))
#define BIT_GET_LPQ_AVAL_PG(x)				(((x) >> BIT_SHIFT_LPQ_AVAL_PG) & BIT_MASK_LPQ_AVAL_PG)
#define BIT_SET_LPQ_AVAL_PG(x, v)			(BIT_CLEAR_LPQ_AVAL_PG(x) | BIT_LPQ_AVAL_PG(v))

#define BIT_SHIFT_HPQ_AVAL_PG				0
#define BIT_MASK_HPQ_AVAL_PG				0xff
#define BIT_HPQ_AVAL_PG(x)				(((x) & BIT_MASK_HPQ_AVAL_PG) << BIT_SHIFT_HPQ_AVAL_PG)
#define BITS_HPQ_AVAL_PG				(BIT_MASK_HPQ_AVAL_PG << BIT_SHIFT_HPQ_AVAL_PG)
#define BIT_CLEAR_HPQ_AVAL_PG(x)			((x) & (~BITS_HPQ_AVAL_PG))
#define BIT_GET_HPQ_AVAL_PG(x)				(((x) >> BIT_SHIFT_HPQ_AVAL_PG) & BIT_MASK_HPQ_AVAL_PG)
#define BIT_SET_HPQ_AVAL_PG(x, v)			(BIT_CLEAR_HPQ_AVAL_PG(x) | BIT_HPQ_AVAL_PG(v))

/* 2 REG_DWBCN0_CTRL				(Offset 0x0208) */

#define BIT_SHIFT_LLT_FREE_PAGE			24
#define BIT_MASK_LLT_FREE_PAGE				0xff
#define BIT_LLT_FREE_PAGE(x)				(((x) & BIT_MASK_LLT_FREE_PAGE) << BIT_SHIFT_LLT_FREE_PAGE)
#define BITS_LLT_FREE_PAGE				(BIT_MASK_LLT_FREE_PAGE << BIT_SHIFT_LLT_FREE_PAGE)
#define BIT_CLEAR_LLT_FREE_PAGE(x)			((x) & (~BITS_LLT_FREE_PAGE))
#define BIT_GET_LLT_FREE_PAGE(x)			(((x) >> BIT_SHIFT_LLT_FREE_PAGE) & BIT_MASK_LLT_FREE_PAGE)
#define BIT_SET_LLT_FREE_PAGE(x, v)			(BIT_CLEAR_LLT_FREE_PAGE(x) | BIT_LLT_FREE_PAGE(v))

#define BIT_SHIFT_RSVD_BYTE1				17
#define BIT_MASK_RSVD_BYTE1				0x7f
#define BIT_RSVD_BYTE1(x)				(((x) & BIT_MASK_RSVD_BYTE1) << BIT_SHIFT_RSVD_BYTE1)
#define BITS_RSVD_BYTE1				(BIT_MASK_RSVD_BYTE1 << BIT_SHIFT_RSVD_BYTE1)
#define BIT_CLEAR_RSVD_BYTE1(x)			((x) & (~BITS_RSVD_BYTE1))
#define BIT_GET_RSVD_BYTE1(x)				(((x) >> BIT_SHIFT_RSVD_BYTE1) & BIT_MASK_RSVD_BYTE1)
#define BIT_SET_RSVD_BYTE1(x, v)			(BIT_CLEAR_RSVD_BYTE1(x) | BIT_RSVD_BYTE1(v))

#define BIT_BCN_VALID					BIT(16)

#define BIT_SHIFT_BCN_HEAD				8
#define BIT_MASK_BCN_HEAD				0xff
#define BIT_BCN_HEAD(x)				(((x) & BIT_MASK_BCN_HEAD) << BIT_SHIFT_BCN_HEAD)
#define BITS_BCN_HEAD					(BIT_MASK_BCN_HEAD << BIT_SHIFT_BCN_HEAD)
#define BIT_CLEAR_BCN_HEAD(x)				((x) & (~BITS_BCN_HEAD))
#define BIT_GET_BCN_HEAD(x)				(((x) >> BIT_SHIFT_BCN_HEAD) & BIT_MASK_BCN_HEAD)
#define BIT_SET_BCN_HEAD(x, v)				(BIT_CLEAR_BCN_HEAD(x) | BIT_BCN_HEAD(v))

#define BIT_SHIFT_BLK_DESC_NUM				4
#define BIT_MASK_BLK_DESC_NUM				0xf
#define BIT_BLK_DESC_NUM(x)				(((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM)
#define BITS_BLK_DESC_NUM				(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM)
#define BIT_CLEAR_BLK_DESC_NUM(x)			((x) & (~BITS_BLK_DESC_NUM))
#define BIT_GET_BLK_DESC_NUM(x)			(((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM)
#define BIT_SET_BLK_DESC_NUM(x, v)			(BIT_CLEAR_BLK_DESC_NUM(x) | BIT_BLK_DESC_NUM(v))

#define BIT_BLK_DESC_OPT				BIT(0)

/* 2 REG_TXDMA_OFFSET_CHK			(Offset 0x020C) */

#define BIT_EN_CHKERR_FINISH				BIT(31)
#define BIT_EN_DMA_PERMU_P				BIT(30)
#define BIT_EN_TXQUE_CLR				BIT(29)
#define BIT_EN_PCIE_FIFO				BIT(28)

#define BIT_SHIFT_PG_UNDER_TH				16
#define BIT_MASK_PG_UNDER_TH				0xff
#define BIT_PG_UNDER_TH(x)				(((x) & BIT_MASK_PG_UNDER_TH) << BIT_SHIFT_PG_UNDER_TH)
#define BITS_PG_UNDER_TH				(BIT_MASK_PG_UNDER_TH << BIT_SHIFT_PG_UNDER_TH)
#define BIT_CLEAR_PG_UNDER_TH(x)			((x) & (~BITS_PG_UNDER_TH))
#define BIT_GET_PG_UNDER_TH(x)				(((x) >> BIT_SHIFT_PG_UNDER_TH) & BIT_MASK_PG_UNDER_TH)
#define BIT_SET_PG_UNDER_TH(x, v)			(BIT_CLEAR_PG_UNDER_TH(x) | BIT_PG_UNDER_TH(v))

#define BIT_DSC_CHKSUM_EN				BIT(13)
#define BIT_RST_RDPTR					BIT(12)
#define BIT_RST_WRPTR					BIT(11)
#define BIT_CHK_PG_TH_EN				BIT(10)
#define BIT_DROP_DATA_EN				BIT(9)
#define BIT_CHECK_OFFSET_EN				BIT(8)

#define BIT_SHIFT_CHK_OFFSET				0
#define BIT_MASK_CHK_OFFSET				0xff
#define BIT_CHK_OFFSET(x)				(((x) & BIT_MASK_CHK_OFFSET) << BIT_SHIFT_CHK_OFFSET)
#define BITS_CHK_OFFSET				(BIT_MASK_CHK_OFFSET << BIT_SHIFT_CHK_OFFSET)
#define BIT_CLEAR_CHK_OFFSET(x)			((x) & (~BITS_CHK_OFFSET))
#define BIT_GET_CHK_OFFSET(x)				(((x) >> BIT_SHIFT_CHK_OFFSET) & BIT_MASK_CHK_OFFSET)
#define BIT_SET_CHK_OFFSET(x, v)			(BIT_CLEAR_CHK_OFFSET(x) | BIT_CHK_OFFSET(v))

/* 2 REG_TXDMA_STATUS			(Offset 0x0210) */

#define BIT_HI_OQT_UDN					BIT(17)
#define BIT_HI_OQT_OVF					BIT(16)
#define BIT_PAYLOAD_CHKSUM_ERR				BIT(15)
#define BIT_PAYLOAD_UDN				BIT(14)
#define BIT_PAYLOAD_OVF				BIT(13)
#define BIT_DSC_CHKSUM_FAIL				BIT(12)
#define BIT_UNKNOWN_QSEL				BIT(11)
#define BIT_EP_QSEL_DIFF				BIT(10)
#define BIT_TX_OFFS_UNMATCH				BIT(9)
#define BIT_TXOQT_UDN					BIT(8)
#define BIT_TXOQT_OVF					BIT(7)
#define BIT_SFF_UDN					BIT(6)
#define BIT_SFF_OVF					BIT(5)
#define BIT_FREE_PG_FF					BIT(4)
#define BIT_PAGE_UNDER					BIT(3)
#define BIT_PAGE_OVER					BIT(2)
#define BIT_PG_UDN					BIT(1)
#define BIT_PG_OVF					BIT(0)

/* 2 REG_RQPN_NPQ				(Offset 0x0214) */

#define BIT_SHIFT_EPQ_PGNUM				24
#define BIT_MASK_EPQ_PGNUM				0xff
#define BIT_EPQ_PGNUM(x)				(((x) & BIT_MASK_EPQ_PGNUM) << BIT_SHIFT_EPQ_PGNUM)
#define BITS_EPQ_PGNUM					(BIT_MASK_EPQ_PGNUM << BIT_SHIFT_EPQ_PGNUM)
#define BIT_CLEAR_EPQ_PGNUM(x)				((x) & (~BITS_EPQ_PGNUM))
#define BIT_GET_EPQ_PGNUM(x)				(((x) >> BIT_SHIFT_EPQ_PGNUM) & BIT_MASK_EPQ_PGNUM)
#define BIT_SET_EPQ_PGNUM(x, v)			(BIT_CLEAR_EPQ_PGNUM(x) | BIT_EPQ_PGNUM(v))

#define BIT_SHIFT_EPQ_R_PGNUM				16
#define BIT_MASK_EPQ_R_PGNUM				0xff
#define BIT_EPQ_R_PGNUM(x)				(((x) & BIT_MASK_EPQ_R_PGNUM) << BIT_SHIFT_EPQ_R_PGNUM)
#define BITS_EPQ_R_PGNUM				(BIT_MASK_EPQ_R_PGNUM << BIT_SHIFT_EPQ_R_PGNUM)
#define BIT_CLEAR_EPQ_R_PGNUM(x)			((x) & (~BITS_EPQ_R_PGNUM))
#define BIT_GET_EPQ_R_PGNUM(x)				(((x) >> BIT_SHIFT_EPQ_R_PGNUM) & BIT_MASK_EPQ_R_PGNUM)
#define BIT_SET_EPQ_R_PGNUM(x, v)			(BIT_CLEAR_EPQ_R_PGNUM(x) | BIT_EPQ_R_PGNUM(v))

#define BIT_SHIFT_NPQ_PGNUM				8
#define BIT_MASK_NPQ_PGNUM				0xff
#define BIT_NPQ_PGNUM(x)				(((x) & BIT_MASK_NPQ_PGNUM) << BIT_SHIFT_NPQ_PGNUM)
#define BITS_NPQ_PGNUM					(BIT_MASK_NPQ_PGNUM << BIT_SHIFT_NPQ_PGNUM)
#define BIT_CLEAR_NPQ_PGNUM(x)				((x) & (~BITS_NPQ_PGNUM))
#define BIT_GET_NPQ_PGNUM(x)				(((x) >> BIT_SHIFT_NPQ_PGNUM) & BIT_MASK_NPQ_PGNUM)
#define BIT_SET_NPQ_PGNUM(x, v)			(BIT_CLEAR_NPQ_PGNUM(x) | BIT_NPQ_PGNUM(v))

#define BIT_SHIFT_NPQ_R_PGNUM				0
#define BIT_MASK_NPQ_R_PGNUM				0xff
#define BIT_NPQ_R_PGNUM(x)				(((x) & BIT_MASK_NPQ_R_PGNUM) << BIT_SHIFT_NPQ_R_PGNUM)
#define BITS_NPQ_R_PGNUM				(BIT_MASK_NPQ_R_PGNUM << BIT_SHIFT_NPQ_R_PGNUM)
#define BIT_CLEAR_NPQ_R_PGNUM(x)			((x) & (~BITS_NPQ_R_PGNUM))
#define BIT_GET_NPQ_R_PGNUM(x)				(((x) >> BIT_SHIFT_NPQ_R_PGNUM) & BIT_MASK_NPQ_R_PGNUM)
#define BIT_SET_NPQ_R_PGNUM(x, v)			(BIT_CLEAR_NPQ_R_PGNUM(x) | BIT_NPQ_R_PGNUM(v))

/* 2 REG_TQPNT1				(Offset 0x0218) */

#define BIT_SHIFT_NPQ_HIGH_TH				24
#define BIT_MASK_NPQ_HIGH_TH				0xff
#define BIT_NPQ_HIGH_TH(x)				(((x) & BIT_MASK_NPQ_HIGH_TH) << BIT_SHIFT_NPQ_HIGH_TH)
#define BITS_NPQ_HIGH_TH				(BIT_MASK_NPQ_HIGH_TH << BIT_SHIFT_NPQ_HIGH_TH)
#define BIT_CLEAR_NPQ_HIGH_TH(x)			((x) & (~BITS_NPQ_HIGH_TH))
#define BIT_GET_NPQ_HIGH_TH(x)				(((x) >> BIT_SHIFT_NPQ_HIGH_TH) & BIT_MASK_NPQ_HIGH_TH)
#define BIT_SET_NPQ_HIGH_TH(x, v)			(BIT_CLEAR_NPQ_HIGH_TH(x) | BIT_NPQ_HIGH_TH(v))

#define BIT_SHIFT_NPQ_LOW_TH				16
#define BIT_MASK_NPQ_LOW_TH				0xff
#define BIT_NPQ_LOW_TH(x)				(((x) & BIT_MASK_NPQ_LOW_TH) << BIT_SHIFT_NPQ_LOW_TH)
#define BITS_NPQ_LOW_TH				(BIT_MASK_NPQ_LOW_TH << BIT_SHIFT_NPQ_LOW_TH)
#define BIT_CLEAR_NPQ_LOW_TH(x)			((x) & (~BITS_NPQ_LOW_TH))
#define BIT_GET_NPQ_LOW_TH(x)				(((x) >> BIT_SHIFT_NPQ_LOW_TH) & BIT_MASK_NPQ_LOW_TH)
#define BIT_SET_NPQ_LOW_TH(x, v)			(BIT_CLEAR_NPQ_LOW_TH(x) | BIT_NPQ_LOW_TH(v))

#define BIT_SHIFT_HPQ_HIGH_TH				8
#define BIT_MASK_HPQ_HIGH_TH				0xff
#define BIT_HPQ_HIGH_TH(x)				(((x) & BIT_MASK_HPQ_HIGH_TH) << BIT_SHIFT_HPQ_HIGH_TH)
#define BITS_HPQ_HIGH_TH				(BIT_MASK_HPQ_HIGH_TH << BIT_SHIFT_HPQ_HIGH_TH)
#define BIT_CLEAR_HPQ_HIGH_TH(x)			((x) & (~BITS_HPQ_HIGH_TH))
#define BIT_GET_HPQ_HIGH_TH(x)				(((x) >> BIT_SHIFT_HPQ_HIGH_TH) & BIT_MASK_HPQ_HIGH_TH)
#define BIT_SET_HPQ_HIGH_TH(x, v)			(BIT_CLEAR_HPQ_HIGH_TH(x) | BIT_HPQ_HIGH_TH(v))

#define BIT_SHIFT_HPQ_LOW_TH				0
#define BIT_MASK_HPQ_LOW_TH				0xff
#define BIT_HPQ_LOW_TH(x)				(((x) & BIT_MASK_HPQ_LOW_TH) << BIT_SHIFT_HPQ_LOW_TH)
#define BITS_HPQ_LOW_TH				(BIT_MASK_HPQ_LOW_TH << BIT_SHIFT_HPQ_LOW_TH)
#define BIT_CLEAR_HPQ_LOW_TH(x)			((x) & (~BITS_HPQ_LOW_TH))
#define BIT_GET_HPQ_LOW_TH(x)				(((x) >> BIT_SHIFT_HPQ_LOW_TH) & BIT_MASK_HPQ_LOW_TH)
#define BIT_SET_HPQ_LOW_TH(x, v)			(BIT_CLEAR_HPQ_LOW_TH(x) | BIT_HPQ_LOW_TH(v))

/* 2 REG_TQPNT2				(Offset 0x021C) */

#define BIT_SHIFT_EXQ_HIGH_TH				24
#define BIT_MASK_EXQ_HIGH_TH				0xff
#define BIT_EXQ_HIGH_TH(x)				(((x) & BIT_MASK_EXQ_HIGH_TH) << BIT_SHIFT_EXQ_HIGH_TH)
#define BITS_EXQ_HIGH_TH				(BIT_MASK_EXQ_HIGH_TH << BIT_SHIFT_EXQ_HIGH_TH)
#define BIT_CLEAR_EXQ_HIGH_TH(x)			((x) & (~BITS_EXQ_HIGH_TH))
#define BIT_GET_EXQ_HIGH_TH(x)				(((x) >> BIT_SHIFT_EXQ_HIGH_TH) & BIT_MASK_EXQ_HIGH_TH)
#define BIT_SET_EXQ_HIGH_TH(x, v)			(BIT_CLEAR_EXQ_HIGH_TH(x) | BIT_EXQ_HIGH_TH(v))

#define BIT_SHIFT_EXQ_LOW_TH				16
#define BIT_MASK_EXQ_LOW_TH				0xff
#define BIT_EXQ_LOW_TH(x)				(((x) & BIT_MASK_EXQ_LOW_TH) << BIT_SHIFT_EXQ_LOW_TH)
#define BITS_EXQ_LOW_TH				(BIT_MASK_EXQ_LOW_TH << BIT_SHIFT_EXQ_LOW_TH)
#define BIT_CLEAR_EXQ_LOW_TH(x)			((x) & (~BITS_EXQ_LOW_TH))
#define BIT_GET_EXQ_LOW_TH(x)				(((x) >> BIT_SHIFT_EXQ_LOW_TH) & BIT_MASK_EXQ_LOW_TH)
#define BIT_SET_EXQ_LOW_TH(x, v)			(BIT_CLEAR_EXQ_LOW_TH(x) | BIT_EXQ_LOW_TH(v))

#define BIT_SHIFT_LPQ_HIGH_TH				8
#define BIT_MASK_LPQ_HIGH_TH				0xff
#define BIT_LPQ_HIGH_TH(x)				(((x) & BIT_MASK_LPQ_HIGH_TH) << BIT_SHIFT_LPQ_HIGH_TH)
#define BITS_LPQ_HIGH_TH				(BIT_MASK_LPQ_HIGH_TH << BIT_SHIFT_LPQ_HIGH_TH)
#define BIT_CLEAR_LPQ_HIGH_TH(x)			((x) & (~BITS_LPQ_HIGH_TH))
#define BIT_GET_LPQ_HIGH_TH(x)				(((x) >> BIT_SHIFT_LPQ_HIGH_TH) & BIT_MASK_LPQ_HIGH_TH)
#define BIT_SET_LPQ_HIGH_TH(x, v)			(BIT_CLEAR_LPQ_HIGH_TH(x) | BIT_LPQ_HIGH_TH(v))

#define BIT_SHIFT_LPQ_LOW_TH				0
#define BIT_MASK_LPQ_LOW_TH				0xff
#define BIT_LPQ_LOW_TH(x)				(((x) & BIT_MASK_LPQ_LOW_TH) << BIT_SHIFT_LPQ_LOW_TH)
#define BITS_LPQ_LOW_TH				(BIT_MASK_LPQ_LOW_TH << BIT_SHIFT_LPQ_LOW_TH)
#define BIT_CLEAR_LPQ_LOW_TH(x)			((x) & (~BITS_LPQ_LOW_TH))
#define BIT_GET_LPQ_LOW_TH(x)				(((x) >> BIT_SHIFT_LPQ_LOW_TH) & BIT_MASK_LPQ_LOW_TH)
#define BIT_SET_LPQ_LOW_TH(x, v)			(BIT_CLEAR_LPQ_LOW_TH(x) | BIT_LPQ_LOW_TH(v))

/* 2 REG_TDE_DEBUG				(Offset 0x0220) */

#define BIT_SHIFT_TDE_DEBUG				0
#define BIT_MASK_TDE_DEBUG				0xffffffffL
#define BIT_TDE_DEBUG(x)				(((x) & BIT_MASK_TDE_DEBUG) << BIT_SHIFT_TDE_DEBUG)
#define BITS_TDE_DEBUG					(BIT_MASK_TDE_DEBUG << BIT_SHIFT_TDE_DEBUG)
#define BIT_CLEAR_TDE_DEBUG(x)				((x) & (~BITS_TDE_DEBUG))
#define BIT_GET_TDE_DEBUG(x)				(((x) >> BIT_SHIFT_TDE_DEBUG) & BIT_MASK_TDE_DEBUG)
#define BIT_SET_TDE_DEBUG(x, v)			(BIT_CLEAR_TDE_DEBUG(x) | BIT_TDE_DEBUG(v))

/* 2 REG_AUTO_LLT				(Offset 0x0224) */

#define BIT_SHIFT_TXPKTNUM_H				24
#define BIT_MASK_TXPKTNUM_H				0xff
#define BIT_TXPKTNUM_H(x)				(((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H)
#define BITS_TXPKTNUM_H				(BIT_MASK_TXPKTNUM_H << BIT_SHIFT_TXPKTNUM_H)
#define BIT_CLEAR_TXPKTNUM_H(x)			((x) & (~BITS_TXPKTNUM_H))
#define BIT_GET_TXPKTNUM_H(x)				(((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H)
#define BIT_SET_TXPKTNUM_H(x, v)			(BIT_CLEAR_TXPKTNUM_H(x) | BIT_TXPKTNUM_H(v))

#define BIT_TDE_DBG_SEL				BIT(23)
#define BIT_MASK_QSEL_DIFF				BIT(22)
#define BIT_AUTO_INIT_LLT				BIT(16)

#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE			8
#define BIT_MASK_TX_OQT_HE_FREE_SPACE			0xff
#define BIT_TX_OQT_HE_FREE_SPACE(x)			(((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE)
#define BITS_TX_OQT_HE_FREE_SPACE			(BIT_MASK_TX_OQT_HE_FREE_SPACE << BIT_SHIFT_TX_OQT_HE_FREE_SPACE)
#define BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x)		((x) & (~BITS_TX_OQT_HE_FREE_SPACE))
#define BIT_GET_TX_OQT_HE_FREE_SPACE(x)		(((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE) & BIT_MASK_TX_OQT_HE_FREE_SPACE)
#define BIT_SET_TX_OQT_HE_FREE_SPACE(x, v)		(BIT_CLEAR_TX_OQT_HE_FREE_SPACE(x) | BIT_TX_OQT_HE_FREE_SPACE(v))

#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE			0
#define BIT_MASK_TX_OQT_NL_FREE_SPACE			0xff
#define BIT_TX_OQT_NL_FREE_SPACE(x)			(((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE)
#define BITS_TX_OQT_NL_FREE_SPACE			(BIT_MASK_TX_OQT_NL_FREE_SPACE << BIT_SHIFT_TX_OQT_NL_FREE_SPACE)
#define BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x)		((x) & (~BITS_TX_OQT_NL_FREE_SPACE))
#define BIT_GET_TX_OQT_NL_FREE_SPACE(x)		(((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE) & BIT_MASK_TX_OQT_NL_FREE_SPACE)
#define BIT_SET_TX_OQT_NL_FREE_SPACE(x, v)		(BIT_CLEAR_TX_OQT_NL_FREE_SPACE(x) | BIT_TX_OQT_NL_FREE_SPACE(v))

/* 2 REG_DWBCN1_CTRL				(Offset 0x0228) */

#define BIT_SHIFT_BCN_HEAD_2				24
#define BIT_MASK_BCN_HEAD_2				0xff
#define BIT_BCN_HEAD_2(x)				(((x) & BIT_MASK_BCN_HEAD_2) << BIT_SHIFT_BCN_HEAD_2)
#define BITS_BCN_HEAD_2				(BIT_MASK_BCN_HEAD_2 << BIT_SHIFT_BCN_HEAD_2)
#define BIT_CLEAR_BCN_HEAD_2(x)			((x) & (~BITS_BCN_HEAD_2))
#define BIT_GET_BCN_HEAD_2(x)				(((x) >> BIT_SHIFT_BCN_HEAD_2) & BIT_MASK_BCN_HEAD_2)
#define BIT_SET_BCN_HEAD_2(x, v)			(BIT_CLEAR_BCN_HEAD_2(x) | BIT_BCN_HEAD_2(v))

#define BIT_SHIFT_SW_BCN_SEL				20
#define BIT_MASK_SW_BCN_SEL				0x3
#define BIT_SW_BCN_SEL(x)				(((x) & BIT_MASK_SW_BCN_SEL) << BIT_SHIFT_SW_BCN_SEL)
#define BITS_SW_BCN_SEL				(BIT_MASK_SW_BCN_SEL << BIT_SHIFT_SW_BCN_SEL)
#define BIT_CLEAR_SW_BCN_SEL(x)			((x) & (~BITS_SW_BCN_SEL))
#define BIT_GET_SW_BCN_SEL(x)				(((x) >> BIT_SHIFT_SW_BCN_SEL) & BIT_MASK_SW_BCN_SEL)
#define BIT_SET_SW_BCN_SEL(x, v)			(BIT_CLEAR_SW_BCN_SEL(x) | BIT_SW_BCN_SEL(v))

#define BIT_BCN_VALID_2				BIT(18)
#define BIT_SW_BCN_SEL_EN				BIT(17)
#define BIT_BCN_VALID_1				BIT(16)

#define BIT_SHIFT_BCN_HEAD_1				8
#define BIT_MASK_BCN_HEAD_1				0xff
#define BIT_BCN_HEAD_1(x)				(((x) & BIT_MASK_BCN_HEAD_1) << BIT_SHIFT_BCN_HEAD_1)
#define BITS_BCN_HEAD_1				(BIT_MASK_BCN_HEAD_1 << BIT_SHIFT_BCN_HEAD_1)
#define BIT_CLEAR_BCN_HEAD_1(x)			((x) & (~BITS_BCN_HEAD_1))
#define BIT_GET_BCN_HEAD_1(x)				(((x) >> BIT_SHIFT_BCN_HEAD_1) & BIT_MASK_BCN_HEAD_1)
#define BIT_SET_BCN_HEAD_1(x, v)			(BIT_CLEAR_BCN_HEAD_1(x) | BIT_BCN_HEAD_1(v))

#define BIT_SHIFT_MAX_TX_PKT				0
#define BIT_MASK_MAX_TX_PKT				0xff
#define BIT_MAX_TX_PKT(x)				(((x) & BIT_MASK_MAX_TX_PKT) << BIT_SHIFT_MAX_TX_PKT)
#define BITS_MAX_TX_PKT				(BIT_MASK_MAX_TX_PKT << BIT_SHIFT_MAX_TX_PKT)
#define BIT_CLEAR_MAX_TX_PKT(x)			((x) & (~BITS_MAX_TX_PKT))
#define BIT_GET_MAX_TX_PKT(x)				(((x) >> BIT_SHIFT_MAX_TX_PKT) & BIT_MASK_MAX_TX_PKT)
#define BIT_SET_MAX_TX_PKT(x, v)			(BIT_CLEAR_MAX_TX_PKT(x) | BIT_MAX_TX_PKT(v))

/* 2 REG_TX_ALIGNMENT_CTRL			(Offset 0x022C) */

#define BIT_ADJUSTABLE_SIZE_EN				BIT(15)

#define BIT_SHIFT_ALIGNMENT_SIZE			0
#define BIT_MASK_ALIGNMENT_SIZE			0xfff
#define BIT_ALIGNMENT_SIZE(x)				(((x) & BIT_MASK_ALIGNMENT_SIZE) << BIT_SHIFT_ALIGNMENT_SIZE)
#define BITS_ALIGNMENT_SIZE				(BIT_MASK_ALIGNMENT_SIZE << BIT_SHIFT_ALIGNMENT_SIZE)
#define BIT_CLEAR_ALIGNMENT_SIZE(x)			((x) & (~BITS_ALIGNMENT_SIZE))
#define BIT_GET_ALIGNMENT_SIZE(x)			(((x) >> BIT_SHIFT_ALIGNMENT_SIZE) & BIT_MASK_ALIGNMENT_SIZE)
#define BIT_SET_ALIGNMENT_SIZE(x, v)			(BIT_CLEAR_ALIGNMENT_SIZE(x) | BIT_ALIGNMENT_SIZE(v))

/* 2 REG_RXDMA_AGG_PG_TH			(Offset 0x0280) */

#define BIT_RXDMA_STORE				BIT(31)
#define BIT_EN_PRE_CALC				BIT(29)

#define BIT_SHIFT_PKT_NUM_WOL				16
#define BIT_MASK_PKT_NUM_WOL				0xff
#define BIT_PKT_NUM_WOL(x)				(((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL)
#define BITS_PKT_NUM_WOL				(BIT_MASK_PKT_NUM_WOL << BIT_SHIFT_PKT_NUM_WOL)
#define BIT_CLEAR_PKT_NUM_WOL(x)			((x) & (~BITS_PKT_NUM_WOL))
#define BIT_GET_PKT_NUM_WOL(x)				(((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL)
#define BIT_SET_PKT_NUM_WOL(x, v)			(BIT_CLEAR_PKT_NUM_WOL(x) | BIT_PKT_NUM_WOL(v))

#define BIT_SHIFT_DMA_TIMEOUT_TH			8
#define BIT_MASK_DMA_TIMEOUT_TH			0xff
#define BIT_DMA_TIMEOUT_TH(x)				(((x) & BIT_MASK_DMA_TIMEOUT_TH) << BIT_SHIFT_DMA_TIMEOUT_TH)
#define BITS_DMA_TIMEOUT_TH				(BIT_MASK_DMA_TIMEOUT_TH << BIT_SHIFT_DMA_TIMEOUT_TH)
#define BIT_CLEAR_DMA_TIMEOUT_TH(x)			((x) & (~BITS_DMA_TIMEOUT_TH))
#define BIT_GET_DMA_TIMEOUT_TH(x)			(((x) >> BIT_SHIFT_DMA_TIMEOUT_TH) & BIT_MASK_DMA_TIMEOUT_TH)
#define BIT_SET_DMA_TIMEOUT_TH(x, v)			(BIT_CLEAR_DMA_TIMEOUT_TH(x) | BIT_DMA_TIMEOUT_TH(v))

#define BIT_SHIFT_RXDMA_AGG_PG_TH			0
#define BIT_MASK_RXDMA_AGG_PG_TH			0xff
#define BIT_RXDMA_AGG_PG_TH(x)				(((x) & BIT_MASK_RXDMA_AGG_PG_TH) << BIT_SHIFT_RXDMA_AGG_PG_TH)
#define BITS_RXDMA_AGG_PG_TH				(BIT_MASK_RXDMA_AGG_PG_TH << BIT_SHIFT_RXDMA_AGG_PG_TH)
#define BIT_CLEAR_RXDMA_AGG_PG_TH(x)			((x) & (~BITS_RXDMA_AGG_PG_TH))
#define BIT_GET_RXDMA_AGG_PG_TH(x)			(((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH) & BIT_MASK_RXDMA_AGG_PG_TH)
#define BIT_SET_RXDMA_AGG_PG_TH(x, v)			(BIT_CLEAR_RXDMA_AGG_PG_TH(x) | BIT_RXDMA_AGG_PG_TH(v))

/* 2 REG_RXPKT_NUM				(Offset 0x0284) */

#define BIT_SHIFT_RXPKT_QUEUED				24
#define BIT_MASK_RXPKT_QUEUED				0xff
#define BIT_RXPKT_QUEUED(x)				(((x) & BIT_MASK_RXPKT_QUEUED) << BIT_SHIFT_RXPKT_QUEUED)
#define BITS_RXPKT_QUEUED				(BIT_MASK_RXPKT_QUEUED << BIT_SHIFT_RXPKT_QUEUED)
#define BIT_CLEAR_RXPKT_QUEUED(x)			((x) & (~BITS_RXPKT_QUEUED))
#define BIT_GET_RXPKT_QUEUED(x)			(((x) >> BIT_SHIFT_RXPKT_QUEUED) & BIT_MASK_RXPKT_QUEUED)
#define BIT_SET_RXPKT_QUEUED(x, v)			(BIT_CLEAR_RXPKT_QUEUED(x) | BIT_RXPKT_QUEUED(v))

#define BIT_WMACSTOP_RXDMA				BIT(20)
#define BIT_RXDMA_REQ					BIT(19)
#define BIT_FW_RELEASE_EN				BIT(18)
#define BIT_RXDMA_IDLE					BIT(17)
#define BIT_RXPKT_RELEASE_POLL				BIT(16)

#define BIT_SHIFT_FW_UPD_RXPKT_RDPTR			0
#define BIT_MASK_FW_UPD_RXPKT_RDPTR			0xffff
#define BIT_FW_UPD_RXPKT_RDPTR(x)			(((x) & BIT_MASK_FW_UPD_RXPKT_RDPTR) << BIT_SHIFT_FW_UPD_RXPKT_RDPTR)
#define BITS_FW_UPD_RXPKT_RDPTR			(BIT_MASK_FW_UPD_RXPKT_RDPTR << BIT_SHIFT_FW_UPD_RXPKT_RDPTR)
#define BIT_CLEAR_FW_UPD_RXPKT_RDPTR(x)		((x) & (~BITS_FW_UPD_RXPKT_RDPTR))
#define BIT_GET_FW_UPD_RXPKT_RDPTR(x)			(((x) >> BIT_SHIFT_FW_UPD_RXPKT_RDPTR) & BIT_MASK_FW_UPD_RXPKT_RDPTR)
#define BIT_SET_FW_UPD_RXPKT_RDPTR(x, v)		(BIT_CLEAR_FW_UPD_RXPKT_RDPTR(x) | BIT_FW_UPD_RXPKT_RDPTR(v))

/* 2 REG_RXDMA_STATUS			(Offset 0x0288) */

#define BIT_C2H_PKT_OVF				BIT(7)
#define BIT_AGG_CONFGI_ISSUE				BIT(6)
#define BIT_FW_POLL_ISSUE				BIT(5)
#define BIT_RX_DATA_UDN				BIT(4)
#define BIT_RX_SFF_UDN					BIT(3)
#define BIT_RX_SFF_OVF					BIT(2)
#define BIT_RXPKT_OVF					BIT(0)

/* 2 REG_RXDMA_DPR				(Offset 0x028C) */

#define BIT_SHIFT_RDE_DBG				0
#define BIT_MASK_RDE_DBG				0xffffffffL
#define BIT_RDE_DBG(x)					(((x) & BIT_MASK_RDE_DBG) << BIT_SHIFT_RDE_DBG)
#define BITS_RDE_DBG					(BIT_MASK_RDE_DBG << BIT_SHIFT_RDE_DBG)
#define BIT_CLEAR_RDE_DBG(x)				((x) & (~BITS_RDE_DBG))
#define BIT_GET_RDE_DBG(x)				(((x) >> BIT_SHIFT_RDE_DBG) & BIT_MASK_RDE_DBG)
#define BIT_SET_RDE_DBG(x, v)				(BIT_CLEAR_RDE_DBG(x) | BIT_RDE_DBG(v))

/* 2 REG_RXDMA_MODE				(Offset 0x0290) */

#define BIT_SHIFT_BURST_SIZE				4
#define BIT_MASK_BURST_SIZE				0x3
#define BIT_BURST_SIZE(x)				(((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE)
#define BITS_BURST_SIZE				(BIT_MASK_BURST_SIZE << BIT_SHIFT_BURST_SIZE)
#define BIT_CLEAR_BURST_SIZE(x)			((x) & (~BITS_BURST_SIZE))
#define BIT_GET_BURST_SIZE(x)				(((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE)
#define BIT_SET_BURST_SIZE(x, v)			(BIT_CLEAR_BURST_SIZE(x) | BIT_BURST_SIZE(v))

#define BIT_SHIFT_BURST_CNT				2
#define BIT_MASK_BURST_CNT				0x3
#define BIT_BURST_CNT(x)				(((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT)
#define BITS_BURST_CNT					(BIT_MASK_BURST_CNT << BIT_SHIFT_BURST_CNT)
#define BIT_CLEAR_BURST_CNT(x)				((x) & (~BITS_BURST_CNT))
#define BIT_GET_BURST_CNT(x)				(((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT)
#define BIT_SET_BURST_CNT(x, v)			(BIT_CLEAR_BURST_CNT(x) | BIT_BURST_CNT(v))

#define BIT_DMA_MODE					BIT(1)
#define BIT_MASK_RX_PKT_PS				BIT(0)

/* 2 REG_C2H_PKT				(Offset 0x0294) */

#define BIT_R_C2H_PKT_REQ				BIT(16)

#define BIT_SHIFT_R_C2H_STR_ADDR			0
#define BIT_MASK_R_C2H_STR_ADDR			0xffff
#define BIT_R_C2H_STR_ADDR(x)				(((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR)
#define BITS_R_C2H_STR_ADDR				(BIT_MASK_R_C2H_STR_ADDR << BIT_SHIFT_R_C2H_STR_ADDR)
#define BIT_CLEAR_R_C2H_STR_ADDR(x)			((x) & (~BITS_R_C2H_STR_ADDR))
#define BIT_GET_R_C2H_STR_ADDR(x)			(((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR)
#define BIT_SET_R_C2H_STR_ADDR(x, v)			(BIT_CLEAR_R_C2H_STR_ADDR(x) | BIT_R_C2H_STR_ADDR(v))

/* 2 REG_Q0_INFO				(Offset 0x0400) */

#define BIT_SHIFT_QUEUEMACID_Q0_V1			25
#define BIT_MASK_QUEUEMACID_Q0_V1			0x7f
#define BIT_QUEUEMACID_Q0_V1(x)			(((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1)
#define BITS_QUEUEMACID_Q0_V1				(BIT_MASK_QUEUEMACID_Q0_V1 << BIT_SHIFT_QUEUEMACID_Q0_V1)
#define BIT_CLEAR_QUEUEMACID_Q0_V1(x)			((x) & (~BITS_QUEUEMACID_Q0_V1))
#define BIT_GET_QUEUEMACID_Q0_V1(x)			(((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1)
#define BIT_SET_QUEUEMACID_Q0_V1(x, v)			(BIT_CLEAR_QUEUEMACID_Q0_V1(x) | BIT_QUEUEMACID_Q0_V1(v))

#define BIT_SHIFT_QUEUEAC_Q0_V1			23
#define BIT_MASK_QUEUEAC_Q0_V1				0x3
#define BIT_QUEUEAC_Q0_V1(x)				(((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1)
#define BITS_QUEUEAC_Q0_V1				(BIT_MASK_QUEUEAC_Q0_V1 << BIT_SHIFT_QUEUEAC_Q0_V1)
#define BIT_CLEAR_QUEUEAC_Q0_V1(x)			((x) & (~BITS_QUEUEAC_Q0_V1))
#define BIT_GET_QUEUEAC_Q0_V1(x)			(((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1)
#define BIT_SET_QUEUEAC_Q0_V1(x, v)			(BIT_CLEAR_QUEUEAC_Q0_V1(x) | BIT_QUEUEAC_Q0_V1(v))

#define BIT_SHIFT_TAIL_PKT_Q0_V1			15
#define BIT_MASK_TAIL_PKT_Q0_V1			0xff
#define BIT_TAIL_PKT_Q0_V1(x)				(((x) & BIT_MASK_TAIL_PKT_Q0_V1) << BIT_SHIFT_TAIL_PKT_Q0_V1)
#define BITS_TAIL_PKT_Q0_V1				(BIT_MASK_TAIL_PKT_Q0_V1 << BIT_SHIFT_TAIL_PKT_Q0_V1)
#define BIT_CLEAR_TAIL_PKT_Q0_V1(x)			((x) & (~BITS_TAIL_PKT_Q0_V1))
#define BIT_GET_TAIL_PKT_Q0_V1(x)			(((x) >> BIT_SHIFT_TAIL_PKT_Q0_V1) & BIT_MASK_TAIL_PKT_Q0_V1)
#define BIT_SET_TAIL_PKT_Q0_V1(x, v)			(BIT_CLEAR_TAIL_PKT_Q0_V1(x) | BIT_TAIL_PKT_Q0_V1(v))

#define BIT_SHIFT_PKT_NUM_Q0_V1			8
#define BIT_MASK_PKT_NUM_Q0_V1				0x7f
#define BIT_PKT_NUM_Q0_V1(x)				(((x) & BIT_MASK_PKT_NUM_Q0_V1) << BIT_SHIFT_PKT_NUM_Q0_V1)
#define BITS_PKT_NUM_Q0_V1				(BIT_MASK_PKT_NUM_Q0_V1 << BIT_SHIFT_PKT_NUM_Q0_V1)
#define BIT_CLEAR_PKT_NUM_Q0_V1(x)			((x) & (~BITS_PKT_NUM_Q0_V1))
#define BIT_GET_PKT_NUM_Q0_V1(x)			(((x) >> BIT_SHIFT_PKT_NUM_Q0_V1) & BIT_MASK_PKT_NUM_Q0_V1)
#define BIT_SET_PKT_NUM_Q0_V1(x, v)			(BIT_CLEAR_PKT_NUM_Q0_V1(x) | BIT_PKT_NUM_Q0_V1(v))

#define BIT_SHIFT_HEAD_PKT_Q0				0
#define BIT_MASK_HEAD_PKT_Q0				0xff
#define BIT_HEAD_PKT_Q0(x)				(((x) & BIT_MASK_HEAD_PKT_Q0) << BIT_SHIFT_HEAD_PKT_Q0)
#define BITS_HEAD_PKT_Q0				(BIT_MASK_HEAD_PKT_Q0 << BIT_SHIFT_HEAD_PKT_Q0)
#define BIT_CLEAR_HEAD_PKT_Q0(x)			((x) & (~BITS_HEAD_PKT_Q0))
#define BIT_GET_HEAD_PKT_Q0(x)				(((x) >> BIT_SHIFT_HEAD_PKT_Q0) & BIT_MASK_HEAD_PKT_Q0)
#define BIT_SET_HEAD_PKT_Q0(x, v)			(BIT_CLEAR_HEAD_PKT_Q0(x) | BIT_HEAD_PKT_Q0(v))

/* 2 REG_Q1_INFO				(Offset 0x0404) */

#define BIT_SHIFT_QUEUEMACID_Q1_V1			25
#define BIT_MASK_QUEUEMACID_Q1_V1			0x7f
#define BIT_QUEUEMACID_Q1_V1(x)			(((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1)
#define BITS_QUEUEMACID_Q1_V1				(BIT_MASK_QUEUEMACID_Q1_V1 << BIT_SHIFT_QUEUEMACID_Q1_V1)
#define BIT_CLEAR_QUEUEMACID_Q1_V1(x)			((x) & (~BITS_QUEUEMACID_Q1_V1))
#define BIT_GET_QUEUEMACID_Q1_V1(x)			(((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1)
#define BIT_SET_QUEUEMACID_Q1_V1(x, v)			(BIT_CLEAR_QUEUEMACID_Q1_V1(x) | BIT_QUEUEMACID_Q1_V1(v))

#define BIT_SHIFT_QUEUEAC_Q1_V1			23
#define BIT_MASK_QUEUEAC_Q1_V1				0x3
#define BIT_QUEUEAC_Q1_V1(x)				(((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1)
#define BITS_QUEUEAC_Q1_V1				(BIT_MASK_QUEUEAC_Q1_V1 << BIT_SHIFT_QUEUEAC_Q1_V1)
#define BIT_CLEAR_QUEUEAC_Q1_V1(x)			((x) & (~BITS_QUEUEAC_Q1_V1))
#define BIT_GET_QUEUEAC_Q1_V1(x)			(((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1)
#define BIT_SET_QUEUEAC_Q1_V1(x, v)			(BIT_CLEAR_QUEUEAC_Q1_V1(x) | BIT_QUEUEAC_Q1_V1(v))

#define BIT_SHIFT_TAIL_PKT_Q1_V1			15
#define BIT_MASK_TAIL_PKT_Q1_V1			0xff
#define BIT_TAIL_PKT_Q1_V1(x)				(((x) & BIT_MASK_TAIL_PKT_Q1_V1) << BIT_SHIFT_TAIL_PKT_Q1_V1)
#define BITS_TAIL_PKT_Q1_V1				(BIT_MASK_TAIL_PKT_Q1_V1 << BIT_SHIFT_TAIL_PKT_Q1_V1)
#define BIT_CLEAR_TAIL_PKT_Q1_V1(x)			((x) & (~BITS_TAIL_PKT_Q1_V1))
#define BIT_GET_TAIL_PKT_Q1_V1(x)			(((x) >> BIT_SHIFT_TAIL_PKT_Q1_V1) & BIT_MASK_TAIL_PKT_Q1_V1)
#define BIT_SET_TAIL_PKT_Q1_V1(x, v)			(BIT_CLEAR_TAIL_PKT_Q1_V1(x) | BIT_TAIL_PKT_Q1_V1(v))

#define BIT_SHIFT_PKT_NUM_Q1_V1			8
#define BIT_MASK_PKT_NUM_Q1_V1				0x7f
#define BIT_PKT_NUM_Q1_V1(x)				(((x) & BIT_MASK_PKT_NUM_Q1_V1) << BIT_SHIFT_PKT_NUM_Q1_V1)
#define BITS_PKT_NUM_Q1_V1				(BIT_MASK_PKT_NUM_Q1_V1 << BIT_SHIFT_PKT_NUM_Q1_V1)
#define BIT_CLEAR_PKT_NUM_Q1_V1(x)			((x) & (~BITS_PKT_NUM_Q1_V1))
#define BIT_GET_PKT_NUM_Q1_V1(x)			(((x) >> BIT_SHIFT_PKT_NUM_Q1_V1) & BIT_MASK_PKT_NUM_Q1_V1)
#define BIT_SET_PKT_NUM_Q1_V1(x, v)			(BIT_CLEAR_PKT_NUM_Q1_V1(x) | BIT_PKT_NUM_Q1_V1(v))

#define BIT_SHIFT_HEAD_PKT_Q1				0
#define BIT_MASK_HEAD_PKT_Q1				0xff
#define BIT_HEAD_PKT_Q1(x)				(((x) & BIT_MASK_HEAD_PKT_Q1) << BIT_SHIFT_HEAD_PKT_Q1)
#define BITS_HEAD_PKT_Q1				(BIT_MASK_HEAD_PKT_Q1 << BIT_SHIFT_HEAD_PKT_Q1)
#define BIT_CLEAR_HEAD_PKT_Q1(x)			((x) & (~BITS_HEAD_PKT_Q1))
#define BIT_GET_HEAD_PKT_Q1(x)				(((x) >> BIT_SHIFT_HEAD_PKT_Q1) & BIT_MASK_HEAD_PKT_Q1)
#define BIT_SET_HEAD_PKT_Q1(x, v)			(BIT_CLEAR_HEAD_PKT_Q1(x) | BIT_HEAD_PKT_Q1(v))

/* 2 REG_Q2_INFO				(Offset 0x0408) */

#define BIT_SHIFT_QUEUEMACID_Q2_V1			25
#define BIT_MASK_QUEUEMACID_Q2_V1			0x7f
#define BIT_QUEUEMACID_Q2_V1(x)			(((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1)
#define BITS_QUEUEMACID_Q2_V1				(BIT_MASK_QUEUEMACID_Q2_V1 << BIT_SHIFT_QUEUEMACID_Q2_V1)
#define BIT_CLEAR_QUEUEMACID_Q2_V1(x)			((x) & (~BITS_QUEUEMACID_Q2_V1))
#define BIT_GET_QUEUEMACID_Q2_V1(x)			(((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1)
#define BIT_SET_QUEUEMACID_Q2_V1(x, v)			(BIT_CLEAR_QUEUEMACID_Q2_V1(x) | BIT_QUEUEMACID_Q2_V1(v))

#define BIT_SHIFT_QUEUEAC_Q2_V1			23
#define BIT_MASK_QUEUEAC_Q2_V1				0x3
#define BIT_QUEUEAC_Q2_V1(x)				(((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1)
#define BITS_QUEUEAC_Q2_V1				(BIT_MASK_QUEUEAC_Q2_V1 << BIT_SHIFT_QUEUEAC_Q2_V1)
#define BIT_CLEAR_QUEUEAC_Q2_V1(x)			((x) & (~BITS_QUEUEAC_Q2_V1))
#define BIT_GET_QUEUEAC_Q2_V1(x)			(((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1)
#define BIT_SET_QUEUEAC_Q2_V1(x, v)			(BIT_CLEAR_QUEUEAC_Q2_V1(x) | BIT_QUEUEAC_Q2_V1(v))

#define BIT_SHIFT_TAIL_PKT_Q2_V1			15
#define BIT_MASK_TAIL_PKT_Q2_V1			0xff
#define BIT_TAIL_PKT_Q2_V1(x)				(((x) & BIT_MASK_TAIL_PKT_Q2_V1) << BIT_SHIFT_TAIL_PKT_Q2_V1)
#define BITS_TAIL_PKT_Q2_V1				(BIT_MASK_TAIL_PKT_Q2_V1 << BIT_SHIFT_TAIL_PKT_Q2_V1)
#define BIT_CLEAR_TAIL_PKT_Q2_V1(x)			((x) & (~BITS_TAIL_PKT_Q2_V1))
#define BIT_GET_TAIL_PKT_Q2_V1(x)			(((x) >> BIT_SHIFT_TAIL_PKT_Q2_V1) & BIT_MASK_TAIL_PKT_Q2_V1)
#define BIT_SET_TAIL_PKT_Q2_V1(x, v)			(BIT_CLEAR_TAIL_PKT_Q2_V1(x) | BIT_TAIL_PKT_Q2_V1(v))

#define BIT_SHIFT_PKT_NUM_Q2_V1			8
#define BIT_MASK_PKT_NUM_Q2_V1				0x7f
#define BIT_PKT_NUM_Q2_V1(x)				(((x) & BIT_MASK_PKT_NUM_Q2_V1) << BIT_SHIFT_PKT_NUM_Q2_V1)
#define BITS_PKT_NUM_Q2_V1				(BIT_MASK_PKT_NUM_Q2_V1 << BIT_SHIFT_PKT_NUM_Q2_V1)
#define BIT_CLEAR_PKT_NUM_Q2_V1(x)			((x) & (~BITS_PKT_NUM_Q2_V1))
#define BIT_GET_PKT_NUM_Q2_V1(x)			(((x) >> BIT_SHIFT_PKT_NUM_Q2_V1) & BIT_MASK_PKT_NUM_Q2_V1)
#define BIT_SET_PKT_NUM_Q2_V1(x, v)			(BIT_CLEAR_PKT_NUM_Q2_V1(x) | BIT_PKT_NUM_Q2_V1(v))

#define BIT_SHIFT_HEAD_PKT_Q2				0
#define BIT_MASK_HEAD_PKT_Q2				0xff
#define BIT_HEAD_PKT_Q2(x)				(((x) & BIT_MASK_HEAD_PKT_Q2) << BIT_SHIFT_HEAD_PKT_Q2)
#define BITS_HEAD_PKT_Q2				(BIT_MASK_HEAD_PKT_Q2 << BIT_SHIFT_HEAD_PKT_Q2)
#define BIT_CLEAR_HEAD_PKT_Q2(x)			((x) & (~BITS_HEAD_PKT_Q2))
#define BIT_GET_HEAD_PKT_Q2(x)				(((x) >> BIT_SHIFT_HEAD_PKT_Q2) & BIT_MASK_HEAD_PKT_Q2)
#define BIT_SET_HEAD_PKT_Q2(x, v)			(BIT_CLEAR_HEAD_PKT_Q2(x) | BIT_HEAD_PKT_Q2(v))

/* 2 REG_Q3_INFO				(Offset 0x040C) */

#define BIT_SHIFT_QUEUEMACID_Q3_V1			25
#define BIT_MASK_QUEUEMACID_Q3_V1			0x7f
#define BIT_QUEUEMACID_Q3_V1(x)			(((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1)
#define BITS_QUEUEMACID_Q3_V1				(BIT_MASK_QUEUEMACID_Q3_V1 << BIT_SHIFT_QUEUEMACID_Q3_V1)
#define BIT_CLEAR_QUEUEMACID_Q3_V1(x)			((x) & (~BITS_QUEUEMACID_Q3_V1))
#define BIT_GET_QUEUEMACID_Q3_V1(x)			(((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1)
#define BIT_SET_QUEUEMACID_Q3_V1(x, v)			(BIT_CLEAR_QUEUEMACID_Q3_V1(x) | BIT_QUEUEMACID_Q3_V1(v))

#define BIT_SHIFT_QUEUEAC_Q3_V1			23
#define BIT_MASK_QUEUEAC_Q3_V1				0x3
#define BIT_QUEUEAC_Q3_V1(x)				(((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1)
#define BITS_QUEUEAC_Q3_V1				(BIT_MASK_QUEUEAC_Q3_V1 << BIT_SHIFT_QUEUEAC_Q3_V1)
#define BIT_CLEAR_QUEUEAC_Q3_V1(x)			((x) & (~BITS_QUEUEAC_Q3_V1))
#define BIT_GET_QUEUEAC_Q3_V1(x)			(((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1)
#define BIT_SET_QUEUEAC_Q3_V1(x, v)			(BIT_CLEAR_QUEUEAC_Q3_V1(x) | BIT_QUEUEAC_Q3_V1(v))

#define BIT_SHIFT_TAIL_PKT_Q3_V1			15
#define BIT_MASK_TAIL_PKT_Q3_V1			0xff
#define BIT_TAIL_PKT_Q3_V1(x)				(((x) & BIT_MASK_TAIL_PKT_Q3_V1) << BIT_SHIFT_TAIL_PKT_Q3_V1)
#define BITS_TAIL_PKT_Q3_V1				(BIT_MASK_TAIL_PKT_Q3_V1 << BIT_SHIFT_TAIL_PKT_Q3_V1)
#define BIT_CLEAR_TAIL_PKT_Q3_V1(x)			((x) & (~BITS_TAIL_PKT_Q3_V1))
#define BIT_GET_TAIL_PKT_Q3_V1(x)			(((x) >> BIT_SHIFT_TAIL_PKT_Q3_V1) & BIT_MASK_TAIL_PKT_Q3_V1)
#define BIT_SET_TAIL_PKT_Q3_V1(x, v)			(BIT_CLEAR_TAIL_PKT_Q3_V1(x) | BIT_TAIL_PKT_Q3_V1(v))

#define BIT_SHIFT_PKT_NUM_Q3_V1			8
#define BIT_MASK_PKT_NUM_Q3_V1				0x7f
#define BIT_PKT_NUM_Q3_V1(x)				(((x) & BIT_MASK_PKT_NUM_Q3_V1) << BIT_SHIFT_PKT_NUM_Q3_V1)
#define BITS_PKT_NUM_Q3_V1				(BIT_MASK_PKT_NUM_Q3_V1 << BIT_SHIFT_PKT_NUM_Q3_V1)
#define BIT_CLEAR_PKT_NUM_Q3_V1(x)			((x) & (~BITS_PKT_NUM_Q3_V1))
#define BIT_GET_PKT_NUM_Q3_V1(x)			(((x) >> BIT_SHIFT_PKT_NUM_Q3_V1) & BIT_MASK_PKT_NUM_Q3_V1)
#define BIT_SET_PKT_NUM_Q3_V1(x, v)			(BIT_CLEAR_PKT_NUM_Q3_V1(x) | BIT_PKT_NUM_Q3_V1(v))

#define BIT_SHIFT_HEAD_PKT_Q3				0
#define BIT_MASK_HEAD_PKT_Q3				0xff
#define BIT_HEAD_PKT_Q3(x)				(((x) & BIT_MASK_HEAD_PKT_Q3) << BIT_SHIFT_HEAD_PKT_Q3)
#define BITS_HEAD_PKT_Q3				(BIT_MASK_HEAD_PKT_Q3 << BIT_SHIFT_HEAD_PKT_Q3)
#define BIT_CLEAR_HEAD_PKT_Q3(x)			((x) & (~BITS_HEAD_PKT_Q3))
#define BIT_GET_HEAD_PKT_Q3(x)				(((x) >> BIT_SHIFT_HEAD_PKT_Q3) & BIT_MASK_HEAD_PKT_Q3)
#define BIT_SET_HEAD_PKT_Q3(x, v)			(BIT_CLEAR_HEAD_PKT_Q3(x) | BIT_HEAD_PKT_Q3(v))

/* 2 REG_MGQ_INFO				(Offset 0x0410) */

#define BIT_SHIFT_QUEUEMACID_MGQ_V1			25
#define BIT_MASK_QUEUEMACID_MGQ_V1			0x7f
#define BIT_QUEUEMACID_MGQ_V1(x)			(((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1)
#define BITS_QUEUEMACID_MGQ_V1				(BIT_MASK_QUEUEMACID_MGQ_V1 << BIT_SHIFT_QUEUEMACID_MGQ_V1)
#define BIT_CLEAR_QUEUEMACID_MGQ_V1(x)			((x) & (~BITS_QUEUEMACID_MGQ_V1))
#define BIT_GET_QUEUEMACID_MGQ_V1(x)			(((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1)
#define BIT_SET_QUEUEMACID_MGQ_V1(x, v)		(BIT_CLEAR_QUEUEMACID_MGQ_V1(x) | BIT_QUEUEMACID_MGQ_V1(v))

#define BIT_SHIFT_QUEUEAC_MGQ_V1			23
#define BIT_MASK_QUEUEAC_MGQ_V1			0x3
#define BIT_QUEUEAC_MGQ_V1(x)				(((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1)
#define BITS_QUEUEAC_MGQ_V1				(BIT_MASK_QUEUEAC_MGQ_V1 << BIT_SHIFT_QUEUEAC_MGQ_V1)
#define BIT_CLEAR_QUEUEAC_MGQ_V1(x)			((x) & (~BITS_QUEUEAC_MGQ_V1))
#define BIT_GET_QUEUEAC_MGQ_V1(x)			(((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1)
#define BIT_SET_QUEUEAC_MGQ_V1(x, v)			(BIT_CLEAR_QUEUEAC_MGQ_V1(x) | BIT_QUEUEAC_MGQ_V1(v))

#define BIT_SHIFT_TAIL_PKT_MGQ_V1			15
#define BIT_MASK_TAIL_PKT_MGQ_V1			0xff
#define BIT_TAIL_PKT_MGQ_V1(x)				(((x) & BIT_MASK_TAIL_PKT_MGQ_V1) << BIT_SHIFT_TAIL_PKT_MGQ_V1)
#define BITS_TAIL_PKT_MGQ_V1				(BIT_MASK_TAIL_PKT_MGQ_V1 << BIT_SHIFT_TAIL_PKT_MGQ_V1)
#define BIT_CLEAR_TAIL_PKT_MGQ_V1(x)			((x) & (~BITS_TAIL_PKT_MGQ_V1))
#define BIT_GET_TAIL_PKT_MGQ_V1(x)			(((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V1) & BIT_MASK_TAIL_PKT_MGQ_V1)
#define BIT_SET_TAIL_PKT_MGQ_V1(x, v)			(BIT_CLEAR_TAIL_PKT_MGQ_V1(x) | BIT_TAIL_PKT_MGQ_V1(v))

#define BIT_SHIFT_PKT_NUM_MGQ_V1			8
#define BIT_MASK_PKT_NUM_MGQ_V1			0x7f
#define BIT_PKT_NUM_MGQ_V1(x)				(((x) & BIT_MASK_PKT_NUM_MGQ_V1) << BIT_SHIFT_PKT_NUM_MGQ_V1)
#define BITS_PKT_NUM_MGQ_V1				(BIT_MASK_PKT_NUM_MGQ_V1 << BIT_SHIFT_PKT_NUM_MGQ_V1)
#define BIT_CLEAR_PKT_NUM_MGQ_V1(x)			((x) & (~BITS_PKT_NUM_MGQ_V1))
#define BIT_GET_PKT_NUM_MGQ_V1(x)			(((x) >> BIT_SHIFT_PKT_NUM_MGQ_V1) & BIT_MASK_PKT_NUM_MGQ_V1)
#define BIT_SET_PKT_NUM_MGQ_V1(x, v)			(BIT_CLEAR_PKT_NUM_MGQ_V1(x) | BIT_PKT_NUM_MGQ_V1(v))

#define BIT_SHIFT_HEAD_PKT_MGQ				0
#define BIT_MASK_HEAD_PKT_MGQ				0xff
#define BIT_HEAD_PKT_MGQ(x)				(((x) & BIT_MASK_HEAD_PKT_MGQ) << BIT_SHIFT_HEAD_PKT_MGQ)
#define BITS_HEAD_PKT_MGQ				(BIT_MASK_HEAD_PKT_MGQ << BIT_SHIFT_HEAD_PKT_MGQ)
#define BIT_CLEAR_HEAD_PKT_MGQ(x)			((x) & (~BITS_HEAD_PKT_MGQ))
#define BIT_GET_HEAD_PKT_MGQ(x)			(((x) >> BIT_SHIFT_HEAD_PKT_MGQ) & BIT_MASK_HEAD_PKT_MGQ)
#define BIT_SET_HEAD_PKT_MGQ(x, v)			(BIT_CLEAR_HEAD_PKT_MGQ(x) | BIT_HEAD_PKT_MGQ(v))

/* 2 REG_HIQ_INFO				(Offset 0x0414) */

#define BIT_SHIFT_QUEUEMACID_HIQ_V1			25
#define BIT_MASK_QUEUEMACID_HIQ_V1			0x7f
#define BIT_QUEUEMACID_HIQ_V1(x)			(((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1)
#define BITS_QUEUEMACID_HIQ_V1				(BIT_MASK_QUEUEMACID_HIQ_V1 << BIT_SHIFT_QUEUEMACID_HIQ_V1)
#define BIT_CLEAR_QUEUEMACID_HIQ_V1(x)			((x) & (~BITS_QUEUEMACID_HIQ_V1))
#define BIT_GET_QUEUEMACID_HIQ_V1(x)			(((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1)
#define BIT_SET_QUEUEMACID_HIQ_V1(x, v)		(BIT_CLEAR_QUEUEMACID_HIQ_V1(x) | BIT_QUEUEMACID_HIQ_V1(v))

#define BIT_SHIFT_QUEUEAC_HIQ_V1			23
#define BIT_MASK_QUEUEAC_HIQ_V1			0x3
#define BIT_QUEUEAC_HIQ_V1(x)				(((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1)
#define BITS_QUEUEAC_HIQ_V1				(BIT_MASK_QUEUEAC_HIQ_V1 << BIT_SHIFT_QUEUEAC_HIQ_V1)
#define BIT_CLEAR_QUEUEAC_HIQ_V1(x)			((x) & (~BITS_QUEUEAC_HIQ_V1))
#define BIT_GET_QUEUEAC_HIQ_V1(x)			(((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1)
#define BIT_SET_QUEUEAC_HIQ_V1(x, v)			(BIT_CLEAR_QUEUEAC_HIQ_V1(x) | BIT_QUEUEAC_HIQ_V1(v))

#define BIT_SHIFT_TAIL_PKT_HIQ_V1			15
#define BIT_MASK_TAIL_PKT_HIQ_V1			0xff
#define BIT_TAIL_PKT_HIQ_V1(x)				(((x) & BIT_MASK_TAIL_PKT_HIQ_V1) << BIT_SHIFT_TAIL_PKT_HIQ_V1)
#define BITS_TAIL_PKT_HIQ_V1				(BIT_MASK_TAIL_PKT_HIQ_V1 << BIT_SHIFT_TAIL_PKT_HIQ_V1)
#define BIT_CLEAR_TAIL_PKT_HIQ_V1(x)			((x) & (~BITS_TAIL_PKT_HIQ_V1))
#define BIT_GET_TAIL_PKT_HIQ_V1(x)			(((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V1) & BIT_MASK_TAIL_PKT_HIQ_V1)
#define BIT_SET_TAIL_PKT_HIQ_V1(x, v)			(BIT_CLEAR_TAIL_PKT_HIQ_V1(x) | BIT_TAIL_PKT_HIQ_V1(v))

#define BIT_SHIFT_PKT_NUM_HIQ_V1			8
#define BIT_MASK_PKT_NUM_HIQ_V1			0x7f
#define BIT_PKT_NUM_HIQ_V1(x)				(((x) & BIT_MASK_PKT_NUM_HIQ_V1) << BIT_SHIFT_PKT_NUM_HIQ_V1)
#define BITS_PKT_NUM_HIQ_V1				(BIT_MASK_PKT_NUM_HIQ_V1 << BIT_SHIFT_PKT_NUM_HIQ_V1)
#define BIT_CLEAR_PKT_NUM_HIQ_V1(x)			((x) & (~BITS_PKT_NUM_HIQ_V1))
#define BIT_GET_PKT_NUM_HIQ_V1(x)			(((x) >> BIT_SHIFT_PKT_NUM_HIQ_V1) & BIT_MASK_PKT_NUM_HIQ_V1)
#define BIT_SET_PKT_NUM_HIQ_V1(x, v)			(BIT_CLEAR_PKT_NUM_HIQ_V1(x) | BIT_PKT_NUM_HIQ_V1(v))

#define BIT_SHIFT_HEAD_PKT_HIQ				0
#define BIT_MASK_HEAD_PKT_HIQ				0xff
#define BIT_HEAD_PKT_HIQ(x)				(((x) & BIT_MASK_HEAD_PKT_HIQ) << BIT_SHIFT_HEAD_PKT_HIQ)
#define BITS_HEAD_PKT_HIQ				(BIT_MASK_HEAD_PKT_HIQ << BIT_SHIFT_HEAD_PKT_HIQ)
#define BIT_CLEAR_HEAD_PKT_HIQ(x)			((x) & (~BITS_HEAD_PKT_HIQ))
#define BIT_GET_HEAD_PKT_HIQ(x)			(((x) >> BIT_SHIFT_HEAD_PKT_HIQ) & BIT_MASK_HEAD_PKT_HIQ)
#define BIT_SET_HEAD_PKT_HIQ(x, v)			(BIT_CLEAR_HEAD_PKT_HIQ(x) | BIT_HEAD_PKT_HIQ(v))

/* 2 REG_BCNQ_INFO				(Offset 0x0418) */

#define BIT_SHIFT_PKT_NUM_BCNQ				8
#define BIT_MASK_PKT_NUM_BCNQ				0xff
#define BIT_PKT_NUM_BCNQ(x)				(((x) & BIT_MASK_PKT_NUM_BCNQ) << BIT_SHIFT_PKT_NUM_BCNQ)
#define BITS_PKT_NUM_BCNQ				(BIT_MASK_PKT_NUM_BCNQ << BIT_SHIFT_PKT_NUM_BCNQ)
#define BIT_CLEAR_PKT_NUM_BCNQ(x)			((x) & (~BITS_PKT_NUM_BCNQ))
#define BIT_GET_PKT_NUM_BCNQ(x)			(((x) >> BIT_SHIFT_PKT_NUM_BCNQ) & BIT_MASK_PKT_NUM_BCNQ)
#define BIT_SET_PKT_NUM_BCNQ(x, v)			(BIT_CLEAR_PKT_NUM_BCNQ(x) | BIT_PKT_NUM_BCNQ(v))

#define BIT_SHIFT_BCNQ_HEAD_PG				0
#define BIT_MASK_BCNQ_HEAD_PG				0xff
#define BIT_BCNQ_HEAD_PG(x)				(((x) & BIT_MASK_BCNQ_HEAD_PG) << BIT_SHIFT_BCNQ_HEAD_PG)
#define BITS_BCNQ_HEAD_PG				(BIT_MASK_BCNQ_HEAD_PG << BIT_SHIFT_BCNQ_HEAD_PG)
#define BIT_CLEAR_BCNQ_HEAD_PG(x)			((x) & (~BITS_BCNQ_HEAD_PG))
#define BIT_GET_BCNQ_HEAD_PG(x)			(((x) >> BIT_SHIFT_BCNQ_HEAD_PG) & BIT_MASK_BCNQ_HEAD_PG)
#define BIT_SET_BCNQ_HEAD_PG(x, v)			(BIT_CLEAR_BCNQ_HEAD_PG(x) | BIT_BCNQ_HEAD_PG(v))

/* 2 REG_TXPKT_EMPTY				(Offset 0x041A) */

#define BIT_BCNQ_EMPTY					BIT(11)
#define BIT_HQQ_EMPTY					BIT(10)
#define BIT_MQQ_EMPTY					BIT(9)
#define BIT_MGQ_CPU_EMPTY				BIT(8)
#define BIT_AC7Q_EMPTY					BIT(7)
#define BIT_AC6Q_EMPTY					BIT(6)
#define BIT_AC5Q_EMPTY					BIT(5)
#define BIT_AC4Q_EMPTY					BIT(4)
#define BIT_AC3Q_EMPTY					BIT(3)
#define BIT_AC2Q_EMPTY					BIT(2)
#define BIT_AC1Q_EMPTY					BIT(1)
#define BIT_AC0Q_EMPTY					BIT(0)

/* 2 REG_CPU_MGQ_INFO			(Offset 0x041C) */

#define BIT_BCN_POLL2					BIT(31)
#define BIT_BCN_POLL1					BIT(30)
#define BIT_CPUMGT_POLL_SET				BIT(29)
#define BIT_BCN_POLL					BIT(28)
#define BIT_CPUMGT_POLL_CLR				BIT(27)
#define BIT_CPUMGQ_FW_NUM				BIT(8)

#define BIT_SHIFT_CPUMGQ_HEAD_PG			0
#define BIT_MASK_CPUMGQ_HEAD_PG			0xff
#define BIT_CPUMGQ_HEAD_PG(x)				(((x) & BIT_MASK_CPUMGQ_HEAD_PG) << BIT_SHIFT_CPUMGQ_HEAD_PG)
#define BITS_CPUMGQ_HEAD_PG				(BIT_MASK_CPUMGQ_HEAD_PG << BIT_SHIFT_CPUMGQ_HEAD_PG)
#define BIT_CLEAR_CPUMGQ_HEAD_PG(x)			((x) & (~BITS_CPUMGQ_HEAD_PG))
#define BIT_GET_CPUMGQ_HEAD_PG(x)			(((x) >> BIT_SHIFT_CPUMGQ_HEAD_PG) & BIT_MASK_CPUMGQ_HEAD_PG)
#define BIT_SET_CPUMGQ_HEAD_PG(x, v)			(BIT_CLEAR_CPUMGQ_HEAD_PG(x) | BIT_CPUMGQ_HEAD_PG(v))

/* 2 REG_FWHW_TXQ_CTRL			(Offset 0x0420) */

#define BIT_RTS_LIMIT_IN_OFDM				BIT(23)
#define BIT_EN_BCNQ_DL					BIT(22)
#define BIT_EN_RD_RESP_NAV_BK				BIT(21)
#define BIT_EN_WR_FREE_TAIL				BIT(20)
#define BIT_TXRPT_DIS					BIT(19)
#define BIT_TXFAILRPT_DIS				BIT(18)
#define BIT_EN_RTY_BC					BIT(17)
#define BIT_EN_RTY_BK_COND				BIT(16)

#define BIT_SHIFT_EN_QUEUE_RPT				8
#define BIT_MASK_EN_QUEUE_RPT				0xff
#define BIT_EN_QUEUE_RPT(x)				(((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT)
#define BITS_EN_QUEUE_RPT				(BIT_MASK_EN_QUEUE_RPT << BIT_SHIFT_EN_QUEUE_RPT)
#define BIT_CLEAR_EN_QUEUE_RPT(x)			((x) & (~BITS_EN_QUEUE_RPT))
#define BIT_GET_EN_QUEUE_RPT(x)			(((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT)
#define BIT_SET_EN_QUEUE_RPT(x, v)			(BIT_CLEAR_EN_QUEUE_RPT(x) | BIT_EN_QUEUE_RPT(v))

#define BIT_EN_RTY_BK					BIT(7)
#define BIT_EN_USE_INI_RAT				BIT(6)
#define BIT_EN_RTS_NAV_BK				BIT(5)
#define BIT_DIS_SSN_CHECK				BIT(4)
#define BIT_MACID_MATCH_RTS				BIT(3)
#define BIT_EN_BCN_TRXRPT				BIT(2)
#define BIT_EN_FTM_RPT					BIT(1)
#define BIT_PROTECT_BMC_NAV				BIT(0)

/* 2 REG_HWSEQ_CTRL				(Offset 0x0423) */

#define BIT_SHIFT_HW_SSN_EN				0
#define BIT_MASK_HW_SSN_EN				0xff
#define BIT_HW_SSN_EN(x)				(((x) & BIT_MASK_HW_SSN_EN) << BIT_SHIFT_HW_SSN_EN)
#define BITS_HW_SSN_EN					(BIT_MASK_HW_SSN_EN << BIT_SHIFT_HW_SSN_EN)
#define BIT_CLEAR_HW_SSN_EN(x)				((x) & (~BITS_HW_SSN_EN))
#define BIT_GET_HW_SSN_EN(x)				(((x) >> BIT_SHIFT_HW_SSN_EN) & BIT_MASK_HW_SSN_EN)
#define BIT_SET_HW_SSN_EN(x, v)			(BIT_CLEAR_HW_SSN_EN(x) | BIT_HW_SSN_EN(v))

/* 2 REG_BCNQ_BDNY				(Offset 0x0424) */

#define BIT_SHIFT_MGQ_PGBNDY				8
#define BIT_MASK_MGQ_PGBNDY				0xff
#define BIT_MGQ_PGBNDY(x)				(((x) & BIT_MASK_MGQ_PGBNDY) << BIT_SHIFT_MGQ_PGBNDY)
#define BITS_MGQ_PGBNDY				(BIT_MASK_MGQ_PGBNDY << BIT_SHIFT_MGQ_PGBNDY)
#define BIT_CLEAR_MGQ_PGBNDY(x)			((x) & (~BITS_MGQ_PGBNDY))
#define BIT_GET_MGQ_PGBNDY(x)				(((x) >> BIT_SHIFT_MGQ_PGBNDY) & BIT_MASK_MGQ_PGBNDY)
#define BIT_SET_MGQ_PGBNDY(x, v)			(BIT_CLEAR_MGQ_PGBNDY(x) | BIT_MGQ_PGBNDY(v))

#define BIT_SHIFT_BCNQ_PGBNDY				0
#define BIT_MASK_BCNQ_PGBNDY				0xff
#define BIT_BCNQ_PGBNDY(x)				(((x) & BIT_MASK_BCNQ_PGBNDY) << BIT_SHIFT_BCNQ_PGBNDY)
#define BITS_BCNQ_PGBNDY				(BIT_MASK_BCNQ_PGBNDY << BIT_SHIFT_BCNQ_PGBNDY)
#define BIT_CLEAR_BCNQ_PGBNDY(x)			((x) & (~BITS_BCNQ_PGBNDY))
#define BIT_GET_BCNQ_PGBNDY(x)				(((x) >> BIT_SHIFT_BCNQ_PGBNDY) & BIT_MASK_BCNQ_PGBNDY)
#define BIT_SET_BCNQ_PGBNDY(x, v)			(BIT_CLEAR_BCNQ_PGBNDY(x) | BIT_BCNQ_PGBNDY(v))

/* 2 REG_LIFETIME_EN				(Offset 0x0426) */

#define BIT_SHIFT_BT_INT_TYPE				6
#define BIT_MASK_BT_INT_TYPE				0x3
#define BIT_BT_INT_TYPE(x)				(((x) & BIT_MASK_BT_INT_TYPE) << BIT_SHIFT_BT_INT_TYPE)
#define BITS_BT_INT_TYPE				(BIT_MASK_BT_INT_TYPE << BIT_SHIFT_BT_INT_TYPE)
#define BIT_CLEAR_BT_INT_TYPE(x)			((x) & (~BITS_BT_INT_TYPE))
#define BIT_GET_BT_INT_TYPE(x)				(((x) >> BIT_SHIFT_BT_INT_TYPE) & BIT_MASK_BT_INT_TYPE)
#define BIT_SET_BT_INT_TYPE(x, v)			(BIT_CLEAR_BT_INT_TYPE(x) | BIT_BT_INT_TYPE(v))

#define BIT_RTYBIT_CTRL_EN				BIT(4)
#define BIT_LIFETIME_BK_EN				BIT(3)
#define BIT_LIFETIME_BE_EN				BIT(2)
#define BIT_LIFETIME_VI_EN				BIT(1)
#define BIT_LIFETIME_VO_EN				BIT(0)

/* 2 REG_FW_FREE_TAIL			(Offset 0x0427) */

#define BIT_SHIFT_FW_FREE_TAIL				0
#define BIT_MASK_FW_FREE_TAIL				0xff
#define BIT_FW_FREE_TAIL(x)				(((x) & BIT_MASK_FW_FREE_TAIL) << BIT_SHIFT_FW_FREE_TAIL)
#define BITS_FW_FREE_TAIL				(BIT_MASK_FW_FREE_TAIL << BIT_SHIFT_FW_FREE_TAIL)
#define BIT_CLEAR_FW_FREE_TAIL(x)			((x) & (~BITS_FW_FREE_TAIL))
#define BIT_GET_FW_FREE_TAIL(x)			(((x) >> BIT_SHIFT_FW_FREE_TAIL) & BIT_MASK_FW_FREE_TAIL)
#define BIT_SET_FW_FREE_TAIL(x, v)			(BIT_CLEAR_FW_FREE_TAIL(x) | BIT_FW_FREE_TAIL(v))

/* 2 REG_SPEC_SIFS				(Offset 0x0428) */

#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL			8
#define BIT_MASK_SPEC_SIFS_OFDM_PTCL			0xff
#define BIT_SPEC_SIFS_OFDM_PTCL(x)			(((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL)
#define BITS_SPEC_SIFS_OFDM_PTCL			(BIT_MASK_SPEC_SIFS_OFDM_PTCL << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL)
#define BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x)		((x) & (~BITS_SPEC_SIFS_OFDM_PTCL))
#define BIT_GET_SPEC_SIFS_OFDM_PTCL(x)			(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL)
#define BIT_SET_SPEC_SIFS_OFDM_PTCL(x, v)		(BIT_CLEAR_SPEC_SIFS_OFDM_PTCL(x) | BIT_SPEC_SIFS_OFDM_PTCL(v))

#define BIT_SHIFT_SRL					8
#define BIT_MASK_SRL					0x3f
#define BIT_SRL(x)					(((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL)
#define BITS_SRL					(BIT_MASK_SRL << BIT_SHIFT_SRL)
#define BIT_CLEAR_SRL(x)				((x) & (~BITS_SRL))
#define BIT_GET_SRL(x)					(((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL)
#define BIT_SET_SRL(x, v)				(BIT_CLEAR_SRL(x) | BIT_SRL(v))

#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL			0
#define BIT_MASK_SPEC_SIFS_CCK_PTCL			0xff
#define BIT_SPEC_SIFS_CCK_PTCL(x)			(((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL)
#define BITS_SPEC_SIFS_CCK_PTCL			(BIT_MASK_SPEC_SIFS_CCK_PTCL << BIT_SHIFT_SPEC_SIFS_CCK_PTCL)
#define BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x)		((x) & (~BITS_SPEC_SIFS_CCK_PTCL))
#define BIT_GET_SPEC_SIFS_CCK_PTCL(x)			(((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL)
#define BIT_SET_SPEC_SIFS_CCK_PTCL(x, v)		(BIT_CLEAR_SPEC_SIFS_CCK_PTCL(x) | BIT_SPEC_SIFS_CCK_PTCL(v))

#define BIT_SHIFT_LRL					0
#define BIT_MASK_LRL					0x3f
#define BIT_LRL(x)					(((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL)
#define BITS_LRL					(BIT_MASK_LRL << BIT_SHIFT_LRL)
#define BIT_CLEAR_LRL(x)				((x) & (~BITS_LRL))
#define BIT_GET_LRL(x)					(((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL)
#define BIT_SET_LRL(x, v)				(BIT_CLEAR_LRL(x) | BIT_LRL(v))

/* 2 REG_TXBF_CTRL				(Offset 0x042C) */

#define BIT_R_ENABLE_NDPA				BIT(31)
#define BIT_USE_NDPA_PARAMETER				BIT(30)
#define BIT_R_PROP_TXBF				BIT(29)
#define BIT_R_EN_NDPA_INT				BIT(28)
#define BIT_R_TXBF1_80M				BIT(27)
#define BIT_R_TXBF1_40M				BIT(26)
#define BIT_R_TXBF1_20M				BIT(25)

#define BIT_SHIFT_R_TXBF1_AID				16
#define BIT_MASK_R_TXBF1_AID				0x1ff
#define BIT_R_TXBF1_AID(x)				(((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID)
#define BITS_R_TXBF1_AID				(BIT_MASK_R_TXBF1_AID << BIT_SHIFT_R_TXBF1_AID)
#define BIT_CLEAR_R_TXBF1_AID(x)			((x) & (~BITS_R_TXBF1_AID))
#define BIT_GET_R_TXBF1_AID(x)				(((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID)
#define BIT_SET_R_TXBF1_AID(x, v)			(BIT_CLEAR_R_TXBF1_AID(x) | BIT_R_TXBF1_AID(v))

#define BIT_NDP_BFEN_DIS				BIT(15)
#define BIT_BCN_NOBLOCK_NDP				BIT(14)
#define BIT_R_TXBF0_80M				BIT(11)
#define BIT_R_TXBF0_40M				BIT(10)
#define BIT_R_TXBF0_20M				BIT(9)

#define BIT_SHIFT_R_TXBF0_AID				0
#define BIT_MASK_R_TXBF0_AID				0x1ff
#define BIT_R_TXBF0_AID(x)				(((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID)
#define BITS_R_TXBF0_AID				(BIT_MASK_R_TXBF0_AID << BIT_SHIFT_R_TXBF0_AID)
#define BIT_CLEAR_R_TXBF0_AID(x)			((x) & (~BITS_R_TXBF0_AID))
#define BIT_GET_R_TXBF0_AID(x)				(((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID)
#define BIT_SET_R_TXBF0_AID(x, v)			(BIT_CLEAR_R_TXBF0_AID(x) | BIT_R_TXBF0_AID(v))

/* 2 REG_DARFRC				(Offset 0x0430) */

#define BIT_SHIFT_DATA_FALLBACK_RC4			24
#define BIT_MASK_DATA_FALLBACK_RC4			0x1f
#define BIT_DATA_FALLBACK_RC4(x)			(((x) & BIT_MASK_DATA_FALLBACK_RC4) << BIT_SHIFT_DATA_FALLBACK_RC4)
#define BITS_DATA_FALLBACK_RC4				(BIT_MASK_DATA_FALLBACK_RC4 << BIT_SHIFT_DATA_FALLBACK_RC4)
#define BIT_CLEAR_DATA_FALLBACK_RC4(x)			((x) & (~BITS_DATA_FALLBACK_RC4))
#define BIT_GET_DATA_FALLBACK_RC4(x)			(((x) >> BIT_SHIFT_DATA_FALLBACK_RC4) & BIT_MASK_DATA_FALLBACK_RC4)
#define BIT_SET_DATA_FALLBACK_RC4(x, v)		(BIT_CLEAR_DATA_FALLBACK_RC4(x) | BIT_DATA_FALLBACK_RC4(v))

#define BIT_SHIFT_DATA_FALLBACK_RC3			16
#define BIT_MASK_DATA_FALLBACK_RC3			0x1f
#define BIT_DATA_FALLBACK_RC3(x)			(((x) & BIT_MASK_DATA_FALLBACK_RC3) << BIT_SHIFT_DATA_FALLBACK_RC3)
#define BITS_DATA_FALLBACK_RC3				(BIT_MASK_DATA_FALLBACK_RC3 << BIT_SHIFT_DATA_FALLBACK_RC3)
#define BIT_CLEAR_DATA_FALLBACK_RC3(x)			((x) & (~BITS_DATA_FALLBACK_RC3))
#define BIT_GET_DATA_FALLBACK_RC3(x)			(((x) >> BIT_SHIFT_DATA_FALLBACK_RC3) & BIT_MASK_DATA_FALLBACK_RC3)
#define BIT_SET_DATA_FALLBACK_RC3(x, v)		(BIT_CLEAR_DATA_FALLBACK_RC3(x) | BIT_DATA_FALLBACK_RC3(v))

#define BIT_SHIFT_DATA_FALLBACK_RC2			8
#define BIT_MASK_DATA_FALLBACK_RC2			0x1f
#define BIT_DATA_FALLBACK_RC2(x)			(((x) & BIT_MASK_DATA_FALLBACK_RC2) << BIT_SHIFT_DATA_FALLBACK_RC2)
#define BITS_DATA_FALLBACK_RC2				(BIT_MASK_DATA_FALLBACK_RC2 << BIT_SHIFT_DATA_FALLBACK_RC2)
#define BIT_CLEAR_DATA_FALLBACK_RC2(x)			((x) & (~BITS_DATA_FALLBACK_RC2))
#define BIT_GET_DATA_FALLBACK_RC2(x)			(((x) >> BIT_SHIFT_DATA_FALLBACK_RC2) & BIT_MASK_DATA_FALLBACK_RC2)
#define BIT_SET_DATA_FALLBACK_RC2(x, v)		(BIT_CLEAR_DATA_FALLBACK_RC2(x) | BIT_DATA_FALLBACK_RC2(v))

#define BIT_SHIFT_DATA_FALLBACK_RC1			0
#define BIT_MASK_DATA_FALLBACK_RC1			0x1f
#define BIT_DATA_FALLBACK_RC1(x)			(((x) & BIT_MASK_DATA_FALLBACK_RC1) << BIT_SHIFT_DATA_FALLBACK_RC1)
#define BITS_DATA_FALLBACK_RC1				(BIT_MASK_DATA_FALLBACK_RC1 << BIT_SHIFT_DATA_FALLBACK_RC1)
#define BIT_CLEAR_DATA_FALLBACK_RC1(x)			((x) & (~BITS_DATA_FALLBACK_RC1))
#define BIT_GET_DATA_FALLBACK_RC1(x)			(((x) >> BIT_SHIFT_DATA_FALLBACK_RC1) & BIT_MASK_DATA_FALLBACK_RC1)
#define BIT_SET_DATA_FALLBACK_RC1(x, v)		(BIT_CLEAR_DATA_FALLBACK_RC1(x) | BIT_DATA_FALLBACK_RC1(v))

/* 2 REG_DARFRCH				(Offset 0x0434) */

#define BIT_SHIFT_DATA_FALLBACK_RC8			24
#define BIT_MASK_DATA_FALLBACK_RC8			0x1f
#define BIT_DATA_FALLBACK_RC8(x)			(((x) & BIT_MASK_DATA_FALLBACK_RC8) << BIT_SHIFT_DATA_FALLBACK_RC8)
#define BITS_DATA_FALLBACK_RC8				(BIT_MASK_DATA_FALLBACK_RC8 << BIT_SHIFT_DATA_FALLBACK_RC8)
#define BIT_CLEAR_DATA_FALLBACK_RC8(x)			((x) & (~BITS_DATA_FALLBACK_RC8))
#define BIT_GET_DATA_FALLBACK_RC8(x)			(((x) >> BIT_SHIFT_DATA_FALLBACK_RC8) & BIT_MASK_DATA_FALLBACK_RC8)
#define BIT_SET_DATA_FALLBACK_RC8(x, v)		(BIT_CLEAR_DATA_FALLBACK_RC8(x) | BIT_DATA_FALLBACK_RC8(v))

#define BIT_SHIFT_DATA_FALLBACK_RC7			16
#define BIT_MASK_DATA_FALLBACK_RC7			0x1f
#define BIT_DATA_FALLBACK_RC7(x)			(((x) & BIT_MASK_DATA_FALLBACK_RC7) << BIT_SHIFT_DATA_FALLBACK_RC7)
#define BITS_DATA_FALLBACK_RC7				(BIT_MASK_DATA_FALLBACK_RC7 << BIT_SHIFT_DATA_FALLBACK_RC7)
#define BIT_CLEAR_DATA_FALLBACK_RC7(x)			((x) & (~BITS_DATA_FALLBACK_RC7))
#define BIT_GET_DATA_FALLBACK_RC7(x)			(((x) >> BIT_SHIFT_DATA_FALLBACK_RC7) & BIT_MASK_DATA_FALLBACK_RC7)
#define BIT_SET_DATA_FALLBACK_RC7(x, v)		(BIT_CLEAR_DATA_FALLBACK_RC7(x) | BIT_DATA_FALLBACK_RC7(v))

#define BIT_SHIFT_DATA_FALLBACK_RC6			8
#define BIT_MASK_DATA_FALLBACK_RC6			0x1f
#define BIT_DATA_FALLBACK_RC6(x)			(((x) & BIT_MASK_DATA_FALLBACK_RC6) << BIT_SHIFT_DATA_FALLBACK_RC6)
#define BITS_DATA_FALLBACK_RC6				(BIT_MASK_DATA_FALLBACK_RC6 << BIT_SHIFT_DATA_FALLBACK_RC6)
#define BIT_CLEAR_DATA_FALLBACK_RC6(x)			((x) & (~BITS_DATA_FALLBACK_RC6))
#define BIT_GET_DATA_FALLBACK_RC6(x)			(((x) >> BIT_SHIFT_DATA_FALLBACK_RC6) & BIT_MASK_DATA_FALLBACK_RC6)
#define BIT_SET_DATA_FALLBACK_RC6(x, v)		(BIT_CLEAR_DATA_FALLBACK_RC6(x) | BIT_DATA_FALLBACK_RC6(v))

#define BIT_SHIFT_DATA_FALLBACK_RC5			0
#define BIT_MASK_DATA_FALLBACK_RC5			0x1f
#define BIT_DATA_FALLBACK_RC5(x)			(((x) & BIT_MASK_DATA_FALLBACK_RC5) << BIT_SHIFT_DATA_FALLBACK_RC5)
#define BITS_DATA_FALLBACK_RC5				(BIT_MASK_DATA_FALLBACK_RC5 << BIT_SHIFT_DATA_FALLBACK_RC5)
#define BIT_CLEAR_DATA_FALLBACK_RC5(x)			((x) & (~BITS_DATA_FALLBACK_RC5))
#define BIT_GET_DATA_FALLBACK_RC5(x)			(((x) >> BIT_SHIFT_DATA_FALLBACK_RC5) & BIT_MASK_DATA_FALLBACK_RC5)
#define BIT_SET_DATA_FALLBACK_RC5(x, v)		(BIT_CLEAR_DATA_FALLBACK_RC5(x) | BIT_DATA_FALLBACK_RC5(v))

/* 2 REG_RARFRC				(Offset 0x0438) */

#define BIT_SHIFT_CTRL_FALLBACK_RC4			24
#define BIT_MASK_CTRL_FALLBACK_RC4			0x1f
#define BIT_CTRL_FALLBACK_RC4(x)			(((x) & BIT_MASK_CTRL_FALLBACK_RC4) << BIT_SHIFT_CTRL_FALLBACK_RC4)
#define BITS_CTRL_FALLBACK_RC4				(BIT_MASK_CTRL_FALLBACK_RC4 << BIT_SHIFT_CTRL_FALLBACK_RC4)
#define BIT_CLEAR_CTRL_FALLBACK_RC4(x)			((x) & (~BITS_CTRL_FALLBACK_RC4))
#define BIT_GET_CTRL_FALLBACK_RC4(x)			(((x) >> BIT_SHIFT_CTRL_FALLBACK_RC4) & BIT_MASK_CTRL_FALLBACK_RC4)
#define BIT_SET_CTRL_FALLBACK_RC4(x, v)		(BIT_CLEAR_CTRL_FALLBACK_RC4(x) | BIT_CTRL_FALLBACK_RC4(v))

#define BIT_SHIFT_CTRL_FALLBACK_RC3			16
#define BIT_MASK_CTRL_FALLBACK_RC3			0x1f
#define BIT_CTRL_FALLBACK_RC3(x)			(((x) & BIT_MASK_CTRL_FALLBACK_RC3) << BIT_SHIFT_CTRL_FALLBACK_RC3)
#define BITS_CTRL_FALLBACK_RC3				(BIT_MASK_CTRL_FALLBACK_RC3 << BIT_SHIFT_CTRL_FALLBACK_RC3)
#define BIT_CLEAR_CTRL_FALLBACK_RC3(x)			((x) & (~BITS_CTRL_FALLBACK_RC3))
#define BIT_GET_CTRL_FALLBACK_RC3(x)			(((x) >> BIT_SHIFT_CTRL_FALLBACK_RC3) & BIT_MASK_CTRL_FALLBACK_RC3)
#define BIT_SET_CTRL_FALLBACK_RC3(x, v)		(BIT_CLEAR_CTRL_FALLBACK_RC3(x) | BIT_CTRL_FALLBACK_RC3(v))

#define BIT_SHIFT_CTRL_FALLBACK_RC2			8
#define BIT_MASK_CTRL_FALLBACK_RC2			0x1f
#define BIT_CTRL_FALLBACK_RC2(x)			(((x) & BIT_MASK_CTRL_FALLBACK_RC2) << BIT_SHIFT_CTRL_FALLBACK_RC2)
#define BITS_CTRL_FALLBACK_RC2				(BIT_MASK_CTRL_FALLBACK_RC2 << BIT_SHIFT_CTRL_FALLBACK_RC2)
#define BIT_CLEAR_CTRL_FALLBACK_RC2(x)			((x) & (~BITS_CTRL_FALLBACK_RC2))
#define BIT_GET_CTRL_FALLBACK_RC2(x)			(((x) >> BIT_SHIFT_CTRL_FALLBACK_RC2) & BIT_MASK_CTRL_FALLBACK_RC2)
#define BIT_SET_CTRL_FALLBACK_RC2(x, v)		(BIT_CLEAR_CTRL_FALLBACK_RC2(x) | BIT_CTRL_FALLBACK_RC2(v))

#define BIT_SHIFT_CTRL_FALLBACK_RC1			0
#define BIT_MASK_CTRL_FALLBACK_RC1			0x1f
#define BIT_CTRL_FALLBACK_RC1(x)			(((x) & BIT_MASK_CTRL_FALLBACK_RC1) << BIT_SHIFT_CTRL_FALLBACK_RC1)
#define BITS_CTRL_FALLBACK_RC1				(BIT_MASK_CTRL_FALLBACK_RC1 << BIT_SHIFT_CTRL_FALLBACK_RC1)
#define BIT_CLEAR_CTRL_FALLBACK_RC1(x)			((x) & (~BITS_CTRL_FALLBACK_RC1))
#define BIT_GET_CTRL_FALLBACK_RC1(x)			(((x) >> BIT_SHIFT_CTRL_FALLBACK_RC1) & BIT_MASK_CTRL_FALLBACK_RC1)
#define BIT_SET_CTRL_FALLBACK_RC1(x, v)		(BIT_CLEAR_CTRL_FALLBACK_RC1(x) | BIT_CTRL_FALLBACK_RC1(v))

/* 2 REG_RARFRCH				(Offset 0x043C) */

#define BIT_SHIFT_CTRL_FALLBACK_RC8			24
#define BIT_MASK_CTRL_FALLBACK_RC8			0x1f
#define BIT_CTRL_FALLBACK_RC8(x)			(((x) & BIT_MASK_CTRL_FALLBACK_RC8) << BIT_SHIFT_CTRL_FALLBACK_RC8)
#define BITS_CTRL_FALLBACK_RC8				(BIT_MASK_CTRL_FALLBACK_RC8 << BIT_SHIFT_CTRL_FALLBACK_RC8)
#define BIT_CLEAR_CTRL_FALLBACK_RC8(x)			((x) & (~BITS_CTRL_FALLBACK_RC8))
#define BIT_GET_CTRL_FALLBACK_RC8(x)			(((x) >> BIT_SHIFT_CTRL_FALLBACK_RC8) & BIT_MASK_CTRL_FALLBACK_RC8)
#define BIT_SET_CTRL_FALLBACK_RC8(x, v)		(BIT_CLEAR_CTRL_FALLBACK_RC8(x) | BIT_CTRL_FALLBACK_RC8(v))

#define BIT_SHIFT_CTRL_FALLBACK_RC7			16
#define BIT_MASK_CTRL_FALLBACK_RC7			0x1f
#define BIT_CTRL_FALLBACK_RC7(x)			(((x) & BIT_MASK_CTRL_FALLBACK_RC7) << BIT_SHIFT_CTRL_FALLBACK_RC7)
#define BITS_CTRL_FALLBACK_RC7				(BIT_MASK_CTRL_FALLBACK_RC7 << BIT_SHIFT_CTRL_FALLBACK_RC7)
#define BIT_CLEAR_CTRL_FALLBACK_RC7(x)			((x) & (~BITS_CTRL_FALLBACK_RC7))
#define BIT_GET_CTRL_FALLBACK_RC7(x)			(((x) >> BIT_SHIFT_CTRL_FALLBACK_RC7) & BIT_MASK_CTRL_FALLBACK_RC7)
#define BIT_SET_CTRL_FALLBACK_RC7(x, v)		(BIT_CLEAR_CTRL_FALLBACK_RC7(x) | BIT_CTRL_FALLBACK_RC7(v))

#define BIT_SHIFT_CTRL_FALLBACK_RC6			8
#define BIT_MASK_CTRL_FALLBACK_RC6			0x1f
#define BIT_CTRL_FALLBACK_RC6(x)			(((x) & BIT_MASK_CTRL_FALLBACK_RC6) << BIT_SHIFT_CTRL_FALLBACK_RC6)
#define BITS_CTRL_FALLBACK_RC6				(BIT_MASK_CTRL_FALLBACK_RC6 << BIT_SHIFT_CTRL_FALLBACK_RC6)
#define BIT_CLEAR_CTRL_FALLBACK_RC6(x)			((x) & (~BITS_CTRL_FALLBACK_RC6))
#define BIT_GET_CTRL_FALLBACK_RC6(x)			(((x) >> BIT_SHIFT_CTRL_FALLBACK_RC6) & BIT_MASK_CTRL_FALLBACK_RC6)
#define BIT_SET_CTRL_FALLBACK_RC6(x, v)		(BIT_CLEAR_CTRL_FALLBACK_RC6(x) | BIT_CTRL_FALLBACK_RC6(v))

#define BIT_SHIFT_CTRL_FALLBACK_RC5			0
#define BIT_MASK_CTRL_FALLBACK_RC5			0x1f
#define BIT_CTRL_FALLBACK_RC5(x)			(((x) & BIT_MASK_CTRL_FALLBACK_RC5) << BIT_SHIFT_CTRL_FALLBACK_RC5)
#define BITS_CTRL_FALLBACK_RC5				(BIT_MASK_CTRL_FALLBACK_RC5 << BIT_SHIFT_CTRL_FALLBACK_RC5)
#define BIT_CLEAR_CTRL_FALLBACK_RC5(x)			((x) & (~BITS_CTRL_FALLBACK_RC5))
#define BIT_GET_CTRL_FALLBACK_RC5(x)			(((x) >> BIT_SHIFT_CTRL_FALLBACK_RC5) & BIT_MASK_CTRL_FALLBACK_RC5)
#define BIT_SET_CTRL_FALLBACK_RC5(x, v)		(BIT_CLEAR_CTRL_FALLBACK_RC5(x) | BIT_CTRL_FALLBACK_RC5(v))

/* 2 REG_RRSR				(Offset 0x0440) */

#define BIT_SHIFT_RRSR_RSC				21
#define BIT_MASK_RRSR_RSC				0xf
#define BIT_RRSR_RSC(x)				(((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC)
#define BITS_RRSR_RSC					(BIT_MASK_RRSR_RSC << BIT_SHIFT_RRSR_RSC)
#define BIT_CLEAR_RRSR_RSC(x)				((x) & (~BITS_RRSR_RSC))
#define BIT_GET_RRSR_RSC(x)				(((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC)
#define BIT_SET_RRSR_RSC(x, v)				(BIT_CLEAR_RRSR_RSC(x) | BIT_RRSR_RSC(v))

#define BIT_SHIFT_R_RATE_CTRL_TABLE			0
#define BIT_MASK_R_RATE_CTRL_TABLE			0xfffff
#define BIT_R_RATE_CTRL_TABLE(x)			(((x) & BIT_MASK_R_RATE_CTRL_TABLE) << BIT_SHIFT_R_RATE_CTRL_TABLE)
#define BITS_R_RATE_CTRL_TABLE				(BIT_MASK_R_RATE_CTRL_TABLE << BIT_SHIFT_R_RATE_CTRL_TABLE)
#define BIT_CLEAR_R_RATE_CTRL_TABLE(x)			((x) & (~BITS_R_RATE_CTRL_TABLE))
#define BIT_GET_R_RATE_CTRL_TABLE(x)			(((x) >> BIT_SHIFT_R_RATE_CTRL_TABLE) & BIT_MASK_R_RATE_CTRL_TABLE)
#define BIT_SET_R_RATE_CTRL_TABLE(x, v)		(BIT_CLEAR_R_RATE_CTRL_TABLE(x) | BIT_R_RATE_CTRL_TABLE(v))

/* 2 REG_ARFRL0				(Offset 0x0444) */

#define BIT_SHIFT_ADPT_RATE_TABLE_L0			0
#define BIT_MASK_ADPT_RATE_TABLE_L0			0xffffffffL
#define BIT_ADPT_RATE_TABLE_L0(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_L0) << BIT_SHIFT_ADPT_RATE_TABLE_L0)
#define BITS_ADPT_RATE_TABLE_L0			(BIT_MASK_ADPT_RATE_TABLE_L0 << BIT_SHIFT_ADPT_RATE_TABLE_L0)
#define BIT_CLEAR_ADPT_RATE_TABLE_L0(x)		((x) & (~BITS_ADPT_RATE_TABLE_L0))
#define BIT_GET_ADPT_RATE_TABLE_L0(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_L0) & BIT_MASK_ADPT_RATE_TABLE_L0)
#define BIT_SET_ADPT_RATE_TABLE_L0(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_L0(x) | BIT_ADPT_RATE_TABLE_L0(v))

/* 2 REG_ARFRH0				(Offset 0x0448) */

#define BIT_SHIFT_ADPT_RATE_TABLE_H0			0
#define BIT_MASK_ADPT_RATE_TABLE_H0			0xffffffffL
#define BIT_ADPT_RATE_TABLE_H0(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_H0) << BIT_SHIFT_ADPT_RATE_TABLE_H0)
#define BITS_ADPT_RATE_TABLE_H0			(BIT_MASK_ADPT_RATE_TABLE_H0 << BIT_SHIFT_ADPT_RATE_TABLE_H0)
#define BIT_CLEAR_ADPT_RATE_TABLE_H0(x)		((x) & (~BITS_ADPT_RATE_TABLE_H0))
#define BIT_GET_ADPT_RATE_TABLE_H0(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_H0) & BIT_MASK_ADPT_RATE_TABLE_H0)
#define BIT_SET_ADPT_RATE_TABLE_H0(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_H0(x) | BIT_ADPT_RATE_TABLE_H0(v))

/* 2 REG_ARFR1_V1				(Offset 0x044C) */

#define BIT_SHIFT_ADPT_RATE_TABLE_L1			0
#define BIT_MASK_ADPT_RATE_TABLE_L1			0xffffffffL
#define BIT_ADPT_RATE_TABLE_L1(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_L1) << BIT_SHIFT_ADPT_RATE_TABLE_L1)
#define BITS_ADPT_RATE_TABLE_L1			(BIT_MASK_ADPT_RATE_TABLE_L1 << BIT_SHIFT_ADPT_RATE_TABLE_L1)
#define BIT_CLEAR_ADPT_RATE_TABLE_L1(x)		((x) & (~BITS_ADPT_RATE_TABLE_L1))
#define BIT_GET_ADPT_RATE_TABLE_L1(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_L1) & BIT_MASK_ADPT_RATE_TABLE_L1)
#define BIT_SET_ADPT_RATE_TABLE_L1(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_L1(x) | BIT_ADPT_RATE_TABLE_L1(v))

/* 2 REG_ARFRH1_V1				(Offset 0x0450) */

#define BIT_SHIFT_ADPT_RATE_TABLE_H1			0
#define BIT_MASK_ADPT_RATE_TABLE_H1			0xffffffffL
#define BIT_ADPT_RATE_TABLE_H1(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_H1) << BIT_SHIFT_ADPT_RATE_TABLE_H1)
#define BITS_ADPT_RATE_TABLE_H1			(BIT_MASK_ADPT_RATE_TABLE_H1 << BIT_SHIFT_ADPT_RATE_TABLE_H1)
#define BIT_CLEAR_ADPT_RATE_TABLE_H1(x)		((x) & (~BITS_ADPT_RATE_TABLE_H1))
#define BIT_GET_ADPT_RATE_TABLE_H1(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_H1) & BIT_MASK_ADPT_RATE_TABLE_H1)
#define BIT_SET_ADPT_RATE_TABLE_H1(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_H1(x) | BIT_ADPT_RATE_TABLE_H1(v))

/* 2 REG_CCK_CHECK				(Offset 0x0454) */

#define BIT_CHECK_CCK_EN				BIT(7)
#define BIT_EN_BCN_PKT_REL				BIT(6)
#define BIT_BCN_PORT_SEL				BIT(5)
#define BIT_MOREDATA_BYPASS				BIT(4)
#define BIT_EN_CLR_CMD_REL_BCN_PKT			BIT(3)
#define BIT_EN_SET_MOREDATA				BIT(2)
#define BIT_DIS_CLEAR_MACID_RELEASE			BIT(1)
#define BIT_EN_MACID_RELEASE				BIT(0)

/* 2 REG_BCNQ2_BDNY				(Offset 0x0455) */

#define BIT_SHIFT_BCNQ2_HEAD				0
#define BIT_MASK_BCNQ2_HEAD				0xff
#define BIT_BCNQ2_HEAD(x)				(((x) & BIT_MASK_BCNQ2_HEAD) << BIT_SHIFT_BCNQ2_HEAD)
#define BITS_BCNQ2_HEAD				(BIT_MASK_BCNQ2_HEAD << BIT_SHIFT_BCNQ2_HEAD)
#define BIT_CLEAR_BCNQ2_HEAD(x)			((x) & (~BITS_BCNQ2_HEAD))
#define BIT_GET_BCNQ2_HEAD(x)				(((x) >> BIT_SHIFT_BCNQ2_HEAD) & BIT_MASK_BCNQ2_HEAD)
#define BIT_SET_BCNQ2_HEAD(x, v)			(BIT_CLEAR_BCNQ2_HEAD(x) | BIT_BCNQ2_HEAD(v))

/* 2 REG_AMPDU_MAX_TIME			(Offset 0x0456) */

#define BIT_SHIFT_AMPDU_MAX_TIME			0
#define BIT_MASK_AMPDU_MAX_TIME			0xff
#define BIT_AMPDU_MAX_TIME(x)				(((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME)
#define BITS_AMPDU_MAX_TIME				(BIT_MASK_AMPDU_MAX_TIME << BIT_SHIFT_AMPDU_MAX_TIME)
#define BIT_CLEAR_AMPDU_MAX_TIME(x)			((x) & (~BITS_AMPDU_MAX_TIME))
#define BIT_GET_AMPDU_MAX_TIME(x)			(((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME)
#define BIT_SET_AMPDU_MAX_TIME(x, v)			(BIT_CLEAR_AMPDU_MAX_TIME(x) | BIT_AMPDU_MAX_TIME(v))

/* 2 REG_BCNQ1_BDNY				(Offset 0x0457) */

#define BIT_SHIFT_BCNQ1_HEAD				0
#define BIT_MASK_BCNQ1_HEAD				0xff
#define BIT_BCNQ1_HEAD(x)				(((x) & BIT_MASK_BCNQ1_HEAD) << BIT_SHIFT_BCNQ1_HEAD)
#define BITS_BCNQ1_HEAD				(BIT_MASK_BCNQ1_HEAD << BIT_SHIFT_BCNQ1_HEAD)
#define BIT_CLEAR_BCNQ1_HEAD(x)			((x) & (~BITS_BCNQ1_HEAD))
#define BIT_GET_BCNQ1_HEAD(x)				(((x) >> BIT_SHIFT_BCNQ1_HEAD) & BIT_MASK_BCNQ1_HEAD)
#define BIT_SET_BCNQ1_HEAD(x, v)			(BIT_CLEAR_BCNQ1_HEAD(x) | BIT_BCNQ1_HEAD(v))

/* 2 REG_AMPDU_MAX_LENGTH			(Offset 0x0458) */

#define BIT_SHIFT_AMPDU_MAX_LENGTH			0
#define BIT_MASK_AMPDU_MAX_LENGTH			0xffffffffL
#define BIT_AMPDU_MAX_LENGTH(x)			(((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH)
#define BITS_AMPDU_MAX_LENGTH				(BIT_MASK_AMPDU_MAX_LENGTH << BIT_SHIFT_AMPDU_MAX_LENGTH)
#define BIT_CLEAR_AMPDU_MAX_LENGTH(x)			((x) & (~BITS_AMPDU_MAX_LENGTH))
#define BIT_GET_AMPDU_MAX_LENGTH(x)			(((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH)
#define BIT_SET_AMPDU_MAX_LENGTH(x, v)			(BIT_CLEAR_AMPDU_MAX_LENGTH(x) | BIT_AMPDU_MAX_LENGTH(v))

/* 2 REG_ACQ_STOP				(Offset 0x045C) */

#define BIT_AC7Q_STOP					BIT(7)
#define BIT_AC6Q_STOP					BIT(6)
#define BIT_AC5Q_STOP					BIT(5)
#define BIT_AC4Q_STOP					BIT(4)
#define BIT_AC3Q_STOP					BIT(3)
#define BIT_AC2Q_STOP					BIT(2)
#define BIT_AC1Q_STOP					BIT(1)
#define BIT_AC0Q_STOP					BIT(0)

/* 2 REG_WMAC_LBK_BUF_HD			(Offset 0x045D) */

#define BIT_SHIFT_WMAC_LBK_BUF_HEAD			0
#define BIT_MASK_WMAC_LBK_BUF_HEAD			0xff
#define BIT_WMAC_LBK_BUF_HEAD(x)			(((x) & BIT_MASK_WMAC_LBK_BUF_HEAD) << BIT_SHIFT_WMAC_LBK_BUF_HEAD)
#define BITS_WMAC_LBK_BUF_HEAD				(BIT_MASK_WMAC_LBK_BUF_HEAD << BIT_SHIFT_WMAC_LBK_BUF_HEAD)
#define BIT_CLEAR_WMAC_LBK_BUF_HEAD(x)			((x) & (~BITS_WMAC_LBK_BUF_HEAD))
#define BIT_GET_WMAC_LBK_BUF_HEAD(x)			(((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD) & BIT_MASK_WMAC_LBK_BUF_HEAD)
#define BIT_SET_WMAC_LBK_BUF_HEAD(x, v)		(BIT_CLEAR_WMAC_LBK_BUF_HEAD(x) | BIT_WMAC_LBK_BUF_HEAD(v))

/* 2 REG_TX_HANG_CTRL			(Offset 0x045E) */

#define BIT_SHIFT_R_SIGTA_BW				6
#define BIT_MASK_R_SIGTA_BW				0x3
#define BIT_R_SIGTA_BW(x)				(((x) & BIT_MASK_R_SIGTA_BW) << BIT_SHIFT_R_SIGTA_BW)
#define BITS_R_SIGTA_BW				(BIT_MASK_R_SIGTA_BW << BIT_SHIFT_R_SIGTA_BW)
#define BIT_CLEAR_R_SIGTA_BW(x)			((x) & (~BITS_R_SIGTA_BW))
#define BIT_GET_R_SIGTA_BW(x)				(((x) >> BIT_SHIFT_R_SIGTA_BW) & BIT_MASK_R_SIGTA_BW)
#define BIT_SET_R_SIGTA_BW(x, v)			(BIT_CLEAR_R_SIGTA_BW(x) | BIT_R_SIGTA_BW(v))

#define BIT_R_SIGTA_BAR				BIT(5)
#define BIT_R_EOF_EN					BIT(4)
#define BIT_R_EN_GNT_BT_AWAKE				BIT(3)
#define BIT_DIS_RELEASE_RETRY				BIT(2)
#define BIT_DIS_OQT_BLOCK				BIT(1)
#define BIT_SEARCH_QUEUE_EN				BIT(0)

/* 2 REG_NDPA_OPT_CTRL			(Offset 0x045F) */

#define BIT_SHIFT_R_NDPA_RATE				2
#define BIT_MASK_R_NDPA_RATE				0x3f
#define BIT_R_NDPA_RATE(x)				(((x) & BIT_MASK_R_NDPA_RATE) << BIT_SHIFT_R_NDPA_RATE)
#define BITS_R_NDPA_RATE				(BIT_MASK_R_NDPA_RATE << BIT_SHIFT_R_NDPA_RATE)
#define BIT_CLEAR_R_NDPA_RATE(x)			((x) & (~BITS_R_NDPA_RATE))
#define BIT_GET_R_NDPA_RATE(x)				(((x) >> BIT_SHIFT_R_NDPA_RATE) & BIT_MASK_R_NDPA_RATE)
#define BIT_SET_R_NDPA_RATE(x, v)			(BIT_CLEAR_R_NDPA_RATE(x) | BIT_R_NDPA_RATE(v))

#define BIT_SHIFT_R_NDPA_BW				0
#define BIT_MASK_R_NDPA_BW				0x3
#define BIT_R_NDPA_BW(x)				(((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW)
#define BITS_R_NDPA_BW					(BIT_MASK_R_NDPA_BW << BIT_SHIFT_R_NDPA_BW)
#define BIT_CLEAR_R_NDPA_BW(x)				((x) & (~BITS_R_NDPA_BW))
#define BIT_GET_R_NDPA_BW(x)				(((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW)
#define BIT_SET_R_NDPA_BW(x, v)			(BIT_CLEAR_R_NDPA_BW(x) | BIT_R_NDPA_BW(v))

/* 2 REG_RD_RESP_PKT_TH			(Offset 0x0463) */

#define BIT_SHIFT_RD_RESP_PKT_TH			0
#define BIT_MASK_RD_RESP_PKT_TH			0x3f
#define BIT_RD_RESP_PKT_TH(x)				(((x) & BIT_MASK_RD_RESP_PKT_TH) << BIT_SHIFT_RD_RESP_PKT_TH)
#define BITS_RD_RESP_PKT_TH				(BIT_MASK_RD_RESP_PKT_TH << BIT_SHIFT_RD_RESP_PKT_TH)
#define BIT_CLEAR_RD_RESP_PKT_TH(x)			((x) & (~BITS_RD_RESP_PKT_TH))
#define BIT_GET_RD_RESP_PKT_TH(x)			(((x) >> BIT_SHIFT_RD_RESP_PKT_TH) & BIT_MASK_RD_RESP_PKT_TH)
#define BIT_SET_RD_RESP_PKT_TH(x, v)			(BIT_CLEAR_RD_RESP_PKT_TH(x) | BIT_RD_RESP_PKT_TH(v))

/* 2 REG_CMDQ_INFO				(Offset 0x0464) */

#define BIT_SHIFT_PKT_NUM_CMDQ_V2			24
#define BIT_MASK_PKT_NUM_CMDQ_V2			0xff
#define BIT_PKT_NUM_CMDQ_V2(x)				(((x) & BIT_MASK_PKT_NUM_CMDQ_V2) << BIT_SHIFT_PKT_NUM_CMDQ_V2)
#define BITS_PKT_NUM_CMDQ_V2				(BIT_MASK_PKT_NUM_CMDQ_V2 << BIT_SHIFT_PKT_NUM_CMDQ_V2)
#define BIT_CLEAR_PKT_NUM_CMDQ_V2(x)			((x) & (~BITS_PKT_NUM_CMDQ_V2))
#define BIT_GET_PKT_NUM_CMDQ_V2(x)			(((x) >> BIT_SHIFT_PKT_NUM_CMDQ_V2) & BIT_MASK_PKT_NUM_CMDQ_V2)
#define BIT_SET_PKT_NUM_CMDQ_V2(x, v)			(BIT_CLEAR_PKT_NUM_CMDQ_V2(x) | BIT_PKT_NUM_CMDQ_V2(v))

#define BIT_SHIFT_TAIL_PKT_CMDQ			16
#define BIT_MASK_TAIL_PKT_CMDQ				0xff
#define BIT_TAIL_PKT_CMDQ(x)				(((x) & BIT_MASK_TAIL_PKT_CMDQ) << BIT_SHIFT_TAIL_PKT_CMDQ)
#define BITS_TAIL_PKT_CMDQ				(BIT_MASK_TAIL_PKT_CMDQ << BIT_SHIFT_TAIL_PKT_CMDQ)
#define BIT_CLEAR_TAIL_PKT_CMDQ(x)			((x) & (~BITS_TAIL_PKT_CMDQ))
#define BIT_GET_TAIL_PKT_CMDQ(x)			(((x) >> BIT_SHIFT_TAIL_PKT_CMDQ) & BIT_MASK_TAIL_PKT_CMDQ)
#define BIT_SET_TAIL_PKT_CMDQ(x, v)			(BIT_CLEAR_TAIL_PKT_CMDQ(x) | BIT_TAIL_PKT_CMDQ(v))

#define BIT_SHIFT_PKT_NUM_CMDQ				8
#define BIT_MASK_PKT_NUM_CMDQ				0xff
#define BIT_PKT_NUM_CMDQ(x)				(((x) & BIT_MASK_PKT_NUM_CMDQ) << BIT_SHIFT_PKT_NUM_CMDQ)
#define BITS_PKT_NUM_CMDQ				(BIT_MASK_PKT_NUM_CMDQ << BIT_SHIFT_PKT_NUM_CMDQ)
#define BIT_CLEAR_PKT_NUM_CMDQ(x)			((x) & (~BITS_PKT_NUM_CMDQ))
#define BIT_GET_PKT_NUM_CMDQ(x)			(((x) >> BIT_SHIFT_PKT_NUM_CMDQ) & BIT_MASK_PKT_NUM_CMDQ)
#define BIT_SET_PKT_NUM_CMDQ(x, v)			(BIT_CLEAR_PKT_NUM_CMDQ(x) | BIT_PKT_NUM_CMDQ(v))

#define BIT_SHIFT_HEAD_PKT_CMDQ			0
#define BIT_MASK_HEAD_PKT_CMDQ				0xff
#define BIT_HEAD_PKT_CMDQ(x)				(((x) & BIT_MASK_HEAD_PKT_CMDQ) << BIT_SHIFT_HEAD_PKT_CMDQ)
#define BITS_HEAD_PKT_CMDQ				(BIT_MASK_HEAD_PKT_CMDQ << BIT_SHIFT_HEAD_PKT_CMDQ)
#define BIT_CLEAR_HEAD_PKT_CMDQ(x)			((x) & (~BITS_HEAD_PKT_CMDQ))
#define BIT_GET_HEAD_PKT_CMDQ(x)			(((x) >> BIT_SHIFT_HEAD_PKT_CMDQ) & BIT_MASK_HEAD_PKT_CMDQ)
#define BIT_SET_HEAD_PKT_CMDQ(x, v)			(BIT_CLEAR_HEAD_PKT_CMDQ(x) | BIT_HEAD_PKT_CMDQ(v))

/* 2 REG_Q4_INFO				(Offset 0x0468) */

#define BIT_SHIFT_QUEUEMACID_Q4_V1			25
#define BIT_MASK_QUEUEMACID_Q4_V1			0x7f
#define BIT_QUEUEMACID_Q4_V1(x)			(((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1)
#define BITS_QUEUEMACID_Q4_V1				(BIT_MASK_QUEUEMACID_Q4_V1 << BIT_SHIFT_QUEUEMACID_Q4_V1)
#define BIT_CLEAR_QUEUEMACID_Q4_V1(x)			((x) & (~BITS_QUEUEMACID_Q4_V1))
#define BIT_GET_QUEUEMACID_Q4_V1(x)			(((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1)
#define BIT_SET_QUEUEMACID_Q4_V1(x, v)			(BIT_CLEAR_QUEUEMACID_Q4_V1(x) | BIT_QUEUEMACID_Q4_V1(v))

#define BIT_SHIFT_QUEUEAC_Q4_V1			23
#define BIT_MASK_QUEUEAC_Q4_V1				0x3
#define BIT_QUEUEAC_Q4_V1(x)				(((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1)
#define BITS_QUEUEAC_Q4_V1				(BIT_MASK_QUEUEAC_Q4_V1 << BIT_SHIFT_QUEUEAC_Q4_V1)
#define BIT_CLEAR_QUEUEAC_Q4_V1(x)			((x) & (~BITS_QUEUEAC_Q4_V1))
#define BIT_GET_QUEUEAC_Q4_V1(x)			(((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1)
#define BIT_SET_QUEUEAC_Q4_V1(x, v)			(BIT_CLEAR_QUEUEAC_Q4_V1(x) | BIT_QUEUEAC_Q4_V1(v))

#define BIT_SHIFT_TAIL_PKT_Q4_V1			15
#define BIT_MASK_TAIL_PKT_Q4_V1			0xff
#define BIT_TAIL_PKT_Q4_V1(x)				(((x) & BIT_MASK_TAIL_PKT_Q4_V1) << BIT_SHIFT_TAIL_PKT_Q4_V1)
#define BITS_TAIL_PKT_Q4_V1				(BIT_MASK_TAIL_PKT_Q4_V1 << BIT_SHIFT_TAIL_PKT_Q4_V1)
#define BIT_CLEAR_TAIL_PKT_Q4_V1(x)			((x) & (~BITS_TAIL_PKT_Q4_V1))
#define BIT_GET_TAIL_PKT_Q4_V1(x)			(((x) >> BIT_SHIFT_TAIL_PKT_Q4_V1) & BIT_MASK_TAIL_PKT_Q4_V1)
#define BIT_SET_TAIL_PKT_Q4_V1(x, v)			(BIT_CLEAR_TAIL_PKT_Q4_V1(x) | BIT_TAIL_PKT_Q4_V1(v))

#define BIT_SHIFT_PKT_NUM_Q4_V1			8
#define BIT_MASK_PKT_NUM_Q4_V1				0x7f
#define BIT_PKT_NUM_Q4_V1(x)				(((x) & BIT_MASK_PKT_NUM_Q4_V1) << BIT_SHIFT_PKT_NUM_Q4_V1)
#define BITS_PKT_NUM_Q4_V1				(BIT_MASK_PKT_NUM_Q4_V1 << BIT_SHIFT_PKT_NUM_Q4_V1)
#define BIT_CLEAR_PKT_NUM_Q4_V1(x)			((x) & (~BITS_PKT_NUM_Q4_V1))
#define BIT_GET_PKT_NUM_Q4_V1(x)			(((x) >> BIT_SHIFT_PKT_NUM_Q4_V1) & BIT_MASK_PKT_NUM_Q4_V1)
#define BIT_SET_PKT_NUM_Q4_V1(x, v)			(BIT_CLEAR_PKT_NUM_Q4_V1(x) | BIT_PKT_NUM_Q4_V1(v))

#define BIT_SHIFT_HEAD_PKT_Q4				0
#define BIT_MASK_HEAD_PKT_Q4				0xff
#define BIT_HEAD_PKT_Q4(x)				(((x) & BIT_MASK_HEAD_PKT_Q4) << BIT_SHIFT_HEAD_PKT_Q4)
#define BITS_HEAD_PKT_Q4				(BIT_MASK_HEAD_PKT_Q4 << BIT_SHIFT_HEAD_PKT_Q4)
#define BIT_CLEAR_HEAD_PKT_Q4(x)			((x) & (~BITS_HEAD_PKT_Q4))
#define BIT_GET_HEAD_PKT_Q4(x)				(((x) >> BIT_SHIFT_HEAD_PKT_Q4) & BIT_MASK_HEAD_PKT_Q4)
#define BIT_SET_HEAD_PKT_Q4(x, v)			(BIT_CLEAR_HEAD_PKT_Q4(x) | BIT_HEAD_PKT_Q4(v))

/* 2 REG_Q5_INFO				(Offset 0x046C) */

#define BIT_SHIFT_QUEUEMACID_Q5_V1			25
#define BIT_MASK_QUEUEMACID_Q5_V1			0x7f
#define BIT_QUEUEMACID_Q5_V1(x)			(((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1)
#define BITS_QUEUEMACID_Q5_V1				(BIT_MASK_QUEUEMACID_Q5_V1 << BIT_SHIFT_QUEUEMACID_Q5_V1)
#define BIT_CLEAR_QUEUEMACID_Q5_V1(x)			((x) & (~BITS_QUEUEMACID_Q5_V1))
#define BIT_GET_QUEUEMACID_Q5_V1(x)			(((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1)
#define BIT_SET_QUEUEMACID_Q5_V1(x, v)			(BIT_CLEAR_QUEUEMACID_Q5_V1(x) | BIT_QUEUEMACID_Q5_V1(v))

#define BIT_SHIFT_QUEUEAC_Q5_V1			23
#define BIT_MASK_QUEUEAC_Q5_V1				0x3
#define BIT_QUEUEAC_Q5_V1(x)				(((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1)
#define BITS_QUEUEAC_Q5_V1				(BIT_MASK_QUEUEAC_Q5_V1 << BIT_SHIFT_QUEUEAC_Q5_V1)
#define BIT_CLEAR_QUEUEAC_Q5_V1(x)			((x) & (~BITS_QUEUEAC_Q5_V1))
#define BIT_GET_QUEUEAC_Q5_V1(x)			(((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1)
#define BIT_SET_QUEUEAC_Q5_V1(x, v)			(BIT_CLEAR_QUEUEAC_Q5_V1(x) | BIT_QUEUEAC_Q5_V1(v))

#define BIT_SHIFT_TAIL_PKT_Q5_V1			15
#define BIT_MASK_TAIL_PKT_Q5_V1			0xff
#define BIT_TAIL_PKT_Q5_V1(x)				(((x) & BIT_MASK_TAIL_PKT_Q5_V1) << BIT_SHIFT_TAIL_PKT_Q5_V1)
#define BITS_TAIL_PKT_Q5_V1				(BIT_MASK_TAIL_PKT_Q5_V1 << BIT_SHIFT_TAIL_PKT_Q5_V1)
#define BIT_CLEAR_TAIL_PKT_Q5_V1(x)			((x) & (~BITS_TAIL_PKT_Q5_V1))
#define BIT_GET_TAIL_PKT_Q5_V1(x)			(((x) >> BIT_SHIFT_TAIL_PKT_Q5_V1) & BIT_MASK_TAIL_PKT_Q5_V1)
#define BIT_SET_TAIL_PKT_Q5_V1(x, v)			(BIT_CLEAR_TAIL_PKT_Q5_V1(x) | BIT_TAIL_PKT_Q5_V1(v))

#define BIT_SHIFT_PKT_NUM_Q5_V1			8
#define BIT_MASK_PKT_NUM_Q5_V1				0x7f
#define BIT_PKT_NUM_Q5_V1(x)				(((x) & BIT_MASK_PKT_NUM_Q5_V1) << BIT_SHIFT_PKT_NUM_Q5_V1)
#define BITS_PKT_NUM_Q5_V1				(BIT_MASK_PKT_NUM_Q5_V1 << BIT_SHIFT_PKT_NUM_Q5_V1)
#define BIT_CLEAR_PKT_NUM_Q5_V1(x)			((x) & (~BITS_PKT_NUM_Q5_V1))
#define BIT_GET_PKT_NUM_Q5_V1(x)			(((x) >> BIT_SHIFT_PKT_NUM_Q5_V1) & BIT_MASK_PKT_NUM_Q5_V1)
#define BIT_SET_PKT_NUM_Q5_V1(x, v)			(BIT_CLEAR_PKT_NUM_Q5_V1(x) | BIT_PKT_NUM_Q5_V1(v))

#define BIT_SHIFT_HEAD_PKT_Q5				0
#define BIT_MASK_HEAD_PKT_Q5				0xff
#define BIT_HEAD_PKT_Q5(x)				(((x) & BIT_MASK_HEAD_PKT_Q5) << BIT_SHIFT_HEAD_PKT_Q5)
#define BITS_HEAD_PKT_Q5				(BIT_MASK_HEAD_PKT_Q5 << BIT_SHIFT_HEAD_PKT_Q5)
#define BIT_CLEAR_HEAD_PKT_Q5(x)			((x) & (~BITS_HEAD_PKT_Q5))
#define BIT_GET_HEAD_PKT_Q5(x)				(((x) >> BIT_SHIFT_HEAD_PKT_Q5) & BIT_MASK_HEAD_PKT_Q5)
#define BIT_SET_HEAD_PKT_Q5(x, v)			(BIT_CLEAR_HEAD_PKT_Q5(x) | BIT_HEAD_PKT_Q5(v))

/* 2 REG_Q6_INFO				(Offset 0x0470) */

#define BIT_SHIFT_QUEUEMACID_Q6_V1			25
#define BIT_MASK_QUEUEMACID_Q6_V1			0x7f
#define BIT_QUEUEMACID_Q6_V1(x)			(((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1)
#define BITS_QUEUEMACID_Q6_V1				(BIT_MASK_QUEUEMACID_Q6_V1 << BIT_SHIFT_QUEUEMACID_Q6_V1)
#define BIT_CLEAR_QUEUEMACID_Q6_V1(x)			((x) & (~BITS_QUEUEMACID_Q6_V1))
#define BIT_GET_QUEUEMACID_Q6_V1(x)			(((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1)
#define BIT_SET_QUEUEMACID_Q6_V1(x, v)			(BIT_CLEAR_QUEUEMACID_Q6_V1(x) | BIT_QUEUEMACID_Q6_V1(v))

#define BIT_SHIFT_QUEUEAC_Q6_V1			23
#define BIT_MASK_QUEUEAC_Q6_V1				0x3
#define BIT_QUEUEAC_Q6_V1(x)				(((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1)
#define BITS_QUEUEAC_Q6_V1				(BIT_MASK_QUEUEAC_Q6_V1 << BIT_SHIFT_QUEUEAC_Q6_V1)
#define BIT_CLEAR_QUEUEAC_Q6_V1(x)			((x) & (~BITS_QUEUEAC_Q6_V1))
#define BIT_GET_QUEUEAC_Q6_V1(x)			(((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1)
#define BIT_SET_QUEUEAC_Q6_V1(x, v)			(BIT_CLEAR_QUEUEAC_Q6_V1(x) | BIT_QUEUEAC_Q6_V1(v))

#define BIT_SHIFT_TAIL_PKT_Q6_V1			15
#define BIT_MASK_TAIL_PKT_Q6_V1			0xff
#define BIT_TAIL_PKT_Q6_V1(x)				(((x) & BIT_MASK_TAIL_PKT_Q6_V1) << BIT_SHIFT_TAIL_PKT_Q6_V1)
#define BITS_TAIL_PKT_Q6_V1				(BIT_MASK_TAIL_PKT_Q6_V1 << BIT_SHIFT_TAIL_PKT_Q6_V1)
#define BIT_CLEAR_TAIL_PKT_Q6_V1(x)			((x) & (~BITS_TAIL_PKT_Q6_V1))
#define BIT_GET_TAIL_PKT_Q6_V1(x)			(((x) >> BIT_SHIFT_TAIL_PKT_Q6_V1) & BIT_MASK_TAIL_PKT_Q6_V1)
#define BIT_SET_TAIL_PKT_Q6_V1(x, v)			(BIT_CLEAR_TAIL_PKT_Q6_V1(x) | BIT_TAIL_PKT_Q6_V1(v))

#define BIT_SHIFT_PKT_NUM_Q6_V1			8
#define BIT_MASK_PKT_NUM_Q6_V1				0x7f
#define BIT_PKT_NUM_Q6_V1(x)				(((x) & BIT_MASK_PKT_NUM_Q6_V1) << BIT_SHIFT_PKT_NUM_Q6_V1)
#define BITS_PKT_NUM_Q6_V1				(BIT_MASK_PKT_NUM_Q6_V1 << BIT_SHIFT_PKT_NUM_Q6_V1)
#define BIT_CLEAR_PKT_NUM_Q6_V1(x)			((x) & (~BITS_PKT_NUM_Q6_V1))
#define BIT_GET_PKT_NUM_Q6_V1(x)			(((x) >> BIT_SHIFT_PKT_NUM_Q6_V1) & BIT_MASK_PKT_NUM_Q6_V1)
#define BIT_SET_PKT_NUM_Q6_V1(x, v)			(BIT_CLEAR_PKT_NUM_Q6_V1(x) | BIT_PKT_NUM_Q6_V1(v))

#define BIT_SHIFT_HEAD_PKT_Q6				0
#define BIT_MASK_HEAD_PKT_Q6				0xff
#define BIT_HEAD_PKT_Q6(x)				(((x) & BIT_MASK_HEAD_PKT_Q6) << BIT_SHIFT_HEAD_PKT_Q6)
#define BITS_HEAD_PKT_Q6				(BIT_MASK_HEAD_PKT_Q6 << BIT_SHIFT_HEAD_PKT_Q6)
#define BIT_CLEAR_HEAD_PKT_Q6(x)			((x) & (~BITS_HEAD_PKT_Q6))
#define BIT_GET_HEAD_PKT_Q6(x)				(((x) >> BIT_SHIFT_HEAD_PKT_Q6) & BIT_MASK_HEAD_PKT_Q6)
#define BIT_SET_HEAD_PKT_Q6(x, v)			(BIT_CLEAR_HEAD_PKT_Q6(x) | BIT_HEAD_PKT_Q6(v))

/* 2 REG_Q7_INFO				(Offset 0x0474) */

#define BIT_SHIFT_QUEUEMACID_Q7_V1			25
#define BIT_MASK_QUEUEMACID_Q7_V1			0x7f
#define BIT_QUEUEMACID_Q7_V1(x)			(((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1)
#define BITS_QUEUEMACID_Q7_V1				(BIT_MASK_QUEUEMACID_Q7_V1 << BIT_SHIFT_QUEUEMACID_Q7_V1)
#define BIT_CLEAR_QUEUEMACID_Q7_V1(x)			((x) & (~BITS_QUEUEMACID_Q7_V1))
#define BIT_GET_QUEUEMACID_Q7_V1(x)			(((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1)
#define BIT_SET_QUEUEMACID_Q7_V1(x, v)			(BIT_CLEAR_QUEUEMACID_Q7_V1(x) | BIT_QUEUEMACID_Q7_V1(v))

#define BIT_SHIFT_QUEUEAC_Q7_V1			23
#define BIT_MASK_QUEUEAC_Q7_V1				0x3
#define BIT_QUEUEAC_Q7_V1(x)				(((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1)
#define BITS_QUEUEAC_Q7_V1				(BIT_MASK_QUEUEAC_Q7_V1 << BIT_SHIFT_QUEUEAC_Q7_V1)
#define BIT_CLEAR_QUEUEAC_Q7_V1(x)			((x) & (~BITS_QUEUEAC_Q7_V1))
#define BIT_GET_QUEUEAC_Q7_V1(x)			(((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1)
#define BIT_SET_QUEUEAC_Q7_V1(x, v)			(BIT_CLEAR_QUEUEAC_Q7_V1(x) | BIT_QUEUEAC_Q7_V1(v))

#define BIT_SHIFT_TAIL_PKT_Q7_V1			15
#define BIT_MASK_TAIL_PKT_Q7_V1			0xff
#define BIT_TAIL_PKT_Q7_V1(x)				(((x) & BIT_MASK_TAIL_PKT_Q7_V1) << BIT_SHIFT_TAIL_PKT_Q7_V1)
#define BITS_TAIL_PKT_Q7_V1				(BIT_MASK_TAIL_PKT_Q7_V1 << BIT_SHIFT_TAIL_PKT_Q7_V1)
#define BIT_CLEAR_TAIL_PKT_Q7_V1(x)			((x) & (~BITS_TAIL_PKT_Q7_V1))
#define BIT_GET_TAIL_PKT_Q7_V1(x)			(((x) >> BIT_SHIFT_TAIL_PKT_Q7_V1) & BIT_MASK_TAIL_PKT_Q7_V1)
#define BIT_SET_TAIL_PKT_Q7_V1(x, v)			(BIT_CLEAR_TAIL_PKT_Q7_V1(x) | BIT_TAIL_PKT_Q7_V1(v))

#define BIT_SHIFT_PKT_NUM_Q7_V1			8
#define BIT_MASK_PKT_NUM_Q7_V1				0x7f
#define BIT_PKT_NUM_Q7_V1(x)				(((x) & BIT_MASK_PKT_NUM_Q7_V1) << BIT_SHIFT_PKT_NUM_Q7_V1)
#define BITS_PKT_NUM_Q7_V1				(BIT_MASK_PKT_NUM_Q7_V1 << BIT_SHIFT_PKT_NUM_Q7_V1)
#define BIT_CLEAR_PKT_NUM_Q7_V1(x)			((x) & (~BITS_PKT_NUM_Q7_V1))
#define BIT_GET_PKT_NUM_Q7_V1(x)			(((x) >> BIT_SHIFT_PKT_NUM_Q7_V1) & BIT_MASK_PKT_NUM_Q7_V1)
#define BIT_SET_PKT_NUM_Q7_V1(x, v)			(BIT_CLEAR_PKT_NUM_Q7_V1(x) | BIT_PKT_NUM_Q7_V1(v))

#define BIT_SHIFT_HEAD_PKT_Q7				0
#define BIT_MASK_HEAD_PKT_Q7				0xff
#define BIT_HEAD_PKT_Q7(x)				(((x) & BIT_MASK_HEAD_PKT_Q7) << BIT_SHIFT_HEAD_PKT_Q7)
#define BITS_HEAD_PKT_Q7				(BIT_MASK_HEAD_PKT_Q7 << BIT_SHIFT_HEAD_PKT_Q7)
#define BIT_CLEAR_HEAD_PKT_Q7(x)			((x) & (~BITS_HEAD_PKT_Q7))
#define BIT_GET_HEAD_PKT_Q7(x)				(((x) >> BIT_SHIFT_HEAD_PKT_Q7) & BIT_MASK_HEAD_PKT_Q7)
#define BIT_SET_HEAD_PKT_Q7(x, v)			(BIT_CLEAR_HEAD_PKT_Q7(x) | BIT_HEAD_PKT_Q7(v))

/* 2 REG_TXRPT_CTRL				(Offset 0x047C) */

#define BIT_SHIFT_AMPDU_TXRPT_TIME_THRS		24
#define BIT_MASK_AMPDU_TXRPT_TIME_THRS			0xff
#define BIT_AMPDU_TXRPT_TIME_THRS(x)			(((x) & BIT_MASK_AMPDU_TXRPT_TIME_THRS) << BIT_SHIFT_AMPDU_TXRPT_TIME_THRS)
#define BITS_AMPDU_TXRPT_TIME_THRS			(BIT_MASK_AMPDU_TXRPT_TIME_THRS << BIT_SHIFT_AMPDU_TXRPT_TIME_THRS)
#define BIT_CLEAR_AMPDU_TXRPT_TIME_THRS(x)		((x) & (~BITS_AMPDU_TXRPT_TIME_THRS))
#define BIT_GET_AMPDU_TXRPT_TIME_THRS(x)		(((x) >> BIT_SHIFT_AMPDU_TXRPT_TIME_THRS) & BIT_MASK_AMPDU_TXRPT_TIME_THRS)
#define BIT_SET_AMPDU_TXRPT_TIME_THRS(x, v)		(BIT_CLEAR_AMPDU_TXRPT_TIME_THRS(x) | BIT_AMPDU_TXRPT_TIME_THRS(v))

#define BIT_SHIFT_AMPDU_TXRPT_LEN_THRS			16
#define BIT_MASK_AMPDU_TXRPT_LEN_THRS			0xff
#define BIT_AMPDU_TXRPT_LEN_THRS(x)			(((x) & BIT_MASK_AMPDU_TXRPT_LEN_THRS) << BIT_SHIFT_AMPDU_TXRPT_LEN_THRS)
#define BITS_AMPDU_TXRPT_LEN_THRS			(BIT_MASK_AMPDU_TXRPT_LEN_THRS << BIT_SHIFT_AMPDU_TXRPT_LEN_THRS)
#define BIT_CLEAR_AMPDU_TXRPT_LEN_THRS(x)		((x) & (~BITS_AMPDU_TXRPT_LEN_THRS))
#define BIT_GET_AMPDU_TXRPT_LEN_THRS(x)		(((x) >> BIT_SHIFT_AMPDU_TXRPT_LEN_THRS) & BIT_MASK_AMPDU_TXRPT_LEN_THRS)
#define BIT_SET_AMPDU_TXRPT_LEN_THRS(x, v)		(BIT_CLEAR_AMPDU_TXRPT_LEN_THRS(x) | BIT_AMPDU_TXRPT_LEN_THRS(v))

#define BIT_SHIFT_AMPDU_TXRPT_R_PTR			8
#define BIT_MASK_AMPDU_TXRPT_R_PTR			0xff
#define BIT_AMPDU_TXRPT_R_PTR(x)			(((x) & BIT_MASK_AMPDU_TXRPT_R_PTR) << BIT_SHIFT_AMPDU_TXRPT_R_PTR)
#define BITS_AMPDU_TXRPT_R_PTR				(BIT_MASK_AMPDU_TXRPT_R_PTR << BIT_SHIFT_AMPDU_TXRPT_R_PTR)
#define BIT_CLEAR_AMPDU_TXRPT_R_PTR(x)			((x) & (~BITS_AMPDU_TXRPT_R_PTR))
#define BIT_GET_AMPDU_TXRPT_R_PTR(x)			(((x) >> BIT_SHIFT_AMPDU_TXRPT_R_PTR) & BIT_MASK_AMPDU_TXRPT_R_PTR)
#define BIT_SET_AMPDU_TXRPT_R_PTR(x, v)		(BIT_CLEAR_AMPDU_TXRPT_R_PTR(x) | BIT_AMPDU_TXRPT_R_PTR(v))

#define BIT_SHIFT_AMPDU_TXRPT_W_PTR			0
#define BIT_MASK_AMPDU_TXRPT_W_PTR			0xff
#define BIT_AMPDU_TXRPT_W_PTR(x)			(((x) & BIT_MASK_AMPDU_TXRPT_W_PTR) << BIT_SHIFT_AMPDU_TXRPT_W_PTR)
#define BITS_AMPDU_TXRPT_W_PTR				(BIT_MASK_AMPDU_TXRPT_W_PTR << BIT_SHIFT_AMPDU_TXRPT_W_PTR)
#define BIT_CLEAR_AMPDU_TXRPT_W_PTR(x)			((x) & (~BITS_AMPDU_TXRPT_W_PTR))
#define BIT_GET_AMPDU_TXRPT_W_PTR(x)			(((x) >> BIT_SHIFT_AMPDU_TXRPT_W_PTR) & BIT_MASK_AMPDU_TXRPT_W_PTR)
#define BIT_SET_AMPDU_TXRPT_W_PTR(x, v)		(BIT_CLEAR_AMPDU_TXRPT_W_PTR(x) | BIT_AMPDU_TXRPT_W_PTR(v))

/* 2 REG_INIRTS_RATE_SEL			(Offset 0x0480) */

#define BIT_LEAG_RTS_BW_DUP				BIT(5)

/* 2 REG_BASIC_CFEND_RATE			(Offset 0x0481) */

#define BIT_SHIFT_BASIC_CFEND_RATE			0
#define BIT_MASK_BASIC_CFEND_RATE			0x1f
#define BIT_BASIC_CFEND_RATE(x)			(((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE)
#define BITS_BASIC_CFEND_RATE				(BIT_MASK_BASIC_CFEND_RATE << BIT_SHIFT_BASIC_CFEND_RATE)
#define BIT_CLEAR_BASIC_CFEND_RATE(x)			((x) & (~BITS_BASIC_CFEND_RATE))
#define BIT_GET_BASIC_CFEND_RATE(x)			(((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE)
#define BIT_SET_BASIC_CFEND_RATE(x, v)			(BIT_CLEAR_BASIC_CFEND_RATE(x) | BIT_BASIC_CFEND_RATE(v))

/* 2 REG_STBC_CFEND_RATE			(Offset 0x0482) */

#define BIT_SHIFT_STBC_CFEND_RATE			0
#define BIT_MASK_STBC_CFEND_RATE			0x1f
#define BIT_STBC_CFEND_RATE(x)				(((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE)
#define BITS_STBC_CFEND_RATE				(BIT_MASK_STBC_CFEND_RATE << BIT_SHIFT_STBC_CFEND_RATE)
#define BIT_CLEAR_STBC_CFEND_RATE(x)			((x) & (~BITS_STBC_CFEND_RATE))
#define BIT_GET_STBC_CFEND_RATE(x)			(((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE)
#define BIT_SET_STBC_CFEND_RATE(x, v)			(BIT_CLEAR_STBC_CFEND_RATE(x) | BIT_STBC_CFEND_RATE(v))

/* 2 REG_DATA_SC				(Offset 0x0483) */

#define BIT_SHIFT_TXSC_40M				4
#define BIT_MASK_TXSC_40M				0xf
#define BIT_TXSC_40M(x)				(((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)
#define BITS_TXSC_40M					(BIT_MASK_TXSC_40M << BIT_SHIFT_TXSC_40M)
#define BIT_CLEAR_TXSC_40M(x)				((x) & (~BITS_TXSC_40M))
#define BIT_GET_TXSC_40M(x)				(((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M)
#define BIT_SET_TXSC_40M(x, v)				(BIT_CLEAR_TXSC_40M(x) | BIT_TXSC_40M(v))

#define BIT_SHIFT_TXSC_20M				0
#define BIT_MASK_TXSC_20M				0xf
#define BIT_TXSC_20M(x)				(((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)
#define BITS_TXSC_20M					(BIT_MASK_TXSC_20M << BIT_SHIFT_TXSC_20M)
#define BIT_CLEAR_TXSC_20M(x)				((x) & (~BITS_TXSC_20M))
#define BIT_GET_TXSC_20M(x)				(((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M)
#define BIT_SET_TXSC_20M(x, v)				(BIT_CLEAR_TXSC_20M(x) | BIT_TXSC_20M(v))

/* 2 REG_MACID_SLEEP3			(Offset 0x0484) */

#define BIT_SHIFT_MACID127_96_PKTSLEEP			0
#define BIT_MASK_MACID127_96_PKTSLEEP			0xffffffffL
#define BIT_MACID127_96_PKTSLEEP(x)			(((x) & BIT_MASK_MACID127_96_PKTSLEEP) << BIT_SHIFT_MACID127_96_PKTSLEEP)
#define BITS_MACID127_96_PKTSLEEP			(BIT_MASK_MACID127_96_PKTSLEEP << BIT_SHIFT_MACID127_96_PKTSLEEP)
#define BIT_CLEAR_MACID127_96_PKTSLEEP(x)		((x) & (~BITS_MACID127_96_PKTSLEEP))
#define BIT_GET_MACID127_96_PKTSLEEP(x)		(((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) & BIT_MASK_MACID127_96_PKTSLEEP)
#define BIT_SET_MACID127_96_PKTSLEEP(x, v)		(BIT_CLEAR_MACID127_96_PKTSLEEP(x) | BIT_MACID127_96_PKTSLEEP(v))

/* 2 REG_MACID_SLEEP1			(Offset 0x0488) */

#define BIT_SHIFT_MACID63_32_PKTSLEEP			0
#define BIT_MASK_MACID63_32_PKTSLEEP			0xffffffffL
#define BIT_MACID63_32_PKTSLEEP(x)			(((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP)
#define BITS_MACID63_32_PKTSLEEP			(BIT_MASK_MACID63_32_PKTSLEEP << BIT_SHIFT_MACID63_32_PKTSLEEP)
#define BIT_CLEAR_MACID63_32_PKTSLEEP(x)		((x) & (~BITS_MACID63_32_PKTSLEEP))
#define BIT_GET_MACID63_32_PKTSLEEP(x)			(((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP)
#define BIT_SET_MACID63_32_PKTSLEEP(x, v)		(BIT_CLEAR_MACID63_32_PKTSLEEP(x) | BIT_MACID63_32_PKTSLEEP(v))

/* 2 REG_ARFR2_V1				(Offset 0x048C) */

#define BIT_SHIFT_ADPT_RATE_TABLE_L2			0
#define BIT_MASK_ADPT_RATE_TABLE_L2			0xffffffffL
#define BIT_ADPT_RATE_TABLE_L2(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_L2) << BIT_SHIFT_ADPT_RATE_TABLE_L2)
#define BITS_ADPT_RATE_TABLE_L2			(BIT_MASK_ADPT_RATE_TABLE_L2 << BIT_SHIFT_ADPT_RATE_TABLE_L2)
#define BIT_CLEAR_ADPT_RATE_TABLE_L2(x)		((x) & (~BITS_ADPT_RATE_TABLE_L2))
#define BIT_GET_ADPT_RATE_TABLE_L2(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_L2) & BIT_MASK_ADPT_RATE_TABLE_L2)
#define BIT_SET_ADPT_RATE_TABLE_L2(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_L2(x) | BIT_ADPT_RATE_TABLE_L2(v))

/* 2 REG_ARFRH2_V1_H				(Offset 0x0490) */

#define BIT_SHIFT_ADPT_RATE_TABLE_H2			0
#define BIT_MASK_ADPT_RATE_TABLE_H2			0xffffffffL
#define BIT_ADPT_RATE_TABLE_H2(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_H2) << BIT_SHIFT_ADPT_RATE_TABLE_H2)
#define BITS_ADPT_RATE_TABLE_H2			(BIT_MASK_ADPT_RATE_TABLE_H2 << BIT_SHIFT_ADPT_RATE_TABLE_H2)
#define BIT_CLEAR_ADPT_RATE_TABLE_H2(x)		((x) & (~BITS_ADPT_RATE_TABLE_H2))
#define BIT_GET_ADPT_RATE_TABLE_H2(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_H2) & BIT_MASK_ADPT_RATE_TABLE_H2)
#define BIT_SET_ADPT_RATE_TABLE_H2(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_H2(x) | BIT_ADPT_RATE_TABLE_H2(v))

/* 2 REG_ARFR3_V1				(Offset 0x0494) */

#define BIT_SHIFT_ADPT_RATE_TABLE_L3			0
#define BIT_MASK_ADPT_RATE_TABLE_L3			0xffffffffL
#define BIT_ADPT_RATE_TABLE_L3(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_L3) << BIT_SHIFT_ADPT_RATE_TABLE_L3)
#define BITS_ADPT_RATE_TABLE_L3			(BIT_MASK_ADPT_RATE_TABLE_L3 << BIT_SHIFT_ADPT_RATE_TABLE_L3)
#define BIT_CLEAR_ADPT_RATE_TABLE_L3(x)		((x) & (~BITS_ADPT_RATE_TABLE_L3))
#define BIT_GET_ADPT_RATE_TABLE_L3(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_L3) & BIT_MASK_ADPT_RATE_TABLE_L3)
#define BIT_SET_ADPT_RATE_TABLE_L3(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_L3(x) | BIT_ADPT_RATE_TABLE_L3(v))

/* 2 REG_ARFRH3_V1_H				(Offset 0x0498) */

#define BIT_SHIFT_ADPT_RATE_TABLE_H3			0
#define BIT_MASK_ADPT_RATE_TABLE_H3			0xffffffffL
#define BIT_ADPT_RATE_TABLE_H3(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_H3) << BIT_SHIFT_ADPT_RATE_TABLE_H3)
#define BITS_ADPT_RATE_TABLE_H3			(BIT_MASK_ADPT_RATE_TABLE_H3 << BIT_SHIFT_ADPT_RATE_TABLE_H3)
#define BIT_CLEAR_ADPT_RATE_TABLE_H3(x)		((x) & (~BITS_ADPT_RATE_TABLE_H3))
#define BIT_GET_ADPT_RATE_TABLE_H3(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_H3) & BIT_MASK_ADPT_RATE_TABLE_H3)
#define BIT_SET_ADPT_RATE_TABLE_H3(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_H3(x) | BIT_ADPT_RATE_TABLE_H3(v))

/* 2 REG_ARFR4				(Offset 0x049C) */

#define BIT_SHIFT_ADPT_RATE_TABLE_L4			0
#define BIT_MASK_ADPT_RATE_TABLE_L4			0xffffffffL
#define BIT_ADPT_RATE_TABLE_L4(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_L4) << BIT_SHIFT_ADPT_RATE_TABLE_L4)
#define BITS_ADPT_RATE_TABLE_L4			(BIT_MASK_ADPT_RATE_TABLE_L4 << BIT_SHIFT_ADPT_RATE_TABLE_L4)
#define BIT_CLEAR_ADPT_RATE_TABLE_L4(x)		((x) & (~BITS_ADPT_RATE_TABLE_L4))
#define BIT_GET_ADPT_RATE_TABLE_L4(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_L4) & BIT_MASK_ADPT_RATE_TABLE_L4)
#define BIT_SET_ADPT_RATE_TABLE_L4(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_L4(x) | BIT_ADPT_RATE_TABLE_L4(v))

/* 2 REG_ARFRH4_H				(Offset 0x04A0) */

#define BIT_SHIFT_ADPT_RATE_TABLE_H4			0
#define BIT_MASK_ADPT_RATE_TABLE_H4			0xffffffffL
#define BIT_ADPT_RATE_TABLE_H4(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_H4) << BIT_SHIFT_ADPT_RATE_TABLE_H4)
#define BITS_ADPT_RATE_TABLE_H4			(BIT_MASK_ADPT_RATE_TABLE_H4 << BIT_SHIFT_ADPT_RATE_TABLE_H4)
#define BIT_CLEAR_ADPT_RATE_TABLE_H4(x)		((x) & (~BITS_ADPT_RATE_TABLE_H4))
#define BIT_GET_ADPT_RATE_TABLE_H4(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_H4) & BIT_MASK_ADPT_RATE_TABLE_H4)
#define BIT_SET_ADPT_RATE_TABLE_H4(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_H4(x) | BIT_ADPT_RATE_TABLE_H4(v))

/* 2 REG_ARFR5				(Offset 0x04A4) */

#define BIT_SHIFT_ADPT_RATE_TABLE_L5			0
#define BIT_MASK_ADPT_RATE_TABLE_L5			0xffffffffL
#define BIT_ADPT_RATE_TABLE_L5(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_L5) << BIT_SHIFT_ADPT_RATE_TABLE_L5)
#define BITS_ADPT_RATE_TABLE_L5			(BIT_MASK_ADPT_RATE_TABLE_L5 << BIT_SHIFT_ADPT_RATE_TABLE_L5)
#define BIT_CLEAR_ADPT_RATE_TABLE_L5(x)		((x) & (~BITS_ADPT_RATE_TABLE_L5))
#define BIT_GET_ADPT_RATE_TABLE_L5(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_L5) & BIT_MASK_ADPT_RATE_TABLE_L5)
#define BIT_SET_ADPT_RATE_TABLE_L5(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_L5(x) | BIT_ADPT_RATE_TABLE_L5(v))

/* 2 REG_ARFRH5				(Offset 0x04A8) */

#define BIT_SHIFT_ADPT_RATE_TABLE_H5			0
#define BIT_MASK_ADPT_RATE_TABLE_H5			0xffffffffL
#define BIT_ADPT_RATE_TABLE_H5(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_H5) << BIT_SHIFT_ADPT_RATE_TABLE_H5)
#define BITS_ADPT_RATE_TABLE_H5			(BIT_MASK_ADPT_RATE_TABLE_H5 << BIT_SHIFT_ADPT_RATE_TABLE_H5)
#define BIT_CLEAR_ADPT_RATE_TABLE_H5(x)		((x) & (~BITS_ADPT_RATE_TABLE_H5))
#define BIT_GET_ADPT_RATE_TABLE_H5(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_H5) & BIT_MASK_ADPT_RATE_TABLE_H5)
#define BIT_SET_ADPT_RATE_TABLE_H5(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_H5(x) | BIT_ADPT_RATE_TABLE_H5(v))

/* 2 REG_TXRPT_START_OFFSET			(Offset 0x04AC) */

#define BIT_RPTFIFO_1K					BIT(16)

#define BIT_SHIFT_MACID_CTRL_OFFSET			8
#define BIT_MASK_MACID_CTRL_OFFSET			0xff
#define BIT_MACID_CTRL_OFFSET(x)			(((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET)
#define BITS_MACID_CTRL_OFFSET				(BIT_MASK_MACID_CTRL_OFFSET << BIT_SHIFT_MACID_CTRL_OFFSET)
#define BIT_CLEAR_MACID_CTRL_OFFSET(x)			((x) & (~BITS_MACID_CTRL_OFFSET))
#define BIT_GET_MACID_CTRL_OFFSET(x)			(((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET)
#define BIT_SET_MACID_CTRL_OFFSET(x, v)		(BIT_CLEAR_MACID_CTRL_OFFSET(x) | BIT_MACID_CTRL_OFFSET(v))

#define BIT_SHIFT_AMPDU_TXRPT_OFFSET			0
#define BIT_MASK_AMPDU_TXRPT_OFFSET			0xff
#define BIT_AMPDU_TXRPT_OFFSET(x)			(((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET)
#define BITS_AMPDU_TXRPT_OFFSET			(BIT_MASK_AMPDU_TXRPT_OFFSET << BIT_SHIFT_AMPDU_TXRPT_OFFSET)
#define BIT_CLEAR_AMPDU_TXRPT_OFFSET(x)		((x) & (~BITS_AMPDU_TXRPT_OFFSET))
#define BIT_GET_AMPDU_TXRPT_OFFSET(x)			(((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET)
#define BIT_SET_AMPDU_TXRPT_OFFSET(x, v)		(BIT_CLEAR_AMPDU_TXRPT_OFFSET(x) | BIT_AMPDU_TXRPT_OFFSET(v))

/* 2 REG_POWER_STAGE1			(Offset 0x04B4) */

#define BIT_PTA_WL_PRI_MASK_CPU_MGQ			BIT(31)
#define BIT_PTA_WL_PRI_MASK_BCNQ			BIT(30)
#define BIT_PTA_WL_PRI_MASK_HIQ			BIT(29)
#define BIT_PTA_WL_PRI_MASK_MGQ			BIT(28)
#define BIT_PTA_WL_PRI_MASK_BK				BIT(27)
#define BIT_PTA_WL_PRI_MASK_BE				BIT(26)
#define BIT_PTA_WL_PRI_MASK_VI				BIT(25)
#define BIT_PTA_WL_PRI_MASK_VO				BIT(24)

#define BIT_SHIFT_POWER_STAGE1				0
#define BIT_MASK_POWER_STAGE1				0xffffff
#define BIT_POWER_STAGE1(x)				(((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1)
#define BITS_POWER_STAGE1				(BIT_MASK_POWER_STAGE1 << BIT_SHIFT_POWER_STAGE1)
#define BIT_CLEAR_POWER_STAGE1(x)			((x) & (~BITS_POWER_STAGE1))
#define BIT_GET_POWER_STAGE1(x)			(((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1)
#define BIT_SET_POWER_STAGE1(x, v)			(BIT_CLEAR_POWER_STAGE1(x) | BIT_POWER_STAGE1(v))

/* 2 REG_POWER_STAGE2			(Offset 0x04B8) */

#define BIT_PTA_WL_PRI_MASK_EVT			BIT(25)
#define BIT_CTRL_PKT_PWR_ADJ_EN			BIT(24)

#define BIT_SHIFT_DMA_THIS_QUEUE			20
#define BIT_MASK_DMA_THIS_QUEUE			0xf
#define BIT_DMA_THIS_QUEUE(x)				(((x) & BIT_MASK_DMA_THIS_QUEUE) << BIT_SHIFT_DMA_THIS_QUEUE)
#define BITS_DMA_THIS_QUEUE				(BIT_MASK_DMA_THIS_QUEUE << BIT_SHIFT_DMA_THIS_QUEUE)
#define BIT_CLEAR_DMA_THIS_QUEUE(x)			((x) & (~BITS_DMA_THIS_QUEUE))
#define BIT_GET_DMA_THIS_QUEUE(x)			(((x) >> BIT_SHIFT_DMA_THIS_QUEUE) & BIT_MASK_DMA_THIS_QUEUE)
#define BIT_SET_DMA_THIS_QUEUE(x, v)			(BIT_CLEAR_DMA_THIS_QUEUE(x) | BIT_DMA_THIS_QUEUE(v))

#define BIT_SHIFT_TOTAL_LEN_THRS			8
#define BIT_MASK_TOTAL_LEN_THRS			0xfff
#define BIT_TOTAL_LEN_THRS(x)				(((x) & BIT_MASK_TOTAL_LEN_THRS) << BIT_SHIFT_TOTAL_LEN_THRS)
#define BITS_TOTAL_LEN_THRS				(BIT_MASK_TOTAL_LEN_THRS << BIT_SHIFT_TOTAL_LEN_THRS)
#define BIT_CLEAR_TOTAL_LEN_THRS(x)			((x) & (~BITS_TOTAL_LEN_THRS))
#define BIT_GET_TOTAL_LEN_THRS(x)			(((x) >> BIT_SHIFT_TOTAL_LEN_THRS) & BIT_MASK_TOTAL_LEN_THRS)
#define BIT_SET_TOTAL_LEN_THRS(x, v)			(BIT_CLEAR_TOTAL_LEN_THRS(x) | BIT_TOTAL_LEN_THRS(v))

#define BIT_WEP_PRETX_EN				BIT(7)
#define BIT_PRE_TX_CMD					BIT(6)

#define BIT_SHIFT_NUM_SCL_EN				4
#define BIT_MASK_NUM_SCL_EN				0x3
#define BIT_NUM_SCL_EN(x)				(((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN)
#define BITS_NUM_SCL_EN				(BIT_MASK_NUM_SCL_EN << BIT_SHIFT_NUM_SCL_EN)
#define BIT_CLEAR_NUM_SCL_EN(x)			((x) & (~BITS_NUM_SCL_EN))
#define BIT_GET_NUM_SCL_EN(x)				(((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN)
#define BIT_SET_NUM_SCL_EN(x, v)			(BIT_CLEAR_NUM_SCL_EN(x) | BIT_NUM_SCL_EN(v))

#define BIT_BK_EN					BIT(3)
#define BIT_BE_EN					BIT(2)
#define BIT_VI_EN					BIT(1)

#define BIT_SHIFT_POWER_STAGE2				0
#define BIT_MASK_POWER_STAGE2				0xffffff
#define BIT_POWER_STAGE2(x)				(((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2)
#define BITS_POWER_STAGE2				(BIT_MASK_POWER_STAGE2 << BIT_SHIFT_POWER_STAGE2)
#define BIT_CLEAR_POWER_STAGE2(x)			((x) & (~BITS_POWER_STAGE2))
#define BIT_GET_POWER_STAGE2(x)			(((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2)
#define BIT_SET_POWER_STAGE2(x, v)			(BIT_CLEAR_POWER_STAGE2(x) | BIT_POWER_STAGE2(v))

#define BIT_VO_EN					BIT(0)

/* 2 REG_PKT_LIFE_TIME			(Offset 0x04C0) */

#define BIT_SHIFT_PKT_LIFTIME_BEBK			16
#define BIT_MASK_PKT_LIFTIME_BEBK			0xffff
#define BIT_PKT_LIFTIME_BEBK(x)			(((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK)
#define BITS_PKT_LIFTIME_BEBK				(BIT_MASK_PKT_LIFTIME_BEBK << BIT_SHIFT_PKT_LIFTIME_BEBK)
#define BIT_CLEAR_PKT_LIFTIME_BEBK(x)			((x) & (~BITS_PKT_LIFTIME_BEBK))
#define BIT_GET_PKT_LIFTIME_BEBK(x)			(((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK)
#define BIT_SET_PKT_LIFTIME_BEBK(x, v)			(BIT_CLEAR_PKT_LIFTIME_BEBK(x) | BIT_PKT_LIFTIME_BEBK(v))

#define BIT_SHIFT_PKT_LIFTIME_VOVI			0
#define BIT_MASK_PKT_LIFTIME_VOVI			0xffff
#define BIT_PKT_LIFTIME_VOVI(x)			(((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI)
#define BITS_PKT_LIFTIME_VOVI				(BIT_MASK_PKT_LIFTIME_VOVI << BIT_SHIFT_PKT_LIFTIME_VOVI)
#define BIT_CLEAR_PKT_LIFTIME_VOVI(x)			((x) & (~BITS_PKT_LIFTIME_VOVI))
#define BIT_GET_PKT_LIFTIME_VOVI(x)			(((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI)
#define BIT_SET_PKT_LIFTIME_VOVI(x, v)			(BIT_CLEAR_PKT_LIFTIME_VOVI(x) | BIT_PKT_LIFTIME_VOVI(v))

/* 2 REG_STBC_SETTING			(Offset 0x04C4) */

#define BIT_SHIFT_CDEND_TXTIME_L			4
#define BIT_MASK_CDEND_TXTIME_L			0xf
#define BIT_CDEND_TXTIME_L(x)				(((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L)
#define BITS_CDEND_TXTIME_L				(BIT_MASK_CDEND_TXTIME_L << BIT_SHIFT_CDEND_TXTIME_L)
#define BIT_CLEAR_CDEND_TXTIME_L(x)			((x) & (~BITS_CDEND_TXTIME_L))
#define BIT_GET_CDEND_TXTIME_L(x)			(((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L)
#define BIT_SET_CDEND_TXTIME_L(x, v)			(BIT_CLEAR_CDEND_TXTIME_L(x) | BIT_CDEND_TXTIME_L(v))

#define BIT_SHIFT_NESS					2
#define BIT_MASK_NESS					0x3
#define BIT_NESS(x)					(((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS)
#define BITS_NESS					(BIT_MASK_NESS << BIT_SHIFT_NESS)
#define BIT_CLEAR_NESS(x)				((x) & (~BITS_NESS))
#define BIT_GET_NESS(x)				(((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS)
#define BIT_SET_NESS(x, v)				(BIT_CLEAR_NESS(x) | BIT_NESS(v))

#define BIT_SHIFT_STBC_CFEND				0
#define BIT_MASK_STBC_CFEND				0x3
#define BIT_STBC_CFEND(x)				(((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND)
#define BITS_STBC_CFEND				(BIT_MASK_STBC_CFEND << BIT_SHIFT_STBC_CFEND)
#define BIT_CLEAR_STBC_CFEND(x)			((x) & (~BITS_STBC_CFEND))
#define BIT_GET_STBC_CFEND(x)				(((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND)
#define BIT_SET_STBC_CFEND(x, v)			(BIT_CLEAR_STBC_CFEND(x) | BIT_STBC_CFEND(v))

/* 2 REG_STBC_SETTING2			(Offset 0x04C5) */

#define BIT_FORCE_RND_PRI				BIT(6)
#define BIT_PTA_EDCCA_EN				BIT(5)
#define BIT_PTA_WL_TX_EN				BIT(4)
#define BIT_R_USE_DATA_BW				BIT(3)
#define BIT_TRI_PKT_STATUS				BIT(2)
#define BIT_TRI_PKT_PKTIN				BIT(1)

#define BIT_SHIFT_CDEND_TXTIME_H			0
#define BIT_MASK_CDEND_TXTIME_H			0x1f
#define BIT_CDEND_TXTIME_H(x)				(((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H)
#define BITS_CDEND_TXTIME_H				(BIT_MASK_CDEND_TXTIME_H << BIT_SHIFT_CDEND_TXTIME_H)
#define BIT_CLEAR_CDEND_TXTIME_H(x)			((x) & (~BITS_CDEND_TXTIME_H))
#define BIT_GET_CDEND_TXTIME_H(x)			(((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H)
#define BIT_SET_CDEND_TXTIME_H(x, v)			(BIT_CLEAR_CDEND_TXTIME_H(x) | BIT_CDEND_TXTIME_H(v))

#define BIT_ACQ_MODE_SEL				BIT(0)

/* 2 REG_SINGLE_AMPDU_CTRL			(Offset 0x04C7) */

#define BIT_EN_SINGLE_APMDU				BIT(7)

/* 2 REG_PROT_MODE_CTRL			(Offset 0x04C8) */

#define BIT_SHIFT_RTS_MAX_AGG_NUM			24
#define BIT_MASK_RTS_MAX_AGG_NUM			0x3f
#define BIT_RTS_MAX_AGG_NUM(x)				(((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM)
#define BITS_RTS_MAX_AGG_NUM				(BIT_MASK_RTS_MAX_AGG_NUM << BIT_SHIFT_RTS_MAX_AGG_NUM)
#define BIT_CLEAR_RTS_MAX_AGG_NUM(x)			((x) & (~BITS_RTS_MAX_AGG_NUM))
#define BIT_GET_RTS_MAX_AGG_NUM(x)			(((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM)
#define BIT_SET_RTS_MAX_AGG_NUM(x, v)			(BIT_CLEAR_RTS_MAX_AGG_NUM(x) | BIT_RTS_MAX_AGG_NUM(v))

#define BIT_SHIFT_MAX_AGG_NUM				16
#define BIT_MASK_MAX_AGG_NUM				0x3f
#define BIT_MAX_AGG_NUM(x)				(((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM)
#define BITS_MAX_AGG_NUM				(BIT_MASK_MAX_AGG_NUM << BIT_SHIFT_MAX_AGG_NUM)
#define BIT_CLEAR_MAX_AGG_NUM(x)			((x) & (~BITS_MAX_AGG_NUM))
#define BIT_GET_MAX_AGG_NUM(x)				(((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM)
#define BIT_SET_MAX_AGG_NUM(x, v)			(BIT_CLEAR_MAX_AGG_NUM(x) | BIT_MAX_AGG_NUM(v))

#define BIT_SHIFT_RTS_TXTIME_TH			8
#define BIT_MASK_RTS_TXTIME_TH				0xff
#define BIT_RTS_TXTIME_TH(x)				(((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH)
#define BITS_RTS_TXTIME_TH				(BIT_MASK_RTS_TXTIME_TH << BIT_SHIFT_RTS_TXTIME_TH)
#define BIT_CLEAR_RTS_TXTIME_TH(x)			((x) & (~BITS_RTS_TXTIME_TH))
#define BIT_GET_RTS_TXTIME_TH(x)			(((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH)
#define BIT_SET_RTS_TXTIME_TH(x, v)			(BIT_CLEAR_RTS_TXTIME_TH(x) | BIT_RTS_TXTIME_TH(v))

#define BIT_SHIFT_RTS_LEN_TH				0
#define BIT_MASK_RTS_LEN_TH				0xff
#define BIT_RTS_LEN_TH(x)				(((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH)
#define BITS_RTS_LEN_TH				(BIT_MASK_RTS_LEN_TH << BIT_SHIFT_RTS_LEN_TH)
#define BIT_CLEAR_RTS_LEN_TH(x)			((x) & (~BITS_RTS_LEN_TH))
#define BIT_GET_RTS_LEN_TH(x)				(((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH)
#define BIT_SET_RTS_LEN_TH(x, v)			(BIT_CLEAR_RTS_LEN_TH(x) | BIT_RTS_LEN_TH(v))

/* 2 REG_BAR_MODE_CTRL			(Offset 0x04CC) */

#define BIT_SHIFT_RTY_PKT_LMT				24
#define BIT_MASK_RTY_PKT_LMT				0x3f
#define BIT_RTY_PKT_LMT(x)				(((x) & BIT_MASK_RTY_PKT_LMT) << BIT_SHIFT_RTY_PKT_LMT)
#define BITS_RTY_PKT_LMT				(BIT_MASK_RTY_PKT_LMT << BIT_SHIFT_RTY_PKT_LMT)
#define BIT_CLEAR_RTY_PKT_LMT(x)			((x) & (~BITS_RTY_PKT_LMT))
#define BIT_GET_RTY_PKT_LMT(x)				(((x) >> BIT_SHIFT_RTY_PKT_LMT) & BIT_MASK_RTY_PKT_LMT)
#define BIT_SET_RTY_PKT_LMT(x, v)			(BIT_CLEAR_RTY_PKT_LMT(x) | BIT_RTY_PKT_LMT(v))

#define BIT_SHIFT_BAR_RTY_LMT				16
#define BIT_MASK_BAR_RTY_LMT				0x3
#define BIT_BAR_RTY_LMT(x)				(((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT)
#define BITS_BAR_RTY_LMT				(BIT_MASK_BAR_RTY_LMT << BIT_SHIFT_BAR_RTY_LMT)
#define BIT_CLEAR_BAR_RTY_LMT(x)			((x) & (~BITS_BAR_RTY_LMT))
#define BIT_GET_BAR_RTY_LMT(x)				(((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT)
#define BIT_SET_BAR_RTY_LMT(x, v)			(BIT_CLEAR_BAR_RTY_LMT(x) | BIT_BAR_RTY_LMT(v))

#define BIT_SHIFT_BAR_PKTTIME_THRS			8
#define BIT_MASK_BAR_PKTTIME_THRS			0xff
#define BIT_BAR_PKTTIME_THRS(x)			(((x) & BIT_MASK_BAR_PKTTIME_THRS) << BIT_SHIFT_BAR_PKTTIME_THRS)
#define BITS_BAR_PKTTIME_THRS				(BIT_MASK_BAR_PKTTIME_THRS << BIT_SHIFT_BAR_PKTTIME_THRS)
#define BIT_CLEAR_BAR_PKTTIME_THRS(x)			((x) & (~BITS_BAR_PKTTIME_THRS))
#define BIT_GET_BAR_PKTTIME_THRS(x)			(((x) >> BIT_SHIFT_BAR_PKTTIME_THRS) & BIT_MASK_BAR_PKTTIME_THRS)
#define BIT_SET_BAR_PKTTIME_THRS(x, v)			(BIT_CLEAR_BAR_PKTTIME_THRS(x) | BIT_BAR_PKTTIME_THRS(v))

#define BIT_SHIFT_BAR_PKTNUM_TH_V1			0
#define BIT_MASK_BAR_PKTNUM_TH_V1			0x7f
#define BIT_BAR_PKTNUM_TH_V1(x)			(((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1)
#define BITS_BAR_PKTNUM_TH_V1				(BIT_MASK_BAR_PKTNUM_TH_V1 << BIT_SHIFT_BAR_PKTNUM_TH_V1)
#define BIT_CLEAR_BAR_PKTNUM_TH_V1(x)			((x) & (~BITS_BAR_PKTNUM_TH_V1))
#define BIT_GET_BAR_PKTNUM_TH_V1(x)			(((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1)
#define BIT_SET_BAR_PKTNUM_TH_V1(x, v)			(BIT_CLEAR_BAR_PKTNUM_TH_V1(x) | BIT_BAR_PKTNUM_TH_V1(v))

/* 2 REG_MACID_SLEEP2			(Offset 0x04D0) */

#define BIT_SHIFT_MACID95_64PKTSLEEP			0
#define BIT_MASK_MACID95_64PKTSLEEP			0xffffffffL
#define BIT_MACID95_64PKTSLEEP(x)			(((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP)
#define BITS_MACID95_64PKTSLEEP			(BIT_MASK_MACID95_64PKTSLEEP << BIT_SHIFT_MACID95_64PKTSLEEP)
#define BIT_CLEAR_MACID95_64PKTSLEEP(x)		((x) & (~BITS_MACID95_64PKTSLEEP))
#define BIT_GET_MACID95_64PKTSLEEP(x)			(((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP)
#define BIT_SET_MACID95_64PKTSLEEP(x, v)		(BIT_CLEAR_MACID95_64PKTSLEEP(x) | BIT_MACID95_64PKTSLEEP(v))

/* 2 REG_MACID_SLEEP				(Offset 0x04D4) */

#define BIT_SHIFT_MACID31_0_PKTSLEEP			0
#define BIT_MASK_MACID31_0_PKTSLEEP			0xffffffffL
#define BIT_MACID31_0_PKTSLEEP(x)			(((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP)
#define BITS_MACID31_0_PKTSLEEP			(BIT_MASK_MACID31_0_PKTSLEEP << BIT_SHIFT_MACID31_0_PKTSLEEP)
#define BIT_CLEAR_MACID31_0_PKTSLEEP(x)		((x) & (~BITS_MACID31_0_PKTSLEEP))
#define BIT_GET_MACID31_0_PKTSLEEP(x)			(((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP)
#define BIT_SET_MACID31_0_PKTSLEEP(x, v)		(BIT_CLEAR_MACID31_0_PKTSLEEP(x) | BIT_MACID31_0_PKTSLEEP(v))

#define BIT_SHIFT_HW_SSN_SEQ0				0
#define BIT_MASK_HW_SSN_SEQ0				0xfff
#define BIT_HW_SSN_SEQ0(x)				(((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0)
#define BITS_HW_SSN_SEQ0				(BIT_MASK_HW_SSN_SEQ0 << BIT_SHIFT_HW_SSN_SEQ0)
#define BIT_CLEAR_HW_SSN_SEQ0(x)			((x) & (~BITS_HW_SSN_SEQ0))
#define BIT_GET_HW_SSN_SEQ0(x)				(((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0)
#define BIT_SET_HW_SSN_SEQ0(x, v)			(BIT_CLEAR_HW_SSN_SEQ0(x) | BIT_HW_SSN_SEQ0(v))

#define BIT_SHIFT_HW_SSN_SEQ1				0
#define BIT_MASK_HW_SSN_SEQ1				0xfff
#define BIT_HW_SSN_SEQ1(x)				(((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1)
#define BITS_HW_SSN_SEQ1				(BIT_MASK_HW_SSN_SEQ1 << BIT_SHIFT_HW_SSN_SEQ1)
#define BIT_CLEAR_HW_SSN_SEQ1(x)			((x) & (~BITS_HW_SSN_SEQ1))
#define BIT_GET_HW_SSN_SEQ1(x)				(((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1)
#define BIT_SET_HW_SSN_SEQ1(x, v)			(BIT_CLEAR_HW_SSN_SEQ1(x) | BIT_HW_SSN_SEQ1(v))

#define BIT_SHIFT_HW_SSN_SEQ2				0
#define BIT_MASK_HW_SSN_SEQ2				0xfff
#define BIT_HW_SSN_SEQ2(x)				(((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2)
#define BITS_HW_SSN_SEQ2				(BIT_MASK_HW_SSN_SEQ2 << BIT_SHIFT_HW_SSN_SEQ2)
#define BIT_CLEAR_HW_SSN_SEQ2(x)			((x) & (~BITS_HW_SSN_SEQ2))
#define BIT_GET_HW_SSN_SEQ2(x)				(((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2)
#define BIT_SET_HW_SSN_SEQ2(x, v)			(BIT_CLEAR_HW_SSN_SEQ2(x) | BIT_HW_SSN_SEQ2(v))

#define BIT_SHIFT_HW_SSN_SEQ3				0
#define BIT_MASK_HW_SSN_SEQ3				0xfff
#define BIT_HW_SSN_SEQ3(x)				(((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3)
#define BITS_HW_SSN_SEQ3				(BIT_MASK_HW_SSN_SEQ3 << BIT_SHIFT_HW_SSN_SEQ3)
#define BIT_CLEAR_HW_SSN_SEQ3(x)			((x) & (~BITS_HW_SSN_SEQ3))
#define BIT_GET_HW_SSN_SEQ3(x)				(((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3)
#define BIT_SET_HW_SSN_SEQ3(x, v)			(BIT_CLEAR_HW_SSN_SEQ3(x) | BIT_HW_SSN_SEQ3(v))

/* 2 REG_NULL_PKT_STATUS			(Offset 0x04E0) */

#define BIT_RD_FTMT2R_ERR				BIT(15)
#define BIT_CLI3_TX_NULL_1				BIT(9)
#define BIT_CLI3_TX_NULL_0				BIT(8)
#define BIT_CLI2_TX_NULL_1				BIT(7)
#define BIT_CLI2_TX_NULL_0				BIT(6)
#define BIT_CLI1_TX_NULL_1				BIT(5)
#define BIT_CLI1_TX_NULL_0				BIT(4)
#define BIT_CLI0_TX_NULL_1				BIT(3)
#define BIT_CLI0_TX_NULL_0				BIT(2)
#define BIT_TX_NULL_1					BIT(1)
#define BIT_TX_NULL_0					BIT(0)

/* 2 REG_PTCL_ERR_STATUS			(Offset 0x04E2) */

#define BIT_PTCL_TOTAL_PG_H				BIT(7)
#define BIT_PTCL_RATE_TABLE_INVALID			BIT(6)
#define BIT_RD_TXHANG_ERR				BIT(5)
#define BIT_RD_STATUS_ERR				BIT(4)
#define BIT_RD_CTN_ERR					BIT(3)

#define BIT_SHIFT_RD_PKTIN_ERR				0
#define BIT_MASK_RD_PKTIN_ERR				0x7
#define BIT_RD_PKTIN_ERR(x)				(((x) & BIT_MASK_RD_PKTIN_ERR) << BIT_SHIFT_RD_PKTIN_ERR)
#define BITS_RD_PKTIN_ERR				(BIT_MASK_RD_PKTIN_ERR << BIT_SHIFT_RD_PKTIN_ERR)
#define BIT_CLEAR_RD_PKTIN_ERR(x)			((x) & (~BITS_RD_PKTIN_ERR))
#define BIT_GET_RD_PKTIN_ERR(x)			(((x) >> BIT_SHIFT_RD_PKTIN_ERR) & BIT_MASK_RD_PKTIN_ERR)
#define BIT_SET_RD_PKTIN_ERR(x, v)			(BIT_CLEAR_RD_PKTIN_ERR(x) | BIT_RD_PKTIN_ERR(v))

/* 2 REG_PTCL_PKT_NUM			(Offset 0x04E3) */

#define BIT_HGQ_DEL_EN					BIT(7)
#define BIT_MGQ_DEL_EN					BIT(6)

#define BIT_SHIFT_PTCL_TOTAL_PG_L			0
#define BIT_MASK_PTCL_TOTAL_PG_L			0xff
#define BIT_PTCL_TOTAL_PG_L(x)				(((x) & BIT_MASK_PTCL_TOTAL_PG_L) << BIT_SHIFT_PTCL_TOTAL_PG_L)
#define BITS_PTCL_TOTAL_PG_L				(BIT_MASK_PTCL_TOTAL_PG_L << BIT_SHIFT_PTCL_TOTAL_PG_L)
#define BIT_CLEAR_PTCL_TOTAL_PG_L(x)			((x) & (~BITS_PTCL_TOTAL_PG_L))
#define BIT_GET_PTCL_TOTAL_PG_L(x)			(((x) >> BIT_SHIFT_PTCL_TOTAL_PG_L) & BIT_MASK_PTCL_TOTAL_PG_L)
#define BIT_SET_PTCL_TOTAL_PG_L(x, v)			(BIT_CLEAR_PTCL_TOTAL_PG_L(x) | BIT_PTCL_TOTAL_PG_L(v))

/* 2 REG_PRECNT_CTRL				(Offset 0x04E5) */

#define BIT_SHIFT_COLLI_DETEC_TIME_MAX			12
#define BIT_MASK_COLLI_DETEC_TIME_MAX			0xf
#define BIT_COLLI_DETEC_TIME_MAX(x)			(((x) & BIT_MASK_COLLI_DETEC_TIME_MAX) << BIT_SHIFT_COLLI_DETEC_TIME_MAX)
#define BITS_COLLI_DETEC_TIME_MAX			(BIT_MASK_COLLI_DETEC_TIME_MAX << BIT_SHIFT_COLLI_DETEC_TIME_MAX)
#define BIT_CLEAR_COLLI_DETEC_TIME_MAX(x)		((x) & (~BITS_COLLI_DETEC_TIME_MAX))
#define BIT_GET_COLLI_DETEC_TIME_MAX(x)		(((x) >> BIT_SHIFT_COLLI_DETEC_TIME_MAX) & BIT_MASK_COLLI_DETEC_TIME_MAX)
#define BIT_SET_COLLI_DETEC_TIME_MAX(x, v)		(BIT_CLEAR_COLLI_DETEC_TIME_MAX(x) | BIT_COLLI_DETEC_TIME_MAX(v))

#define BIT_PRETX_AGGR_EN				BIT(11)

#define BIT_SHIFT_PRETX_AGGR_TIME_MAX			0
#define BIT_MASK_PRETX_AGGR_TIME_MAX			0x7ff
#define BIT_PRETX_AGGR_TIME_MAX(x)			(((x) & BIT_MASK_PRETX_AGGR_TIME_MAX) << BIT_SHIFT_PRETX_AGGR_TIME_MAX)
#define BITS_PRETX_AGGR_TIME_MAX			(BIT_MASK_PRETX_AGGR_TIME_MAX << BIT_SHIFT_PRETX_AGGR_TIME_MAX)
#define BIT_CLEAR_PRETX_AGGR_TIME_MAX(x)		((x) & (~BITS_PRETX_AGGR_TIME_MAX))
#define BIT_GET_PRETX_AGGR_TIME_MAX(x)			(((x) >> BIT_SHIFT_PRETX_AGGR_TIME_MAX) & BIT_MASK_PRETX_AGGR_TIME_MAX)
#define BIT_SET_PRETX_AGGR_TIME_MAX(x, v)		(BIT_CLEAR_PRETX_AGGR_TIME_MAX(x) | BIT_PRETX_AGGR_TIME_MAX(v))

/* 2 REG_BT_POLLUTE_PKT_CNT			(Offset 0x04E8) */

#define BIT_SHIFT_BT_POLLUTE_PKT_CNT			0
#define BIT_MASK_BT_POLLUTE_PKT_CNT			0xffff
#define BIT_BT_POLLUTE_PKT_CNT(x)			(((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT)
#define BITS_BT_POLLUTE_PKT_CNT			(BIT_MASK_BT_POLLUTE_PKT_CNT << BIT_SHIFT_BT_POLLUTE_PKT_CNT)
#define BIT_CLEAR_BT_POLLUTE_PKT_CNT(x)		((x) & (~BITS_BT_POLLUTE_PKT_CNT))
#define BIT_GET_BT_POLLUTE_PKT_CNT(x)			(((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT)
#define BIT_SET_BT_POLLUTE_PKT_CNT(x, v)		(BIT_CLEAR_BT_POLLUTE_PKT_CNT(x) | BIT_BT_POLLUTE_PKT_CNT(v))

/* 2 REG_DROP_PKT_NUM			(Offset 0x04EC) */

#define BIT_SHIFT_LIFE_DROP_NUM			16
#define BIT_MASK_LIFE_DROP_NUM				0xffff
#define BIT_LIFE_DROP_NUM(x)				(((x) & BIT_MASK_LIFE_DROP_NUM) << BIT_SHIFT_LIFE_DROP_NUM)
#define BITS_LIFE_DROP_NUM				(BIT_MASK_LIFE_DROP_NUM << BIT_SHIFT_LIFE_DROP_NUM)
#define BIT_CLEAR_LIFE_DROP_NUM(x)			((x) & (~BITS_LIFE_DROP_NUM))
#define BIT_GET_LIFE_DROP_NUM(x)			(((x) >> BIT_SHIFT_LIFE_DROP_NUM) & BIT_MASK_LIFE_DROP_NUM)
#define BIT_SET_LIFE_DROP_NUM(x, v)			(BIT_CLEAR_LIFE_DROP_NUM(x) | BIT_LIFE_DROP_NUM(v))

#define BIT_SHIFT_MGQ_TRI_HEAD				16
#define BIT_MASK_MGQ_TRI_HEAD				0xfff
#define BIT_MGQ_TRI_HEAD(x)				(((x) & BIT_MASK_MGQ_TRI_HEAD) << BIT_SHIFT_MGQ_TRI_HEAD)
#define BITS_MGQ_TRI_HEAD				(BIT_MASK_MGQ_TRI_HEAD << BIT_SHIFT_MGQ_TRI_HEAD)
#define BIT_CLEAR_MGQ_TRI_HEAD(x)			((x) & (~BITS_MGQ_TRI_HEAD))
#define BIT_GET_MGQ_TRI_HEAD(x)			(((x) >> BIT_SHIFT_MGQ_TRI_HEAD) & BIT_MASK_MGQ_TRI_HEAD)
#define BIT_SET_MGQ_TRI_HEAD(x, v)			(BIT_CLEAR_MGQ_TRI_HEAD(x) | BIT_MGQ_TRI_HEAD(v))

#define BIT_CPUMGQ_TRI_LIFETIME_EN			BIT(8)

#define BIT_SHIFT_DROP_PKT_NUM				0
#define BIT_MASK_DROP_PKT_NUM				0xffff
#define BIT_DROP_PKT_NUM(x)				(((x) & BIT_MASK_DROP_PKT_NUM) << BIT_SHIFT_DROP_PKT_NUM)
#define BITS_DROP_PKT_NUM				(BIT_MASK_DROP_PKT_NUM << BIT_SHIFT_DROP_PKT_NUM)
#define BIT_CLEAR_DROP_PKT_NUM(x)			((x) & (~BITS_DROP_PKT_NUM))
#define BIT_GET_DROP_PKT_NUM(x)			(((x) >> BIT_SHIFT_DROP_PKT_NUM) & BIT_MASK_DROP_PKT_NUM)
#define BIT_SET_DROP_PKT_NUM(x, v)			(BIT_CLEAR_DROP_PKT_NUM(x) | BIT_DROP_PKT_NUM(v))

#define BIT_SHIFT_CPUMGQ_TRI_LIFETIME			0
#define BIT_MASK_CPUMGQ_TRI_LIFETIME			0xff
#define BIT_CPUMGQ_TRI_LIFETIME(x)			(((x) & BIT_MASK_CPUMGQ_TRI_LIFETIME) << BIT_SHIFT_CPUMGQ_TRI_LIFETIME)
#define BITS_CPUMGQ_TRI_LIFETIME			(BIT_MASK_CPUMGQ_TRI_LIFETIME << BIT_SHIFT_CPUMGQ_TRI_LIFETIME)
#define BIT_CLEAR_CPUMGQ_TRI_LIFETIME(x)		((x) & (~BITS_CPUMGQ_TRI_LIFETIME))
#define BIT_GET_CPUMGQ_TRI_LIFETIME(x)			(((x) >> BIT_SHIFT_CPUMGQ_TRI_LIFETIME) & BIT_MASK_CPUMGQ_TRI_LIFETIME)
#define BIT_SET_CPUMGQ_TRI_LIFETIME(x, v)		(BIT_CLEAR_CPUMGQ_TRI_LIFETIME(x) | BIT_CPUMGQ_TRI_LIFETIME(v))

/* 2 REG_DUMMY_PAGE4				(Offset 0x04FC) */

#define BIT_SHIFT_DUMMY_REG_1				18
#define BIT_MASK_DUMMY_REG_1				0x3fff
#define BIT_DUMMY_REG_1(x)				(((x) & BIT_MASK_DUMMY_REG_1) << BIT_SHIFT_DUMMY_REG_1)
#define BITS_DUMMY_REG_1				(BIT_MASK_DUMMY_REG_1 << BIT_SHIFT_DUMMY_REG_1)
#define BIT_CLEAR_DUMMY_REG_1(x)			((x) & (~BITS_DUMMY_REG_1))
#define BIT_GET_DUMMY_REG_1(x)				(((x) >> BIT_SHIFT_DUMMY_REG_1) & BIT_MASK_DUMMY_REG_1)
#define BIT_SET_DUMMY_REG_1(x, v)			(BIT_CLEAR_DUMMY_REG_1(x) | BIT_DUMMY_REG_1(v))

#define BIT_EN_BCN_TRXRPT_V1				BIT(17)

#define BIT_SHIFT_DUMMY_REG_0				0
#define BIT_MASK_DUMMY_REG_0				0x1ffff
#define BIT_DUMMY_REG_0(x)				(((x) & BIT_MASK_DUMMY_REG_0) << BIT_SHIFT_DUMMY_REG_0)
#define BITS_DUMMY_REG_0				(BIT_MASK_DUMMY_REG_0 << BIT_SHIFT_DUMMY_REG_0)
#define BIT_CLEAR_DUMMY_REG_0(x)			((x) & (~BITS_DUMMY_REG_0))
#define BIT_GET_DUMMY_REG_0(x)				(((x) >> BIT_SHIFT_DUMMY_REG_0) & BIT_MASK_DUMMY_REG_0)
#define BIT_SET_DUMMY_REG_0(x, v)			(BIT_CLEAR_DUMMY_REG_0(x) | BIT_DUMMY_REG_0(v))

/* 2 REG_EDCA_VO_PARAM			(Offset 0x0500) */

#define BIT_SHIFT_TXOPLIMIT				16
#define BIT_MASK_TXOPLIMIT				0x7ff
#define BIT_TXOPLIMIT(x)				(((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT)
#define BITS_TXOPLIMIT					(BIT_MASK_TXOPLIMIT << BIT_SHIFT_TXOPLIMIT)
#define BIT_CLEAR_TXOPLIMIT(x)				((x) & (~BITS_TXOPLIMIT))
#define BIT_GET_TXOPLIMIT(x)				(((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT)
#define BIT_SET_TXOPLIMIT(x, v)			(BIT_CLEAR_TXOPLIMIT(x) | BIT_TXOPLIMIT(v))

#define BIT_SHIFT_CW					8
#define BIT_MASK_CW					0xff
#define BIT_CW(x)					(((x) & BIT_MASK_CW) << BIT_SHIFT_CW)
#define BITS_CW					(BIT_MASK_CW << BIT_SHIFT_CW)
#define BIT_CLEAR_CW(x)				((x) & (~BITS_CW))
#define BIT_GET_CW(x)					(((x) >> BIT_SHIFT_CW) & BIT_MASK_CW)
#define BIT_SET_CW(x, v)				(BIT_CLEAR_CW(x) | BIT_CW(v))

#define BIT_SHIFT_AIFS					0
#define BIT_MASK_AIFS					0xff
#define BIT_AIFS(x)					(((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS)
#define BITS_AIFS					(BIT_MASK_AIFS << BIT_SHIFT_AIFS)
#define BIT_CLEAR_AIFS(x)				((x) & (~BITS_AIFS))
#define BIT_GET_AIFS(x)				(((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS)
#define BIT_SET_AIFS(x, v)				(BIT_CLEAR_AIFS(x) | BIT_AIFS(v))

/* 2 REG_BCNTCFG				(Offset 0x0510) */

#define BIT_SHIFT_BCNCW_MAX				12
#define BIT_MASK_BCNCW_MAX				0xf
#define BIT_BCNCW_MAX(x)				(((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX)
#define BITS_BCNCW_MAX					(BIT_MASK_BCNCW_MAX << BIT_SHIFT_BCNCW_MAX)
#define BIT_CLEAR_BCNCW_MAX(x)				((x) & (~BITS_BCNCW_MAX))
#define BIT_GET_BCNCW_MAX(x)				(((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX)
#define BIT_SET_BCNCW_MAX(x, v)			(BIT_CLEAR_BCNCW_MAX(x) | BIT_BCNCW_MAX(v))

#define BIT_SHIFT_BCNCW_MIN				8
#define BIT_MASK_BCNCW_MIN				0xf
#define BIT_BCNCW_MIN(x)				(((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN)
#define BITS_BCNCW_MIN					(BIT_MASK_BCNCW_MIN << BIT_SHIFT_BCNCW_MIN)
#define BIT_CLEAR_BCNCW_MIN(x)				((x) & (~BITS_BCNCW_MIN))
#define BIT_GET_BCNCW_MIN(x)				(((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN)
#define BIT_SET_BCNCW_MIN(x, v)			(BIT_CLEAR_BCNCW_MIN(x) | BIT_BCNCW_MIN(v))

#define BIT_SHIFT_BCNIFS				0
#define BIT_MASK_BCNIFS				0xff
#define BIT_BCNIFS(x)					(((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS)
#define BITS_BCNIFS					(BIT_MASK_BCNIFS << BIT_SHIFT_BCNIFS)
#define BIT_CLEAR_BCNIFS(x)				((x) & (~BITS_BCNIFS))
#define BIT_GET_BCNIFS(x)				(((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS)
#define BIT_SET_BCNIFS(x, v)				(BIT_CLEAR_BCNIFS(x) | BIT_BCNIFS(v))

/* 2 REG_PIFS				(Offset 0x0512) */

#define BIT_SHIFT_PIFS					0
#define BIT_MASK_PIFS					0xff
#define BIT_PIFS(x)					(((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS)
#define BITS_PIFS					(BIT_MASK_PIFS << BIT_SHIFT_PIFS)
#define BIT_CLEAR_PIFS(x)				((x) & (~BITS_PIFS))
#define BIT_GET_PIFS(x)				(((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS)
#define BIT_SET_PIFS(x, v)				(BIT_CLEAR_PIFS(x) | BIT_PIFS(v))

/* 2 REG_RDG_PIFS				(Offset 0x0513) */

#define BIT_SHIFT_RDG_PIFS				0
#define BIT_MASK_RDG_PIFS				0xff
#define BIT_RDG_PIFS(x)				(((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS)
#define BITS_RDG_PIFS					(BIT_MASK_RDG_PIFS << BIT_SHIFT_RDG_PIFS)
#define BIT_CLEAR_RDG_PIFS(x)				((x) & (~BITS_RDG_PIFS))
#define BIT_GET_RDG_PIFS(x)				(((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS)
#define BIT_SET_RDG_PIFS(x, v)				(BIT_CLEAR_RDG_PIFS(x) | BIT_RDG_PIFS(v))

/* 2 REG_SIFS				(Offset 0x0514) */

#define BIT_SHIFT_SIFS_OFDM_TRX			24
#define BIT_MASK_SIFS_OFDM_TRX				0xff
#define BIT_SIFS_OFDM_TRX(x)				(((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX)
#define BITS_SIFS_OFDM_TRX				(BIT_MASK_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)
#define BIT_CLEAR_SIFS_OFDM_TRX(x)			((x) & (~BITS_SIFS_OFDM_TRX))
#define BIT_GET_SIFS_OFDM_TRX(x)			(((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX)
#define BIT_SET_SIFS_OFDM_TRX(x, v)			(BIT_CLEAR_SIFS_OFDM_TRX(x) | BIT_SIFS_OFDM_TRX(v))

#define BIT_SHIFT_SIFS_CCK_TRX				16
#define BIT_MASK_SIFS_CCK_TRX				0xff
#define BIT_SIFS_CCK_TRX(x)				(((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX)
#define BITS_SIFS_CCK_TRX				(BIT_MASK_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX)
#define BIT_CLEAR_SIFS_CCK_TRX(x)			((x) & (~BITS_SIFS_CCK_TRX))
#define BIT_GET_SIFS_CCK_TRX(x)			(((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX)
#define BIT_SET_SIFS_CCK_TRX(x, v)			(BIT_CLEAR_SIFS_CCK_TRX(x) | BIT_SIFS_CCK_TRX(v))

#define BIT_SHIFT_SIFS_OFDM_CTX			8
#define BIT_MASK_SIFS_OFDM_CTX				0xff
#define BIT_SIFS_OFDM_CTX(x)				(((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX)
#define BITS_SIFS_OFDM_CTX				(BIT_MASK_SIFS_OFDM_CTX << BIT_SHIFT_SIFS_OFDM_CTX)
#define BIT_CLEAR_SIFS_OFDM_CTX(x)			((x) & (~BITS_SIFS_OFDM_CTX))
#define BIT_GET_SIFS_OFDM_CTX(x)			(((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX)
#define BIT_SET_SIFS_OFDM_CTX(x, v)			(BIT_CLEAR_SIFS_OFDM_CTX(x) | BIT_SIFS_OFDM_CTX(v))

#define BIT_SHIFT_SIFS_CCK_CTX				0
#define BIT_MASK_SIFS_CCK_CTX				0xff
#define BIT_SIFS_CCK_CTX(x)				(((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX)
#define BITS_SIFS_CCK_CTX				(BIT_MASK_SIFS_CCK_CTX << BIT_SHIFT_SIFS_CCK_CTX)
#define BIT_CLEAR_SIFS_CCK_CTX(x)			((x) & (~BITS_SIFS_CCK_CTX))
#define BIT_GET_SIFS_CCK_CTX(x)			(((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX)
#define BIT_SET_SIFS_CCK_CTX(x, v)			(BIT_CLEAR_SIFS_CCK_CTX(x) | BIT_SIFS_CCK_CTX(v))

/* 2 REG_TSFTR_SYN_OFFSET			(Offset 0x0518) */

#define BIT_SHIFT_TSFTR_SNC_OFFSET			0
#define BIT_MASK_TSFTR_SNC_OFFSET			0xffff
#define BIT_TSFTR_SNC_OFFSET(x)			(((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET)
#define BITS_TSFTR_SNC_OFFSET				(BIT_MASK_TSFTR_SNC_OFFSET << BIT_SHIFT_TSFTR_SNC_OFFSET)
#define BIT_CLEAR_TSFTR_SNC_OFFSET(x)			((x) & (~BITS_TSFTR_SNC_OFFSET))
#define BIT_GET_TSFTR_SNC_OFFSET(x)			(((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET)
#define BIT_SET_TSFTR_SNC_OFFSET(x, v)			(BIT_CLEAR_TSFTR_SNC_OFFSET(x) | BIT_TSFTR_SNC_OFFSET(v))

/* 2 REG_AGGR_BREAK_TIME			(Offset 0x051A) */

#define BIT_SHIFT_AGGR_BK_TIME				0
#define BIT_MASK_AGGR_BK_TIME				0xff
#define BIT_AGGR_BK_TIME(x)				(((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME)
#define BITS_AGGR_BK_TIME				(BIT_MASK_AGGR_BK_TIME << BIT_SHIFT_AGGR_BK_TIME)
#define BIT_CLEAR_AGGR_BK_TIME(x)			((x) & (~BITS_AGGR_BK_TIME))
#define BIT_GET_AGGR_BK_TIME(x)			(((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME)
#define BIT_SET_AGGR_BK_TIME(x, v)			(BIT_CLEAR_AGGR_BK_TIME(x) | BIT_AGGR_BK_TIME(v))

/* 2 REG_SLOT				(Offset 0x051B) */

#define BIT_SHIFT_SLOT					0
#define BIT_MASK_SLOT					0xff
#define BIT_SLOT(x)					(((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT)
#define BITS_SLOT					(BIT_MASK_SLOT << BIT_SHIFT_SLOT)
#define BIT_CLEAR_SLOT(x)				((x) & (~BITS_SLOT))
#define BIT_GET_SLOT(x)				(((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT)
#define BIT_SET_SLOT(x, v)				(BIT_CLEAR_SLOT(x) | BIT_SLOT(v))

/* 2 REG_NOA_ON_ERLY_TIME			(Offset 0x051C) */

#define BIT_SHIFT__NOA_ON_ERLY_TIME			0
#define BIT_MASK__NOA_ON_ERLY_TIME			0xff
#define BIT__NOA_ON_ERLY_TIME(x)			(((x) & BIT_MASK__NOA_ON_ERLY_TIME) << BIT_SHIFT__NOA_ON_ERLY_TIME)
#define BITS__NOA_ON_ERLY_TIME				(BIT_MASK__NOA_ON_ERLY_TIME << BIT_SHIFT__NOA_ON_ERLY_TIME)
#define BIT_CLEAR__NOA_ON_ERLY_TIME(x)			((x) & (~BITS__NOA_ON_ERLY_TIME))
#define BIT_GET__NOA_ON_ERLY_TIME(x)			(((x) >> BIT_SHIFT__NOA_ON_ERLY_TIME) & BIT_MASK__NOA_ON_ERLY_TIME)
#define BIT_SET__NOA_ON_ERLY_TIME(x, v)		(BIT_CLEAR__NOA_ON_ERLY_TIME(x) | BIT__NOA_ON_ERLY_TIME(v))

/* 2 REG_NOA_OFF_ERLY_TIME			(Offset 0x051D) */

#define BIT_SHIFT__NOA_OFF_ERLY_TIME			0
#define BIT_MASK__NOA_OFF_ERLY_TIME			0xff
#define BIT__NOA_OFF_ERLY_TIME(x)			(((x) & BIT_MASK__NOA_OFF_ERLY_TIME) << BIT_SHIFT__NOA_OFF_ERLY_TIME)
#define BITS__NOA_OFF_ERLY_TIME			(BIT_MASK__NOA_OFF_ERLY_TIME << BIT_SHIFT__NOA_OFF_ERLY_TIME)
#define BIT_CLEAR__NOA_OFF_ERLY_TIME(x)		((x) & (~BITS__NOA_OFF_ERLY_TIME))
#define BIT_GET__NOA_OFF_ERLY_TIME(x)			(((x) >> BIT_SHIFT__NOA_OFF_ERLY_TIME) & BIT_MASK__NOA_OFF_ERLY_TIME)
#define BIT_SET__NOA_OFF_ERLY_TIME(x, v)		(BIT_CLEAR__NOA_OFF_ERLY_TIME(x) | BIT__NOA_OFF_ERLY_TIME(v))

/* 2 REG_TX_PTCL_CTRL			(Offset 0x0520) */

#define BIT_DIS_EDCCA					BIT(15)
#define BIT_DIS_CCA					BIT(14)
#define BIT_LSIG_TXOP_TXCMD_NAV			BIT(13)
#define BIT_SIFS_BK_EN					BIT(12)

#define BIT_SHIFT_TXQ_NAV_MSK				8
#define BIT_MASK_TXQ_NAV_MSK				0xf
#define BIT_TXQ_NAV_MSK(x)				(((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK)
#define BITS_TXQ_NAV_MSK				(BIT_MASK_TXQ_NAV_MSK << BIT_SHIFT_TXQ_NAV_MSK)
#define BIT_CLEAR_TXQ_NAV_MSK(x)			((x) & (~BITS_TXQ_NAV_MSK))
#define BIT_GET_TXQ_NAV_MSK(x)				(((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK)
#define BIT_SET_TXQ_NAV_MSK(x, v)			(BIT_CLEAR_TXQ_NAV_MSK(x) | BIT_TXQ_NAV_MSK(v))

#define BIT_DIS_CW					BIT(7)
#define BIT_NAV_END_TXOP				BIT(6)
#define BIT_RDG_END_TXOP				BIT(5)
#define BIT_AC_INBCN_HOLD				BIT(4)
#define BIT_MGTQ_TXOP_EN				BIT(3)
#define BIT_MGTQ_RTSMF_EN				BIT(2)
#define BIT_HIQ_RTSMF_EN				BIT(1)
#define BIT_BCN_RTSMF_EN				BIT(0)

/* 2 REG_TXPAUSE				(Offset 0x0522) */

#define BIT_STOP_BCN_HI_MGT				BIT(7)
#define BIT_MAC_STOPBCNQ				BIT(6)
#define BIT_MAC_STOPHIQ				BIT(5)
#define BIT_MAC_STOPMGQ				BIT(4)
#define BIT_MAC_STOPBK					BIT(3)
#define BIT_MAC_STOPBE					BIT(2)
#define BIT_MAC_STOPVI					BIT(1)
#define BIT_MAC_STOPVO					BIT(0)

/* 2 REG_DIS_TXREQ_CLR			(Offset 0x0523) */

#define BIT_DIS_BT_CCA					BIT(7)
#define BIT_DIS_TXREQ_CLR_CPUMGQ			BIT(6)
#define BIT_DIS_TXREQ_CLR_HI				BIT(5)
#define BIT_DIS_TXREQ_CLR_MGQ				BIT(4)
#define BIT_DIS_TXREQ_CLR_VO				BIT(3)
#define BIT_DIS_TXREQ_CLR_VI				BIT(2)
#define BIT_DIS_TXREQ_CLR_BE				BIT(1)
#define BIT_DIS_TXREQ_CLR_BK				BIT(0)

/* 2 REG_RD_CTRL				(Offset 0x0524) */

#define BIT_EN_CLR_TXREQ_INCCA				BIT(15)
#define BIT_DIS_TX_OVER_BCNQ				BIT(14)
#define BIT_EN_BCNERR_INCCCA				BIT(13)
#define BIT_EN_BCNERR_INEDCCA				BIT(12)
#define BIT_EDCCA_MSK_CNTDOWN_EN			BIT(11)
#define BIT_DIS_TXOP_CFE				BIT(10)
#define BIT_DIS_LSIG_CFE				BIT(9)
#define BIT_DIS_STBC_CFE				BIT(8)
#define BIT_BKQ_RD_INIT_EN				BIT(7)
#define BIT_BEQ_RD_INIT_EN				BIT(6)
#define BIT_VIQ_RD_INIT_EN				BIT(5)
#define BIT_VOQ_RD_INIT_EN				BIT(4)
#define BIT_BKQ_RD_RESP_EN				BIT(3)
#define BIT_BEQ_RD_RESP_EN				BIT(2)
#define BIT_VIQ_RD_RESP_EN				BIT(1)
#define BIT_VOQ_RD_RESP_EN				BIT(0)

/* 2 REG_P2PPS_CTRL				(Offset 0x0527) */

#define BIT_P2P_CTW_ALLSTASLEEP			BIT(7)
#define BIT_P2P_OFF_DISTX_EN				BIT(6)
#define BIT_PWR_MGT_EN					BIT(5)
#define BIT_P2P_NOA1_EN				BIT(2)
#define BIT_P2P_NOA0_EN				BIT(1)

/* 2 REG_PKT_LIFETIME_CTRL			(Offset 0x0528) */

#define BIT_EN_TBTT_AREA_FOR_BB			BIT(23)
#define BIT_EN_BKF_CLR_TXREQ				BIT(22)
#define BIT_EN_TSFBIT32_RST_P2P			BIT(21)
#define BIT_EN_BCN_TX_BTCCA				BIT(20)
#define BIT_DIS_PKT_TX_ATIM				BIT(19)
#define BIT_DIS_BCN_DIS_CTN				BIT(18)
#define BIT_EN_NAVEND_RST_TXOP				BIT(17)
#define BIT_EN_FILTER_CCA				BIT(16)

#define BIT_SHIFT_CCA_FILTER_THRS			8
#define BIT_MASK_CCA_FILTER_THRS			0xff
#define BIT_CCA_FILTER_THRS(x)				(((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS)
#define BITS_CCA_FILTER_THRS				(BIT_MASK_CCA_FILTER_THRS << BIT_SHIFT_CCA_FILTER_THRS)
#define BIT_CLEAR_CCA_FILTER_THRS(x)			((x) & (~BITS_CCA_FILTER_THRS))
#define BIT_GET_CCA_FILTER_THRS(x)			(((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS)
#define BIT_SET_CCA_FILTER_THRS(x, v)			(BIT_CLEAR_CCA_FILTER_THRS(x) | BIT_CCA_FILTER_THRS(v))

#define BIT_SHIFT_EDCCA_THRS				0
#define BIT_MASK_EDCCA_THRS				0xff
#define BIT_EDCCA_THRS(x)				(((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS)
#define BITS_EDCCA_THRS				(BIT_MASK_EDCCA_THRS << BIT_SHIFT_EDCCA_THRS)
#define BIT_CLEAR_EDCCA_THRS(x)			((x) & (~BITS_EDCCA_THRS))
#define BIT_GET_EDCCA_THRS(x)				(((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS)
#define BIT_SET_EDCCA_THRS(x, v)			(BIT_CLEAR_EDCCA_THRS(x) | BIT_EDCCA_THRS(v))

/* 2 REG_P2PPS_SPEC_STATE			(Offset 0x052B) */

#define BIT_SPEC_POWER_STATE				BIT(7)
#define BIT_SPEC_CTWINDOW_ON				BIT(6)
#define BIT_SPEC_BEACON_AREA_ON			BIT(5)
#define BIT_SPEC_CTWIN_EARLY_DISTX			BIT(4)
#define BIT_SPEC_NOA1_OFF_PERIOD			BIT(3)
#define BIT_SPEC_FORCE_DOZE1				BIT(2)
#define BIT_SPEC_NOA0_OFF_PERIOD			BIT(1)
#define BIT_SPEC_FORCE_DOZE0				BIT(0)

/* 2 REG_TBTT_AREA_BLK_4AC			(Offset 0x052C) */

#define BIT_EN_TBTT_AREA_BLK_4AC			BIT(6)

/* 2 REG_P2PON_DIS_TXTIME			(Offset 0x0531) */

#define BIT_SHIFT_P2PON_DIS_TXTIME			0
#define BIT_MASK_P2PON_DIS_TXTIME			0xff
#define BIT_P2PON_DIS_TXTIME(x)			(((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME)
#define BITS_P2PON_DIS_TXTIME				(BIT_MASK_P2PON_DIS_TXTIME << BIT_SHIFT_P2PON_DIS_TXTIME)
#define BIT_CLEAR_P2PON_DIS_TXTIME(x)			((x) & (~BITS_P2PON_DIS_TXTIME))
#define BIT_GET_P2PON_DIS_TXTIME(x)			(((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME)
#define BIT_SET_P2PON_DIS_TXTIME(x, v)			(BIT_CLEAR_P2PON_DIS_TXTIME(x) | BIT_P2PON_DIS_TXTIME(v))

/* 2 REG_EDCA_REF_CTRL			(Offset 0x0534) */

#define BIT_ENABLE_GEN_RANDON_SLOT_TX			BIT(20)
#define BIT_ENABLE_EDCA_REF_FUNCTION			BIT(19)
#define BIT_ENABLE_RANDOM_SHIFT_TX			BIT(18)

/* 2 REG_QUEUE_INCOL_THR			(Offset 0x0538) */

#define BIT_SHIFT_BK_QUEUE_THR				24
#define BIT_MASK_BK_QUEUE_THR				0xff
#define BIT_BK_QUEUE_THR(x)				(((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR)
#define BITS_BK_QUEUE_THR				(BIT_MASK_BK_QUEUE_THR << BIT_SHIFT_BK_QUEUE_THR)
#define BIT_CLEAR_BK_QUEUE_THR(x)			((x) & (~BITS_BK_QUEUE_THR))
#define BIT_GET_BK_QUEUE_THR(x)			(((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR)
#define BIT_SET_BK_QUEUE_THR(x, v)			(BIT_CLEAR_BK_QUEUE_THR(x) | BIT_BK_QUEUE_THR(v))

#define BIT_SHIFT_BE_QUEUE_THR				16
#define BIT_MASK_BE_QUEUE_THR				0xff
#define BIT_BE_QUEUE_THR(x)				(((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR)
#define BITS_BE_QUEUE_THR				(BIT_MASK_BE_QUEUE_THR << BIT_SHIFT_BE_QUEUE_THR)
#define BIT_CLEAR_BE_QUEUE_THR(x)			((x) & (~BITS_BE_QUEUE_THR))
#define BIT_GET_BE_QUEUE_THR(x)			(((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR)
#define BIT_SET_BE_QUEUE_THR(x, v)			(BIT_CLEAR_BE_QUEUE_THR(x) | BIT_BE_QUEUE_THR(v))

#define BIT_SHIFT_VI_QUEUE_THR				8
#define BIT_MASK_VI_QUEUE_THR				0xff
#define BIT_VI_QUEUE_THR(x)				(((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR)
#define BITS_VI_QUEUE_THR				(BIT_MASK_VI_QUEUE_THR << BIT_SHIFT_VI_QUEUE_THR)
#define BIT_CLEAR_VI_QUEUE_THR(x)			((x) & (~BITS_VI_QUEUE_THR))
#define BIT_GET_VI_QUEUE_THR(x)			(((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR)
#define BIT_SET_VI_QUEUE_THR(x, v)			(BIT_CLEAR_VI_QUEUE_THR(x) | BIT_VI_QUEUE_THR(v))

#define BIT_SHIFT_VO_QUEUE_THR				0
#define BIT_MASK_VO_QUEUE_THR				0xff
#define BIT_VO_QUEUE_THR(x)				(((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR)
#define BITS_VO_QUEUE_THR				(BIT_MASK_VO_QUEUE_THR << BIT_SHIFT_VO_QUEUE_THR)
#define BIT_CLEAR_VO_QUEUE_THR(x)			((x) & (~BITS_VO_QUEUE_THR))
#define BIT_GET_VO_QUEUE_THR(x)			(((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR)
#define BIT_SET_VO_QUEUE_THR(x, v)			(BIT_CLEAR_VO_QUEUE_THR(x) | BIT_VO_QUEUE_THR(v))

/* 2 REG_QUEUE_INCOL_EN			(Offset 0x053C) */

#define BIT_QUEUE_INCOL_EN				BIT(16)

#define BIT_SHIFT_BK_TRIGGER_NUM_V1			12
#define BIT_MASK_BK_TRIGGER_NUM_V1			0xf
#define BIT_BK_TRIGGER_NUM_V1(x)			(((x) & BIT_MASK_BK_TRIGGER_NUM_V1) << BIT_SHIFT_BK_TRIGGER_NUM_V1)
#define BITS_BK_TRIGGER_NUM_V1				(BIT_MASK_BK_TRIGGER_NUM_V1 << BIT_SHIFT_BK_TRIGGER_NUM_V1)
#define BIT_CLEAR_BK_TRIGGER_NUM_V1(x)			((x) & (~BITS_BK_TRIGGER_NUM_V1))
#define BIT_GET_BK_TRIGGER_NUM_V1(x)			(((x) >> BIT_SHIFT_BK_TRIGGER_NUM_V1) & BIT_MASK_BK_TRIGGER_NUM_V1)
#define BIT_SET_BK_TRIGGER_NUM_V1(x, v)		(BIT_CLEAR_BK_TRIGGER_NUM_V1(x) | BIT_BK_TRIGGER_NUM_V1(v))

#define BIT_SHIFT_BE_TRIGGER_NUM_V1			8
#define BIT_MASK_BE_TRIGGER_NUM_V1			0xf
#define BIT_BE_TRIGGER_NUM_V1(x)			(((x) & BIT_MASK_BE_TRIGGER_NUM_V1) << BIT_SHIFT_BE_TRIGGER_NUM_V1)
#define BITS_BE_TRIGGER_NUM_V1				(BIT_MASK_BE_TRIGGER_NUM_V1 << BIT_SHIFT_BE_TRIGGER_NUM_V1)
#define BIT_CLEAR_BE_TRIGGER_NUM_V1(x)			((x) & (~BITS_BE_TRIGGER_NUM_V1))
#define BIT_GET_BE_TRIGGER_NUM_V1(x)			(((x) >> BIT_SHIFT_BE_TRIGGER_NUM_V1) & BIT_MASK_BE_TRIGGER_NUM_V1)
#define BIT_SET_BE_TRIGGER_NUM_V1(x, v)		(BIT_CLEAR_BE_TRIGGER_NUM_V1(x) | BIT_BE_TRIGGER_NUM_V1(v))

#define BIT_SHIFT_VI_TRIGGER_NUM			4
#define BIT_MASK_VI_TRIGGER_NUM			0xf
#define BIT_VI_TRIGGER_NUM(x)				(((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM)
#define BITS_VI_TRIGGER_NUM				(BIT_MASK_VI_TRIGGER_NUM << BIT_SHIFT_VI_TRIGGER_NUM)
#define BIT_CLEAR_VI_TRIGGER_NUM(x)			((x) & (~BITS_VI_TRIGGER_NUM))
#define BIT_GET_VI_TRIGGER_NUM(x)			(((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM)
#define BIT_SET_VI_TRIGGER_NUM(x, v)			(BIT_CLEAR_VI_TRIGGER_NUM(x) | BIT_VI_TRIGGER_NUM(v))

#define BIT_SHIFT_VO_TRIGGER_NUM			0
#define BIT_MASK_VO_TRIGGER_NUM			0xf
#define BIT_VO_TRIGGER_NUM(x)				(((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM)
#define BITS_VO_TRIGGER_NUM				(BIT_MASK_VO_TRIGGER_NUM << BIT_SHIFT_VO_TRIGGER_NUM)
#define BIT_CLEAR_VO_TRIGGER_NUM(x)			((x) & (~BITS_VO_TRIGGER_NUM))
#define BIT_GET_VO_TRIGGER_NUM(x)			(((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM)
#define BIT_SET_VO_TRIGGER_NUM(x, v)			(BIT_CLEAR_VO_TRIGGER_NUM(x) | BIT_VO_TRIGGER_NUM(v))

/* 2 REG_TBTT_PROHIBIT			(Offset 0x0540) */

#define BIT_SHIFT_TBTT_HOLD_TIME_AP			8
#define BIT_MASK_TBTT_HOLD_TIME_AP			0xfff
#define BIT_TBTT_HOLD_TIME_AP(x)			(((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP)
#define BITS_TBTT_HOLD_TIME_AP				(BIT_MASK_TBTT_HOLD_TIME_AP << BIT_SHIFT_TBTT_HOLD_TIME_AP)
#define BIT_CLEAR_TBTT_HOLD_TIME_AP(x)			((x) & (~BITS_TBTT_HOLD_TIME_AP))
#define BIT_GET_TBTT_HOLD_TIME_AP(x)			(((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP)
#define BIT_SET_TBTT_HOLD_TIME_AP(x, v)		(BIT_CLEAR_TBTT_HOLD_TIME_AP(x) | BIT_TBTT_HOLD_TIME_AP(v))

#define BIT_SHIFT_TBTT_PROHIBIT_SETUP			0
#define BIT_MASK_TBTT_PROHIBIT_SETUP			0xf
#define BIT_TBTT_PROHIBIT_SETUP(x)			(((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP)
#define BITS_TBTT_PROHIBIT_SETUP			(BIT_MASK_TBTT_PROHIBIT_SETUP << BIT_SHIFT_TBTT_PROHIBIT_SETUP)
#define BIT_CLEAR_TBTT_PROHIBIT_SETUP(x)		((x) & (~BITS_TBTT_PROHIBIT_SETUP))
#define BIT_GET_TBTT_PROHIBIT_SETUP(x)			(((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP)
#define BIT_SET_TBTT_PROHIBIT_SETUP(x, v)		(BIT_CLEAR_TBTT_PROHIBIT_SETUP(x) | BIT_TBTT_PROHIBIT_SETUP(v))

/* 2 REG_P2PPS_STATE				(Offset 0x0543) */

#define BIT_POWER_STATE				BIT(7)
#define BIT_CTWINDOW_ON				BIT(6)
#define BIT_BEACON_AREA_ON				BIT(5)
#define BIT_CTWIN_EARLY_DISTX				BIT(4)
#define BIT_NOA1_OFF_PERIOD				BIT(3)
#define BIT_FORCE_DOZE1				BIT(2)
#define BIT_NOA0_OFF_PERIOD				BIT(1)
#define BIT_FORCE_DOZE0				BIT(0)

/* 2 REG_RD_NAV_NXT				(Offset 0x0544) */

#define BIT_SHIFT_RD_NAV_PROT_NXT			0
#define BIT_MASK_RD_NAV_PROT_NXT			0xffff
#define BIT_RD_NAV_PROT_NXT(x)				(((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT)
#define BITS_RD_NAV_PROT_NXT				(BIT_MASK_RD_NAV_PROT_NXT << BIT_SHIFT_RD_NAV_PROT_NXT)
#define BIT_CLEAR_RD_NAV_PROT_NXT(x)			((x) & (~BITS_RD_NAV_PROT_NXT))
#define BIT_GET_RD_NAV_PROT_NXT(x)			(((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT)
#define BIT_SET_RD_NAV_PROT_NXT(x, v)			(BIT_CLEAR_RD_NAV_PROT_NXT(x) | BIT_RD_NAV_PROT_NXT(v))

/* 2 REG_NAV_PROT_LEN			(Offset 0x0546) */

#define BIT_SHIFT_NAV_PROT_LEN				0
#define BIT_MASK_NAV_PROT_LEN				0xffff
#define BIT_NAV_PROT_LEN(x)				(((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN)
#define BITS_NAV_PROT_LEN				(BIT_MASK_NAV_PROT_LEN << BIT_SHIFT_NAV_PROT_LEN)
#define BIT_CLEAR_NAV_PROT_LEN(x)			((x) & (~BITS_NAV_PROT_LEN))
#define BIT_GET_NAV_PROT_LEN(x)			(((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN)
#define BIT_SET_NAV_PROT_LEN(x, v)			(BIT_CLEAR_NAV_PROT_LEN(x) | BIT_NAV_PROT_LEN(v))

/* 2 REG_FTM_CTRL				(Offset 0x0548) */

#define BIT_SHIFT_FTM_TSF_R2T_PORT			22
#define BIT_MASK_FTM_TSF_R2T_PORT			0x7
#define BIT_FTM_TSF_R2T_PORT(x)			(((x) & BIT_MASK_FTM_TSF_R2T_PORT) << BIT_SHIFT_FTM_TSF_R2T_PORT)
#define BITS_FTM_TSF_R2T_PORT				(BIT_MASK_FTM_TSF_R2T_PORT << BIT_SHIFT_FTM_TSF_R2T_PORT)
#define BIT_CLEAR_FTM_TSF_R2T_PORT(x)			((x) & (~BITS_FTM_TSF_R2T_PORT))
#define BIT_GET_FTM_TSF_R2T_PORT(x)			(((x) >> BIT_SHIFT_FTM_TSF_R2T_PORT) & BIT_MASK_FTM_TSF_R2T_PORT)
#define BIT_SET_FTM_TSF_R2T_PORT(x, v)			(BIT_CLEAR_FTM_TSF_R2T_PORT(x) | BIT_FTM_TSF_R2T_PORT(v))

#define BIT_SHIFT_FTM_TSF_T2R_PORT			19
#define BIT_MASK_FTM_TSF_T2R_PORT			0x7
#define BIT_FTM_TSF_T2R_PORT(x)			(((x) & BIT_MASK_FTM_TSF_T2R_PORT) << BIT_SHIFT_FTM_TSF_T2R_PORT)
#define BITS_FTM_TSF_T2R_PORT				(BIT_MASK_FTM_TSF_T2R_PORT << BIT_SHIFT_FTM_TSF_T2R_PORT)
#define BIT_CLEAR_FTM_TSF_T2R_PORT(x)			((x) & (~BITS_FTM_TSF_T2R_PORT))
#define BIT_GET_FTM_TSF_T2R_PORT(x)			(((x) >> BIT_SHIFT_FTM_TSF_T2R_PORT) & BIT_MASK_FTM_TSF_T2R_PORT)
#define BIT_SET_FTM_TSF_T2R_PORT(x, v)			(BIT_CLEAR_FTM_TSF_T2R_PORT(x) | BIT_FTM_TSF_T2R_PORT(v))

#define BIT_SHIFT_FTM_PTT_PORT				16
#define BIT_MASK_FTM_PTT_PORT				0x7
#define BIT_FTM_PTT_PORT(x)				(((x) & BIT_MASK_FTM_PTT_PORT) << BIT_SHIFT_FTM_PTT_PORT)
#define BITS_FTM_PTT_PORT				(BIT_MASK_FTM_PTT_PORT << BIT_SHIFT_FTM_PTT_PORT)
#define BIT_CLEAR_FTM_PTT_PORT(x)			((x) & (~BITS_FTM_PTT_PORT))
#define BIT_GET_FTM_PTT_PORT(x)			(((x) >> BIT_SHIFT_FTM_PTT_PORT) & BIT_MASK_FTM_PTT_PORT)
#define BIT_SET_FTM_PTT_PORT(x, v)			(BIT_CLEAR_FTM_PTT_PORT(x) | BIT_FTM_PTT_PORT(v))

#define BIT_SHIFT_FTM_PTT				0
#define BIT_MASK_FTM_PTT				0xffff
#define BIT_FTM_PTT(x)					(((x) & BIT_MASK_FTM_PTT) << BIT_SHIFT_FTM_PTT)
#define BITS_FTM_PTT					(BIT_MASK_FTM_PTT << BIT_SHIFT_FTM_PTT)
#define BIT_CLEAR_FTM_PTT(x)				((x) & (~BITS_FTM_PTT))
#define BIT_GET_FTM_PTT(x)				(((x) >> BIT_SHIFT_FTM_PTT) & BIT_MASK_FTM_PTT)
#define BIT_SET_FTM_PTT(x, v)				(BIT_CLEAR_FTM_PTT(x) | BIT_FTM_PTT(v))

/* 2 REG_FTM_TSF_CNT				(Offset 0x054C) */

#define BIT_SHIFT_FTM_TSF_R2T				16
#define BIT_MASK_FTM_TSF_R2T				0xffff
#define BIT_FTM_TSF_R2T(x)				(((x) & BIT_MASK_FTM_TSF_R2T) << BIT_SHIFT_FTM_TSF_R2T)
#define BITS_FTM_TSF_R2T				(BIT_MASK_FTM_TSF_R2T << BIT_SHIFT_FTM_TSF_R2T)
#define BIT_CLEAR_FTM_TSF_R2T(x)			((x) & (~BITS_FTM_TSF_R2T))
#define BIT_GET_FTM_TSF_R2T(x)				(((x) >> BIT_SHIFT_FTM_TSF_R2T) & BIT_MASK_FTM_TSF_R2T)
#define BIT_SET_FTM_TSF_R2T(x, v)			(BIT_CLEAR_FTM_TSF_R2T(x) | BIT_FTM_TSF_R2T(v))

#define BIT_SHIFT_FTM_TSF_T2R				0
#define BIT_MASK_FTM_TSF_T2R				0xffff
#define BIT_FTM_TSF_T2R(x)				(((x) & BIT_MASK_FTM_TSF_T2R) << BIT_SHIFT_FTM_TSF_T2R)
#define BITS_FTM_TSF_T2R				(BIT_MASK_FTM_TSF_T2R << BIT_SHIFT_FTM_TSF_T2R)
#define BIT_CLEAR_FTM_TSF_T2R(x)			((x) & (~BITS_FTM_TSF_T2R))
#define BIT_GET_FTM_TSF_T2R(x)				(((x) >> BIT_SHIFT_FTM_TSF_T2R) & BIT_MASK_FTM_TSF_T2R)
#define BIT_SET_FTM_TSF_T2R(x, v)			(BIT_CLEAR_FTM_TSF_T2R(x) | BIT_FTM_TSF_T2R(v))

/* 2 REG_BCN_CTRL				(Offset 0x0550) */

#define BIT_DIS_RX_BSSID_FIT				BIT(6)
#define BIT_P0_EN_TXBCN_RPT				BIT(5)
#define BIT_DIS_TSF_UDT				BIT(4)
#define BIT_EN_BCN_FUNCTION				BIT(3)
#define BIT_P0_EN_RXBCN_RPT				BIT(2)
#define BIT_EN_P2P_CTWINDOW				BIT(1)
#define BIT_EN_P2P_BCNQ_AREA				BIT(0)

/* 2 REG_BCN_CTRL_CLINT0			(Offset 0x0551) */

#define BIT_CLI0_DIS_RX_BSSID_FIT			BIT(6)
#define BIT_CLI0_DIS_TSF_UDT				BIT(4)
#define BIT_CLI0_EN_BCN_FUNCTION			BIT(3)
#define BIT_CLI0_EN_RXBCN_RPT				BIT(2)
#define BIT_CLI0_ENP2P_CTWINDOW			BIT(1)
#define BIT_CLI0_ENP2P_BCNQ_AREA			BIT(0)

/* 2 REG_MBID_NUM				(Offset 0x0552) */

#define BIT_SHIFT_MBID_BCN_NUM_V2			4
#define BIT_MASK_MBID_BCN_NUM_V2			0xf
#define BIT_MBID_BCN_NUM_V2(x)				(((x) & BIT_MASK_MBID_BCN_NUM_V2) << BIT_SHIFT_MBID_BCN_NUM_V2)
#define BITS_MBID_BCN_NUM_V2				(BIT_MASK_MBID_BCN_NUM_V2 << BIT_SHIFT_MBID_BCN_NUM_V2)
#define BIT_CLEAR_MBID_BCN_NUM_V2(x)			((x) & (~BITS_MBID_BCN_NUM_V2))
#define BIT_GET_MBID_BCN_NUM_V2(x)			(((x) >> BIT_SHIFT_MBID_BCN_NUM_V2) & BIT_MASK_MBID_BCN_NUM_V2)
#define BIT_SET_MBID_BCN_NUM_V2(x, v)			(BIT_CLEAR_MBID_BCN_NUM_V2(x) | BIT_MBID_BCN_NUM_V2(v))

#define BIT_EN_PRE_DL_BEACON				BIT(3)

/* 2 REG_DUAL_TSF_RST			(Offset 0x0553) */

#define BIT_FREECNT_RST				BIT(5)
#define BIT_TSFTR_CLI3_RST				BIT(4)
#define BIT_TSFTR_CLI2_RST				BIT(3)
#define BIT_TSFTR_CLI1_RST				BIT(2)
#define BIT_TSFTR_CLI0_RST				BIT(1)
#define BIT_TSFTR_RST					BIT(0)

/* 2 REG_MBSSID_BCN_SPACE			(Offset 0x0554) */

#define BIT_SHIFT_BCN_TIMER_SEL_FWRD			28
#define BIT_MASK_BCN_TIMER_SEL_FWRD			0x7
#define BIT_BCN_TIMER_SEL_FWRD(x)			(((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD)
#define BITS_BCN_TIMER_SEL_FWRD			(BIT_MASK_BCN_TIMER_SEL_FWRD << BIT_SHIFT_BCN_TIMER_SEL_FWRD)
#define BIT_CLEAR_BCN_TIMER_SEL_FWRD(x)		((x) & (~BITS_BCN_TIMER_SEL_FWRD))
#define BIT_GET_BCN_TIMER_SEL_FWRD(x)			(((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD)
#define BIT_SET_BCN_TIMER_SEL_FWRD(x, v)		(BIT_CLEAR_BCN_TIMER_SEL_FWRD(x) | BIT_BCN_TIMER_SEL_FWRD(v))

#define BIT_SHIFT_BCN_SPACE_CLINT0			16
#define BIT_MASK_BCN_SPACE_CLINT0			0xfff
#define BIT_BCN_SPACE_CLINT0(x)			(((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0)
#define BITS_BCN_SPACE_CLINT0				(BIT_MASK_BCN_SPACE_CLINT0 << BIT_SHIFT_BCN_SPACE_CLINT0)
#define BIT_CLEAR_BCN_SPACE_CLINT0(x)			((x) & (~BITS_BCN_SPACE_CLINT0))
#define BIT_GET_BCN_SPACE_CLINT0(x)			(((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0)
#define BIT_SET_BCN_SPACE_CLINT0(x, v)			(BIT_CLEAR_BCN_SPACE_CLINT0(x) | BIT_BCN_SPACE_CLINT0(v))

#define BIT_SHIFT_BCN_SPACE0				0
#define BIT_MASK_BCN_SPACE0				0xffff
#define BIT_BCN_SPACE0(x)				(((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0)
#define BITS_BCN_SPACE0				(BIT_MASK_BCN_SPACE0 << BIT_SHIFT_BCN_SPACE0)
#define BIT_CLEAR_BCN_SPACE0(x)			((x) & (~BITS_BCN_SPACE0))
#define BIT_GET_BCN_SPACE0(x)				(((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0)
#define BIT_SET_BCN_SPACE0(x, v)			(BIT_CLEAR_BCN_SPACE0(x) | BIT_BCN_SPACE0(v))

/* 2 REG_DRVERLYINT				(Offset 0x0558) */

#define BIT_SHIFT_DRVERLYITV				0
#define BIT_MASK_DRVERLYITV				0xff
#define BIT_DRVERLYITV(x)				(((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV)
#define BITS_DRVERLYITV				(BIT_MASK_DRVERLYITV << BIT_SHIFT_DRVERLYITV)
#define BIT_CLEAR_DRVERLYITV(x)			((x) & (~BITS_DRVERLYITV))
#define BIT_GET_DRVERLYITV(x)				(((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV)
#define BIT_SET_DRVERLYITV(x, v)			(BIT_CLEAR_DRVERLYITV(x) | BIT_DRVERLYITV(v))

/* 2 REG_BCNDMATIM				(Offset 0x0559) */

#define BIT_SHIFT_BCNDMATIM				0
#define BIT_MASK_BCNDMATIM				0xff
#define BIT_BCNDMATIM(x)				(((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM)
#define BITS_BCNDMATIM					(BIT_MASK_BCNDMATIM << BIT_SHIFT_BCNDMATIM)
#define BIT_CLEAR_BCNDMATIM(x)				((x) & (~BITS_BCNDMATIM))
#define BIT_GET_BCNDMATIM(x)				(((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM)
#define BIT_SET_BCNDMATIM(x, v)			(BIT_CLEAR_BCNDMATIM(x) | BIT_BCNDMATIM(v))

/* 2 REG_USTIME_TSF				(Offset 0x055C) */

#define BIT_SHIFT_USTIME_TSF_V1			0
#define BIT_MASK_USTIME_TSF_V1				0xff
#define BIT_USTIME_TSF_V1(x)				(((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1)
#define BITS_USTIME_TSF_V1				(BIT_MASK_USTIME_TSF_V1 << BIT_SHIFT_USTIME_TSF_V1)
#define BIT_CLEAR_USTIME_TSF_V1(x)			((x) & (~BITS_USTIME_TSF_V1))
#define BIT_GET_USTIME_TSF_V1(x)			(((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1)
#define BIT_SET_USTIME_TSF_V1(x, v)			(BIT_CLEAR_USTIME_TSF_V1(x) | BIT_USTIME_TSF_V1(v))

/* 2 REG_BCN_MAX_ERR				(Offset 0x055D) */

#define BIT_SHIFT_BCN_MAX_ERR				0
#define BIT_MASK_BCN_MAX_ERR				0xff
#define BIT_BCN_MAX_ERR(x)				(((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR)
#define BITS_BCN_MAX_ERR				(BIT_MASK_BCN_MAX_ERR << BIT_SHIFT_BCN_MAX_ERR)
#define BIT_CLEAR_BCN_MAX_ERR(x)			((x) & (~BITS_BCN_MAX_ERR))
#define BIT_GET_BCN_MAX_ERR(x)				(((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR)
#define BIT_SET_BCN_MAX_ERR(x, v)			(BIT_CLEAR_BCN_MAX_ERR(x) | BIT_BCN_MAX_ERR(v))

/* 2 REG_RXTSF_OFFSET_CCK			(Offset 0x055E) */

#define BIT_SHIFT_CCK_RXTSF_OFFSET			0
#define BIT_MASK_CCK_RXTSF_OFFSET			0xff
#define BIT_CCK_RXTSF_OFFSET(x)			(((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET)
#define BITS_CCK_RXTSF_OFFSET				(BIT_MASK_CCK_RXTSF_OFFSET << BIT_SHIFT_CCK_RXTSF_OFFSET)
#define BIT_CLEAR_CCK_RXTSF_OFFSET(x)			((x) & (~BITS_CCK_RXTSF_OFFSET))
#define BIT_GET_CCK_RXTSF_OFFSET(x)			(((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET)
#define BIT_SET_CCK_RXTSF_OFFSET(x, v)			(BIT_CLEAR_CCK_RXTSF_OFFSET(x) | BIT_CCK_RXTSF_OFFSET(v))

/* 2 REG_RXTSF_OFFSET_OFDM			(Offset 0x055F) */

#define BIT_SHIFT_OFDM_RXTSF_OFFSET			0
#define BIT_MASK_OFDM_RXTSF_OFFSET			0xff
#define BIT_OFDM_RXTSF_OFFSET(x)			(((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET)
#define BITS_OFDM_RXTSF_OFFSET				(BIT_MASK_OFDM_RXTSF_OFFSET << BIT_SHIFT_OFDM_RXTSF_OFFSET)
#define BIT_CLEAR_OFDM_RXTSF_OFFSET(x)			((x) & (~BITS_OFDM_RXTSF_OFFSET))
#define BIT_GET_OFDM_RXTSF_OFFSET(x)			(((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET)
#define BIT_SET_OFDM_RXTSF_OFFSET(x, v)		(BIT_CLEAR_OFDM_RXTSF_OFFSET(x) | BIT_OFDM_RXTSF_OFFSET(v))

/* 2 REG_TSFTR				(Offset 0x0560) */

#define BIT_SHIFT_TSF_TIMER_V1				0
#define BIT_MASK_TSF_TIMER_V1				0xffffffffL
#define BIT_TSF_TIMER_V1(x)				(((x) & BIT_MASK_TSF_TIMER_V1) << BIT_SHIFT_TSF_TIMER_V1)
#define BITS_TSF_TIMER_V1				(BIT_MASK_TSF_TIMER_V1 << BIT_SHIFT_TSF_TIMER_V1)
#define BIT_CLEAR_TSF_TIMER_V1(x)			((x) & (~BITS_TSF_TIMER_V1))
#define BIT_GET_TSF_TIMER_V1(x)			(((x) >> BIT_SHIFT_TSF_TIMER_V1) & BIT_MASK_TSF_TIMER_V1)
#define BIT_SET_TSF_TIMER_V1(x, v)			(BIT_CLEAR_TSF_TIMER_V1(x) | BIT_TSF_TIMER_V1(v))

/* 2 REG_TSFTR_1				(Offset 0x0564) */

#define BIT_SHIFT_TSF_TIMER_V2				0
#define BIT_MASK_TSF_TIMER_V2				0xffffffffL
#define BIT_TSF_TIMER_V2(x)				(((x) & BIT_MASK_TSF_TIMER_V2) << BIT_SHIFT_TSF_TIMER_V2)
#define BITS_TSF_TIMER_V2				(BIT_MASK_TSF_TIMER_V2 << BIT_SHIFT_TSF_TIMER_V2)
#define BIT_CLEAR_TSF_TIMER_V2(x)			((x) & (~BITS_TSF_TIMER_V2))
#define BIT_GET_TSF_TIMER_V2(x)			(((x) >> BIT_SHIFT_TSF_TIMER_V2) & BIT_MASK_TSF_TIMER_V2)
#define BIT_SET_TSF_TIMER_V2(x, v)			(BIT_CLEAR_TSF_TIMER_V2(x) | BIT_TSF_TIMER_V2(v))

/* 2 REG_FREERUN_CNT				(Offset 0x0568) */

#define BIT_SHIFT_FREERUN_CNT_V1			0
#define BIT_MASK_FREERUN_CNT_V1			0xffffffffL
#define BIT_FREERUN_CNT_V1(x)				(((x) & BIT_MASK_FREERUN_CNT_V1) << BIT_SHIFT_FREERUN_CNT_V1)
#define BITS_FREERUN_CNT_V1				(BIT_MASK_FREERUN_CNT_V1 << BIT_SHIFT_FREERUN_CNT_V1)
#define BIT_CLEAR_FREERUN_CNT_V1(x)			((x) & (~BITS_FREERUN_CNT_V1))
#define BIT_GET_FREERUN_CNT_V1(x)			(((x) >> BIT_SHIFT_FREERUN_CNT_V1) & BIT_MASK_FREERUN_CNT_V1)
#define BIT_SET_FREERUN_CNT_V1(x, v)			(BIT_CLEAR_FREERUN_CNT_V1(x) | BIT_FREERUN_CNT_V1(v))

/* 2 REG_FREERUN_CNT_1			(Offset 0x056C) */

#define BIT_SHIFT_FREERUN_CNT_V2			0
#define BIT_MASK_FREERUN_CNT_V2			0xffffffffL
#define BIT_FREERUN_CNT_V2(x)				(((x) & BIT_MASK_FREERUN_CNT_V2) << BIT_SHIFT_FREERUN_CNT_V2)
#define BITS_FREERUN_CNT_V2				(BIT_MASK_FREERUN_CNT_V2 << BIT_SHIFT_FREERUN_CNT_V2)
#define BIT_CLEAR_FREERUN_CNT_V2(x)			((x) & (~BITS_FREERUN_CNT_V2))
#define BIT_GET_FREERUN_CNT_V2(x)			(((x) >> BIT_SHIFT_FREERUN_CNT_V2) & BIT_MASK_FREERUN_CNT_V2)
#define BIT_SET_FREERUN_CNT_V2(x, v)			(BIT_CLEAR_FREERUN_CNT_V2(x) | BIT_FREERUN_CNT_V2(v))

/* 2 REG_TBTT_PROHIBIT_INFRA			(Offset 0x0571) */

#define BIT_SHIFT_TBTT_PROHIBIT_INFRA			0
#define BIT_MASK_TBTT_PROHIBIT_INFRA			0xff
#define BIT_TBTT_PROHIBIT_INFRA(x)			(((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA)
#define BITS_TBTT_PROHIBIT_INFRA			(BIT_MASK_TBTT_PROHIBIT_INFRA << BIT_SHIFT_TBTT_PROHIBIT_INFRA)
#define BIT_CLEAR_TBTT_PROHIBIT_INFRA(x)		((x) & (~BITS_TBTT_PROHIBIT_INFRA))
#define BIT_GET_TBTT_PROHIBIT_INFRA(x)			(((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA)
#define BIT_SET_TBTT_PROHIBIT_INFRA(x, v)		(BIT_CLEAR_TBTT_PROHIBIT_INFRA(x) | BIT_TBTT_PROHIBIT_INFRA(v))

/* 2 REG_CTWND				(Offset 0x0572) */

#define BIT_SHIFT_CTWND				0
#define BIT_MASK_CTWND					0xff
#define BIT_CTWND(x)					(((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND)
#define BITS_CTWND					(BIT_MASK_CTWND << BIT_SHIFT_CTWND)
#define BIT_CLEAR_CTWND(x)				((x) & (~BITS_CTWND))
#define BIT_GET_CTWND(x)				(((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND)
#define BIT_SET_CTWND(x, v)				(BIT_CLEAR_CTWND(x) | BIT_CTWND(v))

/* 2 REG_BCNIVLCUNT				(Offset 0x0573) */

#define BIT_SHIFT_BCNIVLCUNT				0
#define BIT_MASK_BCNIVLCUNT				0x7f
#define BIT_BCNIVLCUNT(x)				(((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT)
#define BITS_BCNIVLCUNT				(BIT_MASK_BCNIVLCUNT << BIT_SHIFT_BCNIVLCUNT)
#define BIT_CLEAR_BCNIVLCUNT(x)			((x) & (~BITS_BCNIVLCUNT))
#define BIT_GET_BCNIVLCUNT(x)				(((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT)
#define BIT_SET_BCNIVLCUNT(x, v)			(BIT_CLEAR_BCNIVLCUNT(x) | BIT_BCNIVLCUNT(v))

/* 2 REG_BCNDROPCTRL				(Offset 0x0574) */

#define BIT_BEACON_DROP_EN				BIT(7)

#define BIT_SHIFT_BEACON_DROP_IVL			0
#define BIT_MASK_BEACON_DROP_IVL			0x7f
#define BIT_BEACON_DROP_IVL(x)				(((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL)
#define BITS_BEACON_DROP_IVL				(BIT_MASK_BEACON_DROP_IVL << BIT_SHIFT_BEACON_DROP_IVL)
#define BIT_CLEAR_BEACON_DROP_IVL(x)			((x) & (~BITS_BEACON_DROP_IVL))
#define BIT_GET_BEACON_DROP_IVL(x)			(((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL)
#define BIT_SET_BEACON_DROP_IVL(x, v)			(BIT_CLEAR_BEACON_DROP_IVL(x) | BIT_BEACON_DROP_IVL(v))

/* 2 REG_HGQ_TIMEOUT_PERIOD			(Offset 0x0575) */

#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD			0
#define BIT_MASK_HGQ_TIMEOUT_PERIOD			0xff
#define BIT_HGQ_TIMEOUT_PERIOD(x)			(((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD)
#define BITS_HGQ_TIMEOUT_PERIOD			(BIT_MASK_HGQ_TIMEOUT_PERIOD << BIT_SHIFT_HGQ_TIMEOUT_PERIOD)
#define BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x)		((x) & (~BITS_HGQ_TIMEOUT_PERIOD))
#define BIT_GET_HGQ_TIMEOUT_PERIOD(x)			(((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD)
#define BIT_SET_HGQ_TIMEOUT_PERIOD(x, v)		(BIT_CLEAR_HGQ_TIMEOUT_PERIOD(x) | BIT_HGQ_TIMEOUT_PERIOD(v))

/* 2 REG_TXCMD_TIMEOUT_PERIOD		(Offset 0x0576) */

#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD			0
#define BIT_MASK_TXCMD_TIMEOUT_PERIOD			0xff
#define BIT_TXCMD_TIMEOUT_PERIOD(x)			(((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD)
#define BITS_TXCMD_TIMEOUT_PERIOD			(BIT_MASK_TXCMD_TIMEOUT_PERIOD << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD)
#define BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x)		((x) & (~BITS_TXCMD_TIMEOUT_PERIOD))
#define BIT_GET_TXCMD_TIMEOUT_PERIOD(x)		(((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) & BIT_MASK_TXCMD_TIMEOUT_PERIOD)
#define BIT_SET_TXCMD_TIMEOUT_PERIOD(x, v)		(BIT_CLEAR_TXCMD_TIMEOUT_PERIOD(x) | BIT_TXCMD_TIMEOUT_PERIOD(v))

/* 2 REG_MISC_CTRL				(Offset 0x0577) */

#define BIT_DIS_MARK_TSF_US				BIT(7)
#define BIT_EN_TSFAUTO_SYNC				BIT(6)
#define BIT_DIS_TRX_CAL_BCN				BIT(5)
#define BIT_DIS_TX_CAL_TBTT				BIT(4)
#define BIT_EN_FREECNT					BIT(3)
#define BIT_BCN_AGGRESSION				BIT(2)

#define BIT_SHIFT_DIS_SECONDARY_CCA			0
#define BIT_MASK_DIS_SECONDARY_CCA			0x3
#define BIT_DIS_SECONDARY_CCA(x)			(((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA)
#define BITS_DIS_SECONDARY_CCA				(BIT_MASK_DIS_SECONDARY_CCA << BIT_SHIFT_DIS_SECONDARY_CCA)
#define BIT_CLEAR_DIS_SECONDARY_CCA(x)			((x) & (~BITS_DIS_SECONDARY_CCA))
#define BIT_GET_DIS_SECONDARY_CCA(x)			(((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA)
#define BIT_SET_DIS_SECONDARY_CCA(x, v)		(BIT_CLEAR_DIS_SECONDARY_CCA(x) | BIT_DIS_SECONDARY_CCA(v))

/* 2 REG_BCN_CTRL_CLINT1			(Offset 0x0578) */

#define BIT_CLI1_DIS_RX_BSSID_FIT			BIT(6)
#define BIT_CLI1_DIS_TSF_UDT				BIT(4)
#define BIT_CLI1_EN_BCN_FUNCTION			BIT(3)
#define BIT_CLI1_EN_RXBCN_RPT				BIT(2)
#define BIT_CLI1_ENP2P_CTWINDOW			BIT(1)
#define BIT_CLI1_ENP2P_BCNQ_AREA			BIT(0)

/* 2 REG_BCN_CTRL_CLINT2			(Offset 0x0579) */

#define BIT_CLI2_DIS_RX_BSSID_FIT			BIT(6)
#define BIT_CLI2_DIS_TSF_UDT				BIT(4)
#define BIT_CLI2_EN_BCN_FUNCTION			BIT(3)
#define BIT_CLI2_EN_RXBCN_RPT				BIT(2)
#define BIT_CLI2_ENP2P_CTWINDOW			BIT(1)
#define BIT_CLI2_ENP2P_BCNQ_AREA			BIT(0)

/* 2 REG_BCN_CTRL_CLINT3			(Offset 0x057A) */

#define BIT_CLI3_DIS_RX_BSSID_FIT			BIT(6)
#define BIT_CLI3_DIS_TSF_UDT				BIT(4)
#define BIT_CLI3_EN_BCN_FUNCTION			BIT(3)
#define BIT_CLI3_EN_RXBCN_RPT				BIT(2)
#define BIT_CLI3_ENP2P_CTWINDOW			BIT(1)
#define BIT_CLI3_ENP2P_BCNQ_AREA			BIT(0)

/* 2 REG_EXTEND_CTRL				(Offset 0x057B) */

#define BIT_EN_TSFBIT32_RST_P2P2			BIT(5)
#define BIT_EN_TSFBIT32_RST_P2P1			BIT(4)

#define BIT_SHIFT_PORT_SEL				0
#define BIT_MASK_PORT_SEL				0x7
#define BIT_PORT_SEL(x)				(((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL)
#define BITS_PORT_SEL					(BIT_MASK_PORT_SEL << BIT_SHIFT_PORT_SEL)
#define BIT_CLEAR_PORT_SEL(x)				((x) & (~BITS_PORT_SEL))
#define BIT_GET_PORT_SEL(x)				(((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL)
#define BIT_SET_PORT_SEL(x, v)				(BIT_CLEAR_PORT_SEL(x) | BIT_PORT_SEL(v))

/* 2 REG_P2PPS1_SPEC_STATE			(Offset 0x057C) */

#define BIT_P2P1_SPEC_POWER_STATE			BIT(7)
#define BIT_P2P1_SPEC_CTWINDOW_ON			BIT(6)
#define BIT_P2P1_SPEC_BCN_AREA_ON			BIT(5)
#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX		BIT(4)
#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD			BIT(3)
#define BIT_P2P1_SPEC_FORCE_DOZE1			BIT(2)
#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD			BIT(1)
#define BIT_P2P1_SPEC_FORCE_DOZE0			BIT(0)

/* 2 REG_P2PPS1_STATE			(Offset 0x057D) */

#define BIT_P2P1_POWER_STATE				BIT(7)
#define BIT_P2P1_CTWINDOW_ON				BIT(6)
#define BIT_P2P1_BEACON_AREA_ON			BIT(5)
#define BIT_P2P1_CTWIN_EARLY_DISTX			BIT(4)
#define BIT_P2P1_NOA1_OFF_PERIOD			BIT(3)
#define BIT_P2P1_FORCE_DOZE1				BIT(2)
#define BIT_P2P1_NOA0_OFF_PERIOD			BIT(1)
#define BIT_P2P1_FORCE_DOZE0				BIT(0)

/* 2 REG_P2PPS2_SPEC_STATE			(Offset 0x057E) */

#define BIT_P2P2_SPEC_POWER_STATE			BIT(7)
#define BIT_P2P2_SPEC_CTWINDOW_ON			BIT(6)
#define BIT_P2P2_SPEC_BCN_AREA_ON			BIT(5)
#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX		BIT(4)
#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD			BIT(3)
#define BIT_P2P2_SPEC_FORCE_DOZE1			BIT(2)
#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD			BIT(1)
#define BIT_P2P2_SPEC_FORCE_DOZE0			BIT(0)

/* 2 REG_P2PPS2_STATE			(Offset 0x057F) */

#define BIT_P2P2_POWER_STATE				BIT(7)
#define BIT_P2P2_CTWINDOW_ON				BIT(6)
#define BIT_P2P2_BEACON_AREA_ON			BIT(5)
#define BIT_P2P2_CTWIN_EARLY_DISTX			BIT(4)
#define BIT_P2P2_NOA1_OFF_PERIOD			BIT(3)
#define BIT_P2P2_FORCE_DOZE1				BIT(2)
#define BIT_P2P2_NOA0_OFF_PERIOD			BIT(1)
#define BIT_P2P2_FORCE_DOZE0				BIT(0)

/* 2 REG_PS_TIMER0				(Offset 0x0580) */

#define BIT_SHIFT_PSTIMER0_INT				5
#define BIT_MASK_PSTIMER0_INT				0x7ffffff
#define BIT_PSTIMER0_INT(x)				(((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT)
#define BITS_PSTIMER0_INT				(BIT_MASK_PSTIMER0_INT << BIT_SHIFT_PSTIMER0_INT)
#define BIT_CLEAR_PSTIMER0_INT(x)			((x) & (~BITS_PSTIMER0_INT))
#define BIT_GET_PSTIMER0_INT(x)			(((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT)
#define BIT_SET_PSTIMER0_INT(x, v)			(BIT_CLEAR_PSTIMER0_INT(x) | BIT_PSTIMER0_INT(v))

/* 2 REG_PS_TIMER1				(Offset 0x0584) */

#define BIT_SHIFT_PSTIMER1_INT				5
#define BIT_MASK_PSTIMER1_INT				0x7ffffff
#define BIT_PSTIMER1_INT(x)				(((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT)
#define BITS_PSTIMER1_INT				(BIT_MASK_PSTIMER1_INT << BIT_SHIFT_PSTIMER1_INT)
#define BIT_CLEAR_PSTIMER1_INT(x)			((x) & (~BITS_PSTIMER1_INT))
#define BIT_GET_PSTIMER1_INT(x)			(((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT)
#define BIT_SET_PSTIMER1_INT(x, v)			(BIT_CLEAR_PSTIMER1_INT(x) | BIT_PSTIMER1_INT(v))

/* 2 REG_PS_TIMER2				(Offset 0x0588) */

#define BIT_SHIFT_PSTIMER2_INT				5
#define BIT_MASK_PSTIMER2_INT				0x7ffffff
#define BIT_PSTIMER2_INT(x)				(((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT)
#define BITS_PSTIMER2_INT				(BIT_MASK_PSTIMER2_INT << BIT_SHIFT_PSTIMER2_INT)
#define BIT_CLEAR_PSTIMER2_INT(x)			((x) & (~BITS_PSTIMER2_INT))
#define BIT_GET_PSTIMER2_INT(x)			(((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT)
#define BIT_SET_PSTIMER2_INT(x, v)			(BIT_CLEAR_PSTIMER2_INT(x) | BIT_PSTIMER2_INT(v))

/* 2 REG_TBTT_CTN_AREA			(Offset 0x058C) */

#define BIT_SHIFT_TBTT_CTN_AREA			0
#define BIT_MASK_TBTT_CTN_AREA				0xff
#define BIT_TBTT_CTN_AREA(x)				(((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA)
#define BITS_TBTT_CTN_AREA				(BIT_MASK_TBTT_CTN_AREA << BIT_SHIFT_TBTT_CTN_AREA)
#define BIT_CLEAR_TBTT_CTN_AREA(x)			((x) & (~BITS_TBTT_CTN_AREA))
#define BIT_GET_TBTT_CTN_AREA(x)			(((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA)
#define BIT_SET_TBTT_CTN_AREA(x, v)			(BIT_CLEAR_TBTT_CTN_AREA(x) | BIT_TBTT_CTN_AREA(v))

/* 2 REG_FORCE_BCN_IFS			(Offset 0x058E) */

#define BIT_SHIFT_FORCE_BCN_IFS			0
#define BIT_MASK_FORCE_BCN_IFS				0xff
#define BIT_FORCE_BCN_IFS(x)				(((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS)
#define BITS_FORCE_BCN_IFS				(BIT_MASK_FORCE_BCN_IFS << BIT_SHIFT_FORCE_BCN_IFS)
#define BIT_CLEAR_FORCE_BCN_IFS(x)			((x) & (~BITS_FORCE_BCN_IFS))
#define BIT_GET_FORCE_BCN_IFS(x)			(((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS)
#define BIT_SET_FORCE_BCN_IFS(x, v)			(BIT_CLEAR_FORCE_BCN_IFS(x) | BIT_FORCE_BCN_IFS(v))

/* 2 REG_TXOP_MIN				(Offset 0x0590) */

#define BIT_NAV_BLK_HGQ				BIT(15)
#define BIT_NAV_BLK_MGQ				BIT(14)

#define BIT_SHIFT_TXOP_MIN				0
#define BIT_MASK_TXOP_MIN				0x3fff
#define BIT_TXOP_MIN(x)				(((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN)
#define BITS_TXOP_MIN					(BIT_MASK_TXOP_MIN << BIT_SHIFT_TXOP_MIN)
#define BIT_CLEAR_TXOP_MIN(x)				((x) & (~BITS_TXOP_MIN))
#define BIT_GET_TXOP_MIN(x)				(((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN)
#define BIT_SET_TXOP_MIN(x, v)				(BIT_CLEAR_TXOP_MIN(x) | BIT_TXOP_MIN(v))

/* 2 REG_PRE_BKF_TIME			(Offset 0x0592) */

#define BIT_SHIFT_PRE_BKF_TIME				0
#define BIT_MASK_PRE_BKF_TIME				0xff
#define BIT_PRE_BKF_TIME(x)				(((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME)
#define BITS_PRE_BKF_TIME				(BIT_MASK_PRE_BKF_TIME << BIT_SHIFT_PRE_BKF_TIME)
#define BIT_CLEAR_PRE_BKF_TIME(x)			((x) & (~BITS_PRE_BKF_TIME))
#define BIT_GET_PRE_BKF_TIME(x)			(((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME)
#define BIT_SET_PRE_BKF_TIME(x, v)			(BIT_CLEAR_PRE_BKF_TIME(x) | BIT_PRE_BKF_TIME(v))

/* 2 REG_CROSS_TXOP_CTRL			(Offset 0x0593) */

#define BIT_NOPKT_END_RTSMF				BIT(7)
#define BIT_TXOP_FAIL_BREAK				BIT(3)
#define BIT_DTIM_BYPASS				BIT(2)
#define BIT_RTS_NAV_TXOP				BIT(1)
#define BIT_NOT_CROSS_TXOP				BIT(0)

/* 2 REG_TBTT_INT_SHIFT_CLI			(Offset 0x0594) */

#define BIT_TBTT_INT_SHIFT_DIR_CLI3_V1			BIT(31)

#define BIT_SHIFT_TBTT_INT_SHIFT_CLI3_V1		24
#define BIT_MASK_TBTT_INT_SHIFT_CLI3_V1		0x7f
#define BIT_TBTT_INT_SHIFT_CLI3_V1(x)			(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI3_V1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_V1)
#define BITS_TBTT_INT_SHIFT_CLI3_V1			(BIT_MASK_TBTT_INT_SHIFT_CLI3_V1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI3_V1)
#define BIT_CLEAR_TBTT_INT_SHIFT_CLI3_V1(x)		((x) & (~BITS_TBTT_INT_SHIFT_CLI3_V1))
#define BIT_GET_TBTT_INT_SHIFT_CLI3_V1(x)		(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI3_V1) & BIT_MASK_TBTT_INT_SHIFT_CLI3_V1)
#define BIT_SET_TBTT_INT_SHIFT_CLI3_V1(x, v)		(BIT_CLEAR_TBTT_INT_SHIFT_CLI3_V1(x) | BIT_TBTT_INT_SHIFT_CLI3_V1(v))

#define BIT_TBTT_INT_SHIFT_DIR_CLI2_V1			BIT(23)

#define BIT_SHIFT_TBTT_INT_SHIFT_CLI2_V1		16
#define BIT_MASK_TBTT_INT_SHIFT_CLI2_V1		0x7f
#define BIT_TBTT_INT_SHIFT_CLI2_V1(x)			(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI2_V1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_V1)
#define BITS_TBTT_INT_SHIFT_CLI2_V1			(BIT_MASK_TBTT_INT_SHIFT_CLI2_V1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI2_V1)
#define BIT_CLEAR_TBTT_INT_SHIFT_CLI2_V1(x)		((x) & (~BITS_TBTT_INT_SHIFT_CLI2_V1))
#define BIT_GET_TBTT_INT_SHIFT_CLI2_V1(x)		(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI2_V1) & BIT_MASK_TBTT_INT_SHIFT_CLI2_V1)
#define BIT_SET_TBTT_INT_SHIFT_CLI2_V1(x, v)		(BIT_CLEAR_TBTT_INT_SHIFT_CLI2_V1(x) | BIT_TBTT_INT_SHIFT_CLI2_V1(v))

#define BIT_TBTT_INT_SHIFT_DIR_CLI1_V1			BIT(15)

#define BIT_SHIFT_TBTT_INT_SHIFT_CLI1_V1		8
#define BIT_MASK_TBTT_INT_SHIFT_CLI1_V1		0x7f
#define BIT_TBTT_INT_SHIFT_CLI1_V1(x)			(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI1_V1) << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_V1)
#define BITS_TBTT_INT_SHIFT_CLI1_V1			(BIT_MASK_TBTT_INT_SHIFT_CLI1_V1 << BIT_SHIFT_TBTT_INT_SHIFT_CLI1_V1)
#define BIT_CLEAR_TBTT_INT_SHIFT_CLI1_V1(x)		((x) & (~BITS_TBTT_INT_SHIFT_CLI1_V1))
#define BIT_GET_TBTT_INT_SHIFT_CLI1_V1(x)		(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI1_V1) & BIT_MASK_TBTT_INT_SHIFT_CLI1_V1)
#define BIT_SET_TBTT_INT_SHIFT_CLI1_V1(x, v)		(BIT_CLEAR_TBTT_INT_SHIFT_CLI1_V1(x) | BIT_TBTT_INT_SHIFT_CLI1_V1(v))

#define BIT_TBTT_INT_SHIFT_DIR_CLI0_V1			BIT(7)

#define BIT_SHIFT_TBTT_INT_SHIFT_CLI0			0
#define BIT_MASK_TBTT_INT_SHIFT_CLI0			0x7f
#define BIT_TBTT_INT_SHIFT_CLI0(x)			(((x) & BIT_MASK_TBTT_INT_SHIFT_CLI0) << BIT_SHIFT_TBTT_INT_SHIFT_CLI0)
#define BITS_TBTT_INT_SHIFT_CLI0			(BIT_MASK_TBTT_INT_SHIFT_CLI0 << BIT_SHIFT_TBTT_INT_SHIFT_CLI0)
#define BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x)		((x) & (~BITS_TBTT_INT_SHIFT_CLI0))
#define BIT_GET_TBTT_INT_SHIFT_CLI0(x)			(((x) >> BIT_SHIFT_TBTT_INT_SHIFT_CLI0) & BIT_MASK_TBTT_INT_SHIFT_CLI0)
#define BIT_SET_TBTT_INT_SHIFT_CLI0(x, v)		(BIT_CLEAR_TBTT_INT_SHIFT_CLI0(x) | BIT_TBTT_INT_SHIFT_CLI0(v))

/* 2 REG_TBTT_INT_SHIFT_ENABLE		(Offset 0x0598) */

#define BIT_EN_TBTT_RTY				BIT(1)
#define BIT_TBTT_INT_SHIFT_ENABLE			BIT(0)

/* 2 REG_ATIMWND_GROUP1			(Offset 0x05A0) */

#define BIT_SHIFT_ATIMWND_GROUP1			0
#define BIT_MASK_ATIMWND_GROUP1			0xff
#define BIT_ATIMWND_GROUP1(x)				(((x) & BIT_MASK_ATIMWND_GROUP1) << BIT_SHIFT_ATIMWND_GROUP1)
#define BITS_ATIMWND_GROUP1				(BIT_MASK_ATIMWND_GROUP1 << BIT_SHIFT_ATIMWND_GROUP1)
#define BIT_CLEAR_ATIMWND_GROUP1(x)			((x) & (~BITS_ATIMWND_GROUP1))
#define BIT_GET_ATIMWND_GROUP1(x)			(((x) >> BIT_SHIFT_ATIMWND_GROUP1) & BIT_MASK_ATIMWND_GROUP1)
#define BIT_SET_ATIMWND_GROUP1(x, v)			(BIT_CLEAR_ATIMWND_GROUP1(x) | BIT_ATIMWND_GROUP1(v))

/* 2 REG_ATIMWND_GROUP2			(Offset 0x05A1) */

#define BIT_SHIFT_ATIMWND_GROUP2			0
#define BIT_MASK_ATIMWND_GROUP2			0xff
#define BIT_ATIMWND_GROUP2(x)				(((x) & BIT_MASK_ATIMWND_GROUP2) << BIT_SHIFT_ATIMWND_GROUP2)
#define BITS_ATIMWND_GROUP2				(BIT_MASK_ATIMWND_GROUP2 << BIT_SHIFT_ATIMWND_GROUP2)
#define BIT_CLEAR_ATIMWND_GROUP2(x)			((x) & (~BITS_ATIMWND_GROUP2))
#define BIT_GET_ATIMWND_GROUP2(x)			(((x) >> BIT_SHIFT_ATIMWND_GROUP2) & BIT_MASK_ATIMWND_GROUP2)
#define BIT_SET_ATIMWND_GROUP2(x, v)			(BIT_CLEAR_ATIMWND_GROUP2(x) | BIT_ATIMWND_GROUP2(v))

/* 2 REG_ATIMWND_GROUP3			(Offset 0x05A2) */

#define BIT_SHIFT_ATIMWND_GROUP3			0
#define BIT_MASK_ATIMWND_GROUP3			0xff
#define BIT_ATIMWND_GROUP3(x)				(((x) & BIT_MASK_ATIMWND_GROUP3) << BIT_SHIFT_ATIMWND_GROUP3)
#define BITS_ATIMWND_GROUP3				(BIT_MASK_ATIMWND_GROUP3 << BIT_SHIFT_ATIMWND_GROUP3)
#define BIT_CLEAR_ATIMWND_GROUP3(x)			((x) & (~BITS_ATIMWND_GROUP3))
#define BIT_GET_ATIMWND_GROUP3(x)			(((x) >> BIT_SHIFT_ATIMWND_GROUP3) & BIT_MASK_ATIMWND_GROUP3)
#define BIT_SET_ATIMWND_GROUP3(x, v)			(BIT_CLEAR_ATIMWND_GROUP3(x) | BIT_ATIMWND_GROUP3(v))

/* 2 REG_ATIMWND_GROUP4			(Offset 0x05A3) */

#define BIT_SHIFT_ATIMWND_GROUP4			0
#define BIT_MASK_ATIMWND_GROUP4			0xff
#define BIT_ATIMWND_GROUP4(x)				(((x) & BIT_MASK_ATIMWND_GROUP4) << BIT_SHIFT_ATIMWND_GROUP4)
#define BITS_ATIMWND_GROUP4				(BIT_MASK_ATIMWND_GROUP4 << BIT_SHIFT_ATIMWND_GROUP4)
#define BIT_CLEAR_ATIMWND_GROUP4(x)			((x) & (~BITS_ATIMWND_GROUP4))
#define BIT_GET_ATIMWND_GROUP4(x)			(((x) >> BIT_SHIFT_ATIMWND_GROUP4) & BIT_MASK_ATIMWND_GROUP4)
#define BIT_SET_ATIMWND_GROUP4(x, v)			(BIT_CLEAR_ATIMWND_GROUP4(x) | BIT_ATIMWND_GROUP4(v))

/* 2 REG_DTIM_COUNT_GROUP1			(Offset 0x05A4) */

#define BIT_SHIFT_DTIM_COUNT_GROUP1			0
#define BIT_MASK_DTIM_COUNT_GROUP1			0xff
#define BIT_DTIM_COUNT_GROUP1(x)			(((x) & BIT_MASK_DTIM_COUNT_GROUP1) << BIT_SHIFT_DTIM_COUNT_GROUP1)
#define BITS_DTIM_COUNT_GROUP1				(BIT_MASK_DTIM_COUNT_GROUP1 << BIT_SHIFT_DTIM_COUNT_GROUP1)
#define BIT_CLEAR_DTIM_COUNT_GROUP1(x)			((x) & (~BITS_DTIM_COUNT_GROUP1))
#define BIT_GET_DTIM_COUNT_GROUP1(x)			(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP1) & BIT_MASK_DTIM_COUNT_GROUP1)
#define BIT_SET_DTIM_COUNT_GROUP1(x, v)		(BIT_CLEAR_DTIM_COUNT_GROUP1(x) | BIT_DTIM_COUNT_GROUP1(v))

/* 2 REG_DTIM_COUNT_GROUP2			(Offset 0x05A5) */

#define BIT_SHIFT_DTIM_COUNT_GROUP2			0
#define BIT_MASK_DTIM_COUNT_GROUP2			0xff
#define BIT_DTIM_COUNT_GROUP2(x)			(((x) & BIT_MASK_DTIM_COUNT_GROUP2) << BIT_SHIFT_DTIM_COUNT_GROUP2)
#define BITS_DTIM_COUNT_GROUP2				(BIT_MASK_DTIM_COUNT_GROUP2 << BIT_SHIFT_DTIM_COUNT_GROUP2)
#define BIT_CLEAR_DTIM_COUNT_GROUP2(x)			((x) & (~BITS_DTIM_COUNT_GROUP2))
#define BIT_GET_DTIM_COUNT_GROUP2(x)			(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP2) & BIT_MASK_DTIM_COUNT_GROUP2)
#define BIT_SET_DTIM_COUNT_GROUP2(x, v)		(BIT_CLEAR_DTIM_COUNT_GROUP2(x) | BIT_DTIM_COUNT_GROUP2(v))

/* 2 REG_DTIM_COUNT_GROUP3			(Offset 0x05A6) */

#define BIT_SHIFT_DTIM_COUNT_GROUP3			0
#define BIT_MASK_DTIM_COUNT_GROUP3			0xff
#define BIT_DTIM_COUNT_GROUP3(x)			(((x) & BIT_MASK_DTIM_COUNT_GROUP3) << BIT_SHIFT_DTIM_COUNT_GROUP3)
#define BITS_DTIM_COUNT_GROUP3				(BIT_MASK_DTIM_COUNT_GROUP3 << BIT_SHIFT_DTIM_COUNT_GROUP3)
#define BIT_CLEAR_DTIM_COUNT_GROUP3(x)			((x) & (~BITS_DTIM_COUNT_GROUP3))
#define BIT_GET_DTIM_COUNT_GROUP3(x)			(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP3) & BIT_MASK_DTIM_COUNT_GROUP3)
#define BIT_SET_DTIM_COUNT_GROUP3(x, v)		(BIT_CLEAR_DTIM_COUNT_GROUP3(x) | BIT_DTIM_COUNT_GROUP3(v))

/* 2 REG_DTIM_COUNT_GROUP4			(Offset 0x05A7) */

#define BIT_SHIFT_ATIM_CFG_SEL				24
#define BIT_MASK_ATIM_CFG_SEL				0x3
#define BIT_ATIM_CFG_SEL(x)				(((x) & BIT_MASK_ATIM_CFG_SEL) << BIT_SHIFT_ATIM_CFG_SEL)
#define BITS_ATIM_CFG_SEL				(BIT_MASK_ATIM_CFG_SEL << BIT_SHIFT_ATIM_CFG_SEL)
#define BIT_CLEAR_ATIM_CFG_SEL(x)			((x) & (~BITS_ATIM_CFG_SEL))
#define BIT_GET_ATIM_CFG_SEL(x)			(((x) >> BIT_SHIFT_ATIM_CFG_SEL) & BIT_MASK_ATIM_CFG_SEL)
#define BIT_SET_ATIM_CFG_SEL(x, v)			(BIT_CLEAR_ATIM_CFG_SEL(x) | BIT_ATIM_CFG_SEL(v))

#define BIT_SHIFT_DIS_ATIM_V1				16
#define BIT_MASK_DIS_ATIM_V1				0xff
#define BIT_DIS_ATIM_V1(x)				(((x) & BIT_MASK_DIS_ATIM_V1) << BIT_SHIFT_DIS_ATIM_V1)
#define BITS_DIS_ATIM_V1				(BIT_MASK_DIS_ATIM_V1 << BIT_SHIFT_DIS_ATIM_V1)
#define BIT_CLEAR_DIS_ATIM_V1(x)			((x) & (~BITS_DIS_ATIM_V1))
#define BIT_GET_DIS_ATIM_V1(x)				(((x) >> BIT_SHIFT_DIS_ATIM_V1) & BIT_MASK_DIS_ATIM_V1)
#define BIT_SET_DIS_ATIM_V1(x, v)			(BIT_CLEAR_DIS_ATIM_V1(x) | BIT_DIS_ATIM_V1(v))

#define BIT_SHIFT_ATIM_URGENT_V1			16
#define BIT_MASK_ATIM_URGENT_V1			0xff
#define BIT_ATIM_URGENT_V1(x)				(((x) & BIT_MASK_ATIM_URGENT_V1) << BIT_SHIFT_ATIM_URGENT_V1)
#define BITS_ATIM_URGENT_V1				(BIT_MASK_ATIM_URGENT_V1 << BIT_SHIFT_ATIM_URGENT_V1)
#define BIT_CLEAR_ATIM_URGENT_V1(x)			((x) & (~BITS_ATIM_URGENT_V1))
#define BIT_GET_ATIM_URGENT_V1(x)			(((x) >> BIT_SHIFT_ATIM_URGENT_V1) & BIT_MASK_ATIM_URGENT_V1)
#define BIT_SET_ATIM_URGENT_V1(x, v)			(BIT_CLEAR_ATIM_URGENT_V1(x) | BIT_ATIM_URGENT_V1(v))

#define BIT_HIQ_NO_LMT_EN_VAP7				BIT(7)
#define BIT_HIQ_NO_LMT_EN_VAP6				BIT(6)
#define BIT_HIQ_NO_LMT_EN_VAP5				BIT(5)
#define BIT_HIQ_NO_LMT_EN_VAP4				BIT(4)
#define BIT_HIQ_NO_LMT_EN_VAP3				BIT(3)
#define BIT_HIQ_NO_LMT_EN_VAP2				BIT(2)
#define BIT_HIQ_NO_LMT_EN_VAP1				BIT(1)

#define BIT_SHIFT_DTIM_COUNT_GROUP4			0
#define BIT_MASK_DTIM_COUNT_GROUP4			0xff
#define BIT_DTIM_COUNT_GROUP4(x)			(((x) & BIT_MASK_DTIM_COUNT_GROUP4) << BIT_SHIFT_DTIM_COUNT_GROUP4)
#define BITS_DTIM_COUNT_GROUP4				(BIT_MASK_DTIM_COUNT_GROUP4 << BIT_SHIFT_DTIM_COUNT_GROUP4)
#define BIT_CLEAR_DTIM_COUNT_GROUP4(x)			((x) & (~BITS_DTIM_COUNT_GROUP4))
#define BIT_GET_DTIM_COUNT_GROUP4(x)			(((x) >> BIT_SHIFT_DTIM_COUNT_GROUP4) & BIT_MASK_DTIM_COUNT_GROUP4)
#define BIT_SET_DTIM_COUNT_GROUP4(x, v)		(BIT_CLEAR_DTIM_COUNT_GROUP4(x) | BIT_DTIM_COUNT_GROUP4(v))

#define BIT_HIQ_NO_LMT_EN_ROOT				BIT(0)

#define BIT_SHIFT_MBID_BCNQ_EN_V1			0
#define BIT_MASK_MBID_BCNQ_EN_V1			0xff
#define BIT_MBID_BCNQ_EN_V1(x)				(((x) & BIT_MASK_MBID_BCNQ_EN_V1) << BIT_SHIFT_MBID_BCNQ_EN_V1)
#define BITS_MBID_BCNQ_EN_V1				(BIT_MASK_MBID_BCNQ_EN_V1 << BIT_SHIFT_MBID_BCNQ_EN_V1)
#define BIT_CLEAR_MBID_BCNQ_EN_V1(x)			((x) & (~BITS_MBID_BCNQ_EN_V1))
#define BIT_GET_MBID_BCNQ_EN_V1(x)			(((x) >> BIT_SHIFT_MBID_BCNQ_EN_V1) & BIT_MASK_MBID_BCNQ_EN_V1)
#define BIT_SET_MBID_BCNQ_EN_V1(x, v)			(BIT_CLEAR_MBID_BCNQ_EN_V1(x) | BIT_MBID_BCNQ_EN_V1(v))

/* 2 REG_EARLY_128US				(Offset 0x05B1) */

#define BIT_SHIFT_TSFT_SEL_TIMER1			3
#define BIT_MASK_TSFT_SEL_TIMER1			0x7
#define BIT_TSFT_SEL_TIMER1(x)				(((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1)
#define BITS_TSFT_SEL_TIMER1				(BIT_MASK_TSFT_SEL_TIMER1 << BIT_SHIFT_TSFT_SEL_TIMER1)
#define BIT_CLEAR_TSFT_SEL_TIMER1(x)			((x) & (~BITS_TSFT_SEL_TIMER1))
#define BIT_GET_TSFT_SEL_TIMER1(x)			(((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1)
#define BIT_SET_TSFT_SEL_TIMER1(x, v)			(BIT_CLEAR_TSFT_SEL_TIMER1(x) | BIT_TSFT_SEL_TIMER1(v))

#define BIT_SHIFT_EARLY_128US				0
#define BIT_MASK_EARLY_128US				0x7
#define BIT_EARLY_128US(x)				(((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US)
#define BITS_EARLY_128US				(BIT_MASK_EARLY_128US << BIT_SHIFT_EARLY_128US)
#define BIT_CLEAR_EARLY_128US(x)			((x) & (~BITS_EARLY_128US))
#define BIT_GET_EARLY_128US(x)				(((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US)
#define BIT_SET_EARLY_128US(x, v)			(BIT_CLEAR_EARLY_128US(x) | BIT_EARLY_128US(v))

/* 2 REG_P2PPS1_CTRL				(Offset 0x05B2) */

#define BIT_P2P1_CTW_ALLSTASLEEP			BIT(7)
#define BIT_P2P1_OFF_DISTX_EN				BIT(6)
#define BIT_P2P1_PWR_MGT_EN				BIT(5)
#define BIT_P2P1_NOA1_EN				BIT(2)
#define BIT_P2P1_NOA0_EN				BIT(1)

/* 2 REG_P2PPS2_CTRL				(Offset 0x05B3) */

#define BIT_P2P2_CTW_ALLSTASLEEP			BIT(7)
#define BIT_P2P2_OFF_DISTX_EN				BIT(6)
#define BIT_P2P2_PWR_MGT_EN				BIT(5)
#define BIT_P2P2_NOA1_EN				BIT(2)
#define BIT_P2P2_NOA0_EN				BIT(1)

/* 2 REG_TIMER0_SRC_SEL			(Offset 0x05B4) */

#define BIT_SHIFT_SYNC_CLI_SEL				4
#define BIT_MASK_SYNC_CLI_SEL				0x7
#define BIT_SYNC_CLI_SEL(x)				(((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL)
#define BITS_SYNC_CLI_SEL				(BIT_MASK_SYNC_CLI_SEL << BIT_SHIFT_SYNC_CLI_SEL)
#define BIT_CLEAR_SYNC_CLI_SEL(x)			((x) & (~BITS_SYNC_CLI_SEL))
#define BIT_GET_SYNC_CLI_SEL(x)			(((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL)
#define BIT_SET_SYNC_CLI_SEL(x, v)			(BIT_CLEAR_SYNC_CLI_SEL(x) | BIT_SYNC_CLI_SEL(v))

#define BIT_SHIFT_TSFT_SEL_TIMER0			0
#define BIT_MASK_TSFT_SEL_TIMER0			0x7
#define BIT_TSFT_SEL_TIMER0(x)				(((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0)
#define BITS_TSFT_SEL_TIMER0				(BIT_MASK_TSFT_SEL_TIMER0 << BIT_SHIFT_TSFT_SEL_TIMER0)
#define BIT_CLEAR_TSFT_SEL_TIMER0(x)			((x) & (~BITS_TSFT_SEL_TIMER0))
#define BIT_GET_TSFT_SEL_TIMER0(x)			(((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0)
#define BIT_SET_TSFT_SEL_TIMER0(x, v)			(BIT_CLEAR_TSFT_SEL_TIMER0(x) | BIT_TSFT_SEL_TIMER0(v))

/* 2 REG_NOA_UNIT_SEL			(Offset 0x05B5) */

#define BIT_SHIFT_NOA_UNIT2_SEL			8
#define BIT_MASK_NOA_UNIT2_SEL				0x7
#define BIT_NOA_UNIT2_SEL(x)				(((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL)
#define BITS_NOA_UNIT2_SEL				(BIT_MASK_NOA_UNIT2_SEL << BIT_SHIFT_NOA_UNIT2_SEL)
#define BIT_CLEAR_NOA_UNIT2_SEL(x)			((x) & (~BITS_NOA_UNIT2_SEL))
#define BIT_GET_NOA_UNIT2_SEL(x)			(((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL)
#define BIT_SET_NOA_UNIT2_SEL(x, v)			(BIT_CLEAR_NOA_UNIT2_SEL(x) | BIT_NOA_UNIT2_SEL(v))

#define BIT_SHIFT_NOA_UNIT1_SEL			4
#define BIT_MASK_NOA_UNIT1_SEL				0x7
#define BIT_NOA_UNIT1_SEL(x)				(((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL)
#define BITS_NOA_UNIT1_SEL				(BIT_MASK_NOA_UNIT1_SEL << BIT_SHIFT_NOA_UNIT1_SEL)
#define BIT_CLEAR_NOA_UNIT1_SEL(x)			((x) & (~BITS_NOA_UNIT1_SEL))
#define BIT_GET_NOA_UNIT1_SEL(x)			(((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL)
#define BIT_SET_NOA_UNIT1_SEL(x, v)			(BIT_CLEAR_NOA_UNIT1_SEL(x) | BIT_NOA_UNIT1_SEL(v))

#define BIT_SHIFT_NOA_UNIT0_SEL			0
#define BIT_MASK_NOA_UNIT0_SEL				0x7
#define BIT_NOA_UNIT0_SEL(x)				(((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL)
#define BITS_NOA_UNIT0_SEL				(BIT_MASK_NOA_UNIT0_SEL << BIT_SHIFT_NOA_UNIT0_SEL)
#define BIT_CLEAR_NOA_UNIT0_SEL(x)			((x) & (~BITS_NOA_UNIT0_SEL))
#define BIT_GET_NOA_UNIT0_SEL(x)			(((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL)
#define BIT_SET_NOA_UNIT0_SEL(x, v)			(BIT_CLEAR_NOA_UNIT0_SEL(x) | BIT_NOA_UNIT0_SEL(v))

/* 2 REG_P2POFF_DIS_TXTIME			(Offset 0x05B7) */

#define BIT_SHIFT_P2POFF_DIS_TXTIME			0
#define BIT_MASK_P2POFF_DIS_TXTIME			0xff
#define BIT_P2POFF_DIS_TXTIME(x)			(((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME)
#define BITS_P2POFF_DIS_TXTIME				(BIT_MASK_P2POFF_DIS_TXTIME << BIT_SHIFT_P2POFF_DIS_TXTIME)
#define BIT_CLEAR_P2POFF_DIS_TXTIME(x)			((x) & (~BITS_P2POFF_DIS_TXTIME))
#define BIT_GET_P2POFF_DIS_TXTIME(x)			(((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME)
#define BIT_SET_P2POFF_DIS_TXTIME(x, v)		(BIT_CLEAR_P2POFF_DIS_TXTIME(x) | BIT_P2POFF_DIS_TXTIME(v))

/* 2 REG_MBSSID_BCN_SPACE2			(Offset 0x05B8) */

#define BIT_SHIFT_BCN_SPACE_CLINT2			16
#define BIT_MASK_BCN_SPACE_CLINT2			0xfff
#define BIT_BCN_SPACE_CLINT2(x)			(((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2)
#define BITS_BCN_SPACE_CLINT2				(BIT_MASK_BCN_SPACE_CLINT2 << BIT_SHIFT_BCN_SPACE_CLINT2)
#define BIT_CLEAR_BCN_SPACE_CLINT2(x)			((x) & (~BITS_BCN_SPACE_CLINT2))
#define BIT_GET_BCN_SPACE_CLINT2(x)			(((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2)
#define BIT_SET_BCN_SPACE_CLINT2(x, v)			(BIT_CLEAR_BCN_SPACE_CLINT2(x) | BIT_BCN_SPACE_CLINT2(v))

#define BIT_SHIFT_BCN_SPACE_CLINT1			0
#define BIT_MASK_BCN_SPACE_CLINT1			0xfff
#define BIT_BCN_SPACE_CLINT1(x)			(((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1)
#define BITS_BCN_SPACE_CLINT1				(BIT_MASK_BCN_SPACE_CLINT1 << BIT_SHIFT_BCN_SPACE_CLINT1)
#define BIT_CLEAR_BCN_SPACE_CLINT1(x)			((x) & (~BITS_BCN_SPACE_CLINT1))
#define BIT_GET_BCN_SPACE_CLINT1(x)			(((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1)
#define BIT_SET_BCN_SPACE_CLINT1(x, v)			(BIT_CLEAR_BCN_SPACE_CLINT1(x) | BIT_BCN_SPACE_CLINT1(v))

/* 2 REG_MBSSID_BCN_SPACE3			(Offset 0x05BC) */

#define BIT_SHIFT_SUB_BCN_SPACE			16
#define BIT_MASK_SUB_BCN_SPACE				0xff
#define BIT_SUB_BCN_SPACE(x)				(((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE)
#define BITS_SUB_BCN_SPACE				(BIT_MASK_SUB_BCN_SPACE << BIT_SHIFT_SUB_BCN_SPACE)
#define BIT_CLEAR_SUB_BCN_SPACE(x)			((x) & (~BITS_SUB_BCN_SPACE))
#define BIT_GET_SUB_BCN_SPACE(x)			(((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE)
#define BIT_SET_SUB_BCN_SPACE(x, v)			(BIT_CLEAR_SUB_BCN_SPACE(x) | BIT_SUB_BCN_SPACE(v))

#define BIT_SHIFT_BCN_SPACE_CLINT3			0
#define BIT_MASK_BCN_SPACE_CLINT3			0xfff
#define BIT_BCN_SPACE_CLINT3(x)			(((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3)
#define BITS_BCN_SPACE_CLINT3				(BIT_MASK_BCN_SPACE_CLINT3 << BIT_SHIFT_BCN_SPACE_CLINT3)
#define BIT_CLEAR_BCN_SPACE_CLINT3(x)			((x) & (~BITS_BCN_SPACE_CLINT3))
#define BIT_GET_BCN_SPACE_CLINT3(x)			(((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3)
#define BIT_SET_BCN_SPACE_CLINT3(x, v)			(BIT_CLEAR_BCN_SPACE_CLINT3(x) | BIT_BCN_SPACE_CLINT3(v))

/* 2 REG_ACMHWCTRL				(Offset 0x05C0) */

#define BIT_BEQ_ACM_STATUS				BIT(7)
#define BIT_VIQ_ACM_STATUS				BIT(6)
#define BIT_VOQ_ACM_STATUS				BIT(5)
#define BIT_BEQ_ACM_EN					BIT(3)
#define BIT_VIQ_ACM_EN					BIT(2)
#define BIT_VOQ_ACM_EN					BIT(1)
#define BIT_ACMHWEN					BIT(0)

/* 2 REG_ACMRSTCTRL				(Offset 0x05C1) */

#define BIT_BE_ACM_RESET_USED_TIME			BIT(2)
#define BIT_VI_ACM_RESET_USED_TIME			BIT(1)
#define BIT_VO_ACM_RESET_USED_TIME			BIT(0)

/* 2 REG_ACMAVG				(Offset 0x05C2) */

#define BIT_SHIFT_AVGPERIOD				0
#define BIT_MASK_AVGPERIOD				0xffff
#define BIT_AVGPERIOD(x)				(((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD)
#define BITS_AVGPERIOD					(BIT_MASK_AVGPERIOD << BIT_SHIFT_AVGPERIOD)
#define BIT_CLEAR_AVGPERIOD(x)				((x) & (~BITS_AVGPERIOD))
#define BIT_GET_AVGPERIOD(x)				(((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD)
#define BIT_SET_AVGPERIOD(x, v)			(BIT_CLEAR_AVGPERIOD(x) | BIT_AVGPERIOD(v))

/* 2 REG_VO_ADMTIME				(Offset 0x05C4) */

#define BIT_SHIFT_VO_ADMITTED_TIME			0
#define BIT_MASK_VO_ADMITTED_TIME			0xffff
#define BIT_VO_ADMITTED_TIME(x)			(((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME)
#define BITS_VO_ADMITTED_TIME				(BIT_MASK_VO_ADMITTED_TIME << BIT_SHIFT_VO_ADMITTED_TIME)
#define BIT_CLEAR_VO_ADMITTED_TIME(x)			((x) & (~BITS_VO_ADMITTED_TIME))
#define BIT_GET_VO_ADMITTED_TIME(x)			(((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME)
#define BIT_SET_VO_ADMITTED_TIME(x, v)			(BIT_CLEAR_VO_ADMITTED_TIME(x) | BIT_VO_ADMITTED_TIME(v))

/* 2 REG_VI_ADMTIME				(Offset 0x05C6) */

#define BIT_SHIFT_VI_ADMITTED_TIME			0
#define BIT_MASK_VI_ADMITTED_TIME			0xffff
#define BIT_VI_ADMITTED_TIME(x)			(((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME)
#define BITS_VI_ADMITTED_TIME				(BIT_MASK_VI_ADMITTED_TIME << BIT_SHIFT_VI_ADMITTED_TIME)
#define BIT_CLEAR_VI_ADMITTED_TIME(x)			((x) & (~BITS_VI_ADMITTED_TIME))
#define BIT_GET_VI_ADMITTED_TIME(x)			(((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME)
#define BIT_SET_VI_ADMITTED_TIME(x, v)			(BIT_CLEAR_VI_ADMITTED_TIME(x) | BIT_VI_ADMITTED_TIME(v))

/* 2 REG_BE_ADMTIME				(Offset 0x05C8) */

#define BIT_CHANGE_POW_BCN_AREA			BIT(9)
#define BIT_DIS_NDPA_NAV_CHK				BIT(8)

#define BIT_SHIFT_BE_ADMITTED_TIME			0
#define BIT_MASK_BE_ADMITTED_TIME			0xffff
#define BIT_BE_ADMITTED_TIME(x)			(((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME)
#define BITS_BE_ADMITTED_TIME				(BIT_MASK_BE_ADMITTED_TIME << BIT_SHIFT_BE_ADMITTED_TIME)
#define BIT_CLEAR_BE_ADMITTED_TIME(x)			((x) & (~BITS_BE_ADMITTED_TIME))
#define BIT_GET_BE_ADMITTED_TIME(x)			(((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME)
#define BIT_SET_BE_ADMITTED_TIME(x, v)			(BIT_CLEAR_BE_ADMITTED_TIME(x) | BIT_BE_ADMITTED_TIME(v))

#define BIT_SHIFT_MHDR_NAV_OFFSET			0
#define BIT_MASK_MHDR_NAV_OFFSET			0xff
#define BIT_MHDR_NAV_OFFSET(x)				(((x) & BIT_MASK_MHDR_NAV_OFFSET) << BIT_SHIFT_MHDR_NAV_OFFSET)
#define BITS_MHDR_NAV_OFFSET				(BIT_MASK_MHDR_NAV_OFFSET << BIT_SHIFT_MHDR_NAV_OFFSET)
#define BIT_CLEAR_MHDR_NAV_OFFSET(x)			((x) & (~BITS_MHDR_NAV_OFFSET))
#define BIT_GET_MHDR_NAV_OFFSET(x)			(((x) >> BIT_SHIFT_MHDR_NAV_OFFSET) & BIT_MASK_MHDR_NAV_OFFSET)
#define BIT_SET_MHDR_NAV_OFFSET(x, v)			(BIT_CLEAR_MHDR_NAV_OFFSET(x) | BIT_MHDR_NAV_OFFSET(v))

/* 2 REG_EDCA_RANDOM_GEN			(Offset 0x05CC) */

#define BIT_SHIFT_RANDOM_GEN				0
#define BIT_MASK_RANDOM_GEN				0xffffff
#define BIT_RANDOM_GEN(x)				(((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN)
#define BITS_RANDOM_GEN				(BIT_MASK_RANDOM_GEN << BIT_SHIFT_RANDOM_GEN)
#define BIT_CLEAR_RANDOM_GEN(x)			((x) & (~BITS_RANDOM_GEN))
#define BIT_GET_RANDOM_GEN(x)				(((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN)
#define BIT_SET_RANDOM_GEN(x, v)			(BIT_CLEAR_RANDOM_GEN(x) | BIT_RANDOM_GEN(v))

/* 2 REG_TXCMD_NOA_SEL			(Offset 0x05CF) */

#define BIT_SHIFT_NOA_SEL_V2				4
#define BIT_MASK_NOA_SEL_V2				0x7
#define BIT_NOA_SEL_V2(x)				(((x) & BIT_MASK_NOA_SEL_V2) << BIT_SHIFT_NOA_SEL_V2)
#define BITS_NOA_SEL_V2				(BIT_MASK_NOA_SEL_V2 << BIT_SHIFT_NOA_SEL_V2)
#define BIT_CLEAR_NOA_SEL_V2(x)			((x) & (~BITS_NOA_SEL_V2))
#define BIT_GET_NOA_SEL_V2(x)				(((x) >> BIT_SHIFT_NOA_SEL_V2) & BIT_MASK_NOA_SEL_V2)
#define BIT_SET_NOA_SEL_V2(x, v)			(BIT_CLEAR_NOA_SEL_V2(x) | BIT_NOA_SEL_V2(v))

#define BIT_SHIFT_TXCMD_SEG_SEL			0
#define BIT_MASK_TXCMD_SEG_SEL				0xf
#define BIT_TXCMD_SEG_SEL(x)				(((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL)
#define BITS_TXCMD_SEG_SEL				(BIT_MASK_TXCMD_SEG_SEL << BIT_SHIFT_TXCMD_SEG_SEL)
#define BIT_CLEAR_TXCMD_SEG_SEL(x)			((x) & (~BITS_TXCMD_SEG_SEL))
#define BIT_GET_TXCMD_SEG_SEL(x)			(((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL)
#define BIT_SET_TXCMD_SEG_SEL(x, v)			(BIT_CLEAR_TXCMD_SEG_SEL(x) | BIT_TXCMD_SEG_SEL(v))

/* 2 REG_BCNERR_CFG				(Offset 0x05D0) */

#define BIT_BCNERR_CNT_EN				BIT(20)

#define BIT_SHIFT_BCNERR_PORT_SEL_V2			16
#define BIT_MASK_BCNERR_PORT_SEL_V2			0x7
#define BIT_BCNERR_PORT_SEL_V2(x)			(((x) & BIT_MASK_BCNERR_PORT_SEL_V2) << BIT_SHIFT_BCNERR_PORT_SEL_V2)
#define BITS_BCNERR_PORT_SEL_V2			(BIT_MASK_BCNERR_PORT_SEL_V2 << BIT_SHIFT_BCNERR_PORT_SEL_V2)
#define BIT_CLEAR_BCNERR_PORT_SEL_V2(x)		((x) & (~BITS_BCNERR_PORT_SEL_V2))
#define BIT_GET_BCNERR_PORT_SEL_V2(x)			(((x) >> BIT_SHIFT_BCNERR_PORT_SEL_V2) & BIT_MASK_BCNERR_PORT_SEL_V2)
#define BIT_SET_BCNERR_PORT_SEL_V2(x, v)		(BIT_CLEAR_BCNERR_PORT_SEL_V2(x) | BIT_BCNERR_PORT_SEL_V2(v))

#define BIT_SHIFT_TXPAUSE1				8
#define BIT_MASK_TXPAUSE1				0xff
#define BIT_TXPAUSE1(x)				(((x) & BIT_MASK_TXPAUSE1) << BIT_SHIFT_TXPAUSE1)
#define BITS_TXPAUSE1					(BIT_MASK_TXPAUSE1 << BIT_SHIFT_TXPAUSE1)
#define BIT_CLEAR_TXPAUSE1(x)				((x) & (~BITS_TXPAUSE1))
#define BIT_GET_TXPAUSE1(x)				(((x) >> BIT_SHIFT_TXPAUSE1) & BIT_MASK_TXPAUSE1)
#define BIT_SET_TXPAUSE1(x, v)				(BIT_CLEAR_TXPAUSE1(x) | BIT_TXPAUSE1(v))

#define BIT_SHIFT_BW_CFG				0
#define BIT_MASK_BW_CFG				0x3
#define BIT_BW_CFG(x)					(((x) & BIT_MASK_BW_CFG) << BIT_SHIFT_BW_CFG)
#define BITS_BW_CFG					(BIT_MASK_BW_CFG << BIT_SHIFT_BW_CFG)
#define BIT_CLEAR_BW_CFG(x)				((x) & (~BITS_BW_CFG))
#define BIT_GET_BW_CFG(x)				(((x) >> BIT_SHIFT_BW_CFG) & BIT_MASK_BW_CFG)
#define BIT_SET_BW_CFG(x, v)				(BIT_CLEAR_BW_CFG(x) | BIT_BW_CFG(v))

/* 2 REG_BCN_ELY_ADJ				(Offset 0x05D4) */

#define BIT_SHIFT_RXBCN_TIMER				16
#define BIT_MASK_RXBCN_TIMER				0xffff
#define BIT_RXBCN_TIMER(x)				(((x) & BIT_MASK_RXBCN_TIMER) << BIT_SHIFT_RXBCN_TIMER)
#define BITS_RXBCN_TIMER				(BIT_MASK_RXBCN_TIMER << BIT_SHIFT_RXBCN_TIMER)
#define BIT_CLEAR_RXBCN_TIMER(x)			((x) & (~BITS_RXBCN_TIMER))
#define BIT_GET_RXBCN_TIMER(x)				(((x) >> BIT_SHIFT_RXBCN_TIMER) & BIT_MASK_RXBCN_TIMER)
#define BIT_SET_RXBCN_TIMER(x, v)			(BIT_CLEAR_RXBCN_TIMER(x) | BIT_RXBCN_TIMER(v))

#define BIT_SHIFT_BCN_ELY_ADJ				0
#define BIT_MASK_BCN_ELY_ADJ				0xffff
#define BIT_BCN_ELY_ADJ(x)				(((x) & BIT_MASK_BCN_ELY_ADJ) << BIT_SHIFT_BCN_ELY_ADJ)
#define BITS_BCN_ELY_ADJ				(BIT_MASK_BCN_ELY_ADJ << BIT_SHIFT_BCN_ELY_ADJ)
#define BIT_CLEAR_BCN_ELY_ADJ(x)			((x) & (~BITS_BCN_ELY_ADJ))
#define BIT_GET_BCN_ELY_ADJ(x)				(((x) >> BIT_SHIFT_BCN_ELY_ADJ) & BIT_MASK_BCN_ELY_ADJ)
#define BIT_SET_BCN_ELY_ADJ(x, v)			(BIT_CLEAR_BCN_ELY_ADJ(x) | BIT_BCN_ELY_ADJ(v))

/* 2 REG_BCNERR_CNT1				(Offset 0x05D8) */

#define BIT_SHIFT_BCNERR_CNT_OTHERS			24
#define BIT_MASK_BCNERR_CNT_OTHERS			0xff
#define BIT_BCNERR_CNT_OTHERS(x)			(((x) & BIT_MASK_BCNERR_CNT_OTHERS) << BIT_SHIFT_BCNERR_CNT_OTHERS)
#define BITS_BCNERR_CNT_OTHERS				(BIT_MASK_BCNERR_CNT_OTHERS << BIT_SHIFT_BCNERR_CNT_OTHERS)
#define BIT_CLEAR_BCNERR_CNT_OTHERS(x)			((x) & (~BITS_BCNERR_CNT_OTHERS))
#define BIT_GET_BCNERR_CNT_OTHERS(x)			(((x) >> BIT_SHIFT_BCNERR_CNT_OTHERS) & BIT_MASK_BCNERR_CNT_OTHERS)
#define BIT_SET_BCNERR_CNT_OTHERS(x, v)		(BIT_CLEAR_BCNERR_CNT_OTHERS(x) | BIT_BCNERR_CNT_OTHERS(v))

#define BIT_SHIFT_BCNERR_CNT_INVALID			16
#define BIT_MASK_BCNERR_CNT_INVALID			0xff
#define BIT_BCNERR_CNT_INVALID(x)			(((x) & BIT_MASK_BCNERR_CNT_INVALID) << BIT_SHIFT_BCNERR_CNT_INVALID)
#define BITS_BCNERR_CNT_INVALID			(BIT_MASK_BCNERR_CNT_INVALID << BIT_SHIFT_BCNERR_CNT_INVALID)
#define BIT_CLEAR_BCNERR_CNT_INVALID(x)		((x) & (~BITS_BCNERR_CNT_INVALID))
#define BIT_GET_BCNERR_CNT_INVALID(x)			(((x) >> BIT_SHIFT_BCNERR_CNT_INVALID) & BIT_MASK_BCNERR_CNT_INVALID)
#define BIT_SET_BCNERR_CNT_INVALID(x, v)		(BIT_CLEAR_BCNERR_CNT_INVALID(x) | BIT_BCNERR_CNT_INVALID(v))

#define BIT_SHIFT_BCNERR_CNT_MAC			8
#define BIT_MASK_BCNERR_CNT_MAC			0xff
#define BIT_BCNERR_CNT_MAC(x)				(((x) & BIT_MASK_BCNERR_CNT_MAC) << BIT_SHIFT_BCNERR_CNT_MAC)
#define BITS_BCNERR_CNT_MAC				(BIT_MASK_BCNERR_CNT_MAC << BIT_SHIFT_BCNERR_CNT_MAC)
#define BIT_CLEAR_BCNERR_CNT_MAC(x)			((x) & (~BITS_BCNERR_CNT_MAC))
#define BIT_GET_BCNERR_CNT_MAC(x)			(((x) >> BIT_SHIFT_BCNERR_CNT_MAC) & BIT_MASK_BCNERR_CNT_MAC)
#define BIT_SET_BCNERR_CNT_MAC(x, v)			(BIT_CLEAR_BCNERR_CNT_MAC(x) | BIT_BCNERR_CNT_MAC(v))

#define BIT_SHIFT_BCNERR_CNT_CCA			0
#define BIT_MASK_BCNERR_CNT_CCA			0xff
#define BIT_BCNERR_CNT_CCA(x)				(((x) & BIT_MASK_BCNERR_CNT_CCA) << BIT_SHIFT_BCNERR_CNT_CCA)
#define BITS_BCNERR_CNT_CCA				(BIT_MASK_BCNERR_CNT_CCA << BIT_SHIFT_BCNERR_CNT_CCA)
#define BIT_CLEAR_BCNERR_CNT_CCA(x)			((x) & (~BITS_BCNERR_CNT_CCA))
#define BIT_GET_BCNERR_CNT_CCA(x)			(((x) >> BIT_SHIFT_BCNERR_CNT_CCA) & BIT_MASK_BCNERR_CNT_CCA)
#define BIT_SET_BCNERR_CNT_CCA(x, v)			(BIT_CLEAR_BCNERR_CNT_CCA(x) | BIT_BCNERR_CNT_CCA(v))

/* 2 REG_BCNERR_CNT2				(Offset 0x05DC) */

#define BIT_SHIFT_BCNERR_CNT_EDCCA			0
#define BIT_MASK_BCNERR_CNT_EDCCA			0xff
#define BIT_BCNERR_CNT_EDCCA(x)			(((x) & BIT_MASK_BCNERR_CNT_EDCCA) << BIT_SHIFT_BCNERR_CNT_EDCCA)
#define BITS_BCNERR_CNT_EDCCA				(BIT_MASK_BCNERR_CNT_EDCCA << BIT_SHIFT_BCNERR_CNT_EDCCA)
#define BIT_CLEAR_BCNERR_CNT_EDCCA(x)			((x) & (~BITS_BCNERR_CNT_EDCCA))
#define BIT_GET_BCNERR_CNT_EDCCA(x)			(((x) >> BIT_SHIFT_BCNERR_CNT_EDCCA) & BIT_MASK_BCNERR_CNT_EDCCA)
#define BIT_SET_BCNERR_CNT_EDCCA(x, v)			(BIT_CLEAR_BCNERR_CNT_EDCCA(x) | BIT_BCNERR_CNT_EDCCA(v))

/* 2 REG_NOA_PARAM				(Offset 0x05E0) */

#define BIT_SHIFT_NOA_DURATION_V1			0
#define BIT_MASK_NOA_DURATION_V1			0xffffffffL
#define BIT_NOA_DURATION_V1(x)				(((x) & BIT_MASK_NOA_DURATION_V1) << BIT_SHIFT_NOA_DURATION_V1)
#define BITS_NOA_DURATION_V1				(BIT_MASK_NOA_DURATION_V1 << BIT_SHIFT_NOA_DURATION_V1)
#define BIT_CLEAR_NOA_DURATION_V1(x)			((x) & (~BITS_NOA_DURATION_V1))
#define BIT_GET_NOA_DURATION_V1(x)			(((x) >> BIT_SHIFT_NOA_DURATION_V1) & BIT_MASK_NOA_DURATION_V1)
#define BIT_SET_NOA_DURATION_V1(x, v)			(BIT_CLEAR_NOA_DURATION_V1(x) | BIT_NOA_DURATION_V1(v))

/* 2 REG_NOA_PARAM_1				(Offset 0x05E4) */

#define BIT_SHIFT_NOA_INTERVAL_V1			0
#define BIT_MASK_NOA_INTERVAL_V1			0xffffffffL
#define BIT_NOA_INTERVAL_V1(x)				(((x) & BIT_MASK_NOA_INTERVAL_V1) << BIT_SHIFT_NOA_INTERVAL_V1)
#define BITS_NOA_INTERVAL_V1				(BIT_MASK_NOA_INTERVAL_V1 << BIT_SHIFT_NOA_INTERVAL_V1)
#define BIT_CLEAR_NOA_INTERVAL_V1(x)			((x) & (~BITS_NOA_INTERVAL_V1))
#define BIT_GET_NOA_INTERVAL_V1(x)			(((x) >> BIT_SHIFT_NOA_INTERVAL_V1) & BIT_MASK_NOA_INTERVAL_V1)
#define BIT_SET_NOA_INTERVAL_V1(x, v)			(BIT_CLEAR_NOA_INTERVAL_V1(x) | BIT_NOA_INTERVAL_V1(v))

/* 2 REG_NOA_PARAM_2				(Offset 0x05E8) */

#define BIT_SHIFT_NOA_START_TIME_V1			0
#define BIT_MASK_NOA_START_TIME_V1			0xffffffffL
#define BIT_NOA_START_TIME_V1(x)			(((x) & BIT_MASK_NOA_START_TIME_V1) << BIT_SHIFT_NOA_START_TIME_V1)
#define BITS_NOA_START_TIME_V1				(BIT_MASK_NOA_START_TIME_V1 << BIT_SHIFT_NOA_START_TIME_V1)
#define BIT_CLEAR_NOA_START_TIME_V1(x)			((x) & (~BITS_NOA_START_TIME_V1))
#define BIT_GET_NOA_START_TIME_V1(x)			(((x) >> BIT_SHIFT_NOA_START_TIME_V1) & BIT_MASK_NOA_START_TIME_V1)
#define BIT_SET_NOA_START_TIME_V1(x, v)		(BIT_CLEAR_NOA_START_TIME_V1(x) | BIT_NOA_START_TIME_V1(v))

/* 2 REG_NOA_PARAM_3				(Offset 0x05EC) */

#define BIT_SHIFT_NOA_COUNT_V3				0
#define BIT_MASK_NOA_COUNT_V3				0xff
#define BIT_NOA_COUNT_V3(x)				(((x) & BIT_MASK_NOA_COUNT_V3) << BIT_SHIFT_NOA_COUNT_V3)
#define BITS_NOA_COUNT_V3				(BIT_MASK_NOA_COUNT_V3 << BIT_SHIFT_NOA_COUNT_V3)
#define BIT_CLEAR_NOA_COUNT_V3(x)			((x) & (~BITS_NOA_COUNT_V3))
#define BIT_GET_NOA_COUNT_V3(x)			(((x) >> BIT_SHIFT_NOA_COUNT_V3) & BIT_MASK_NOA_COUNT_V3)
#define BIT_SET_NOA_COUNT_V3(x, v)			(BIT_CLEAR_NOA_COUNT_V3(x) | BIT_NOA_COUNT_V3(v))

/* 2 REG_P2P_RST				(Offset 0x05F0) */

#define BIT_P2P2_PWR_RST1				BIT(5)
#define BIT_P2P2_PWR_RST0				BIT(4)
#define BIT_P2P1_PWR_RST1				BIT(3)
#define BIT_P2P1_PWR_RST0				BIT(2)
#define BIT_P2P_PWR_RST1_V1				BIT(1)
#define BIT_P2P_PWR_RST0_V1				BIT(0)

/* 2 REG_SCHEDULER_RST			(Offset 0x05F1) */

#define BIT_SYNC_CLI_ONCE_RIGHT_NOW			BIT(2)
#define BIT_SYNC_CLI_ONCE_BY_TBTT			BIT(1)
#define BIT_SCHEDULER_RST_V1				BIT(0)

/* 2 REG_SCHEDULER_DBG			(Offset 0x05F4) */

#define BIT_SHIFT_DBG_SCHEDULER			0
#define BIT_MASK_DBG_SCHEDULER				0xffffffffL
#define BIT_DBG_SCHEDULER(x)				(((x) & BIT_MASK_DBG_SCHEDULER) << BIT_SHIFT_DBG_SCHEDULER)
#define BITS_DBG_SCHEDULER				(BIT_MASK_DBG_SCHEDULER << BIT_SHIFT_DBG_SCHEDULER)
#define BIT_CLEAR_DBG_SCHEDULER(x)			((x) & (~BITS_DBG_SCHEDULER))
#define BIT_GET_DBG_SCHEDULER(x)			(((x) >> BIT_SHIFT_DBG_SCHEDULER) & BIT_MASK_DBG_SCHEDULER)
#define BIT_SET_DBG_SCHEDULER(x, v)			(BIT_CLEAR_DBG_SCHEDULER(x) | BIT_DBG_SCHEDULER(v))

/* 2 REG_SCH_TXCMD				(Offset 0x05F8) */

#define BIT_SHIFT_SCH_TXCMD				0
#define BIT_MASK_SCH_TXCMD				0xffffffffL
#define BIT_SCH_TXCMD(x)				(((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD)
#define BITS_SCH_TXCMD					(BIT_MASK_SCH_TXCMD << BIT_SHIFT_SCH_TXCMD)
#define BIT_CLEAR_SCH_TXCMD(x)				((x) & (~BITS_SCH_TXCMD))
#define BIT_GET_SCH_TXCMD(x)				(((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD)
#define BIT_SET_SCH_TXCMD(x, v)			(BIT_CLEAR_SCH_TXCMD(x) | BIT_SCH_TXCMD(v))

/* 2 REG_WMAC_CR				(Offset 0x0600) */

#define BIT_APSDOFF					BIT(6)
#define BIT_IC_MACPHY_M				BIT(0)

/* 2 REG_FWPKT_CR				(Offset 0x0601) */

#define BIT_FWRX_EN					BIT(7)
#define BIT_PHYSTS_PKT_CTRL				BIT(6)
#define BIT_APPHDR_MIDSRCH_FAIL			BIT(4)
#define BIT_FWPARSING_EN				BIT(3)

#define BIT_SHIFT_APPEND_MHDR_LEN			0
#define BIT_MASK_APPEND_MHDR_LEN			0x7
#define BIT_APPEND_MHDR_LEN(x)				(((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN)
#define BITS_APPEND_MHDR_LEN				(BIT_MASK_APPEND_MHDR_LEN << BIT_SHIFT_APPEND_MHDR_LEN)
#define BIT_CLEAR_APPEND_MHDR_LEN(x)			((x) & (~BITS_APPEND_MHDR_LEN))
#define BIT_GET_APPEND_MHDR_LEN(x)			(((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN)
#define BIT_SET_APPEND_MHDR_LEN(x, v)			(BIT_CLEAR_APPEND_MHDR_LEN(x) | BIT_APPEND_MHDR_LEN(v))

/* 2 REG_FWPKT_CR_EXT			(Offset 0x0602) */

#define BIT_DATA_FW_STS_FILTER				BIT(2)
#define BIT_CTRL_FW_STS_FILTER				BIT(1)
#define BIT_MGNT_FW_STS_FILTER				BIT(0)

/* 2 REG_WMAC_BWOPMODE			(Offset 0x0603) */

#define BIT_WMAC_20MHZBW				BIT(2)
#define BIT_WMAC_M11J					BIT(0)

/* 2 REG_TCR					(Offset 0x0604) */

#define BIT_WMAC_EN_RTS_ADDR				BIT(31)
#define BIT_WMAC_DISABLE_CCK				BIT(30)
#define BIT_WMAC_RAW_LEN				BIT(29)
#define BIT_WMAC_NOTX_IN_RXNDP				BIT(28)
#define BIT_WMAC_EN_EOF				BIT(27)
#define BIT_WMAC_BF_SEL				BIT(26)
#define BIT_WMAC_ANTMODE_SEL				BIT(25)
#define BIT_WMAC_TCRPWRMGT_HWCTL			BIT(24)
#define BIT_WMAC_SMOOTH_VAL				BIT(23)
#define BIT_WMAC_EN_SCRAM_INC				BIT(22)
#define BIT_UNDERFLOWEN_CMPLEN_SEL			BIT(21)
#define BIT_FETCH_MPDU_AFTER_WSECRDY			BIT(20)
#define BIT_WMAC_TCR_EN_20MST				BIT(19)
#define BIT_WMAC_DIS_SIGTA				BIT(18)
#define BIT_WMAC_DIS_A2B0				BIT(17)
#define BIT_WMAC_MSK_SIGBCRC				BIT(16)
#define BIT_WMAC_TCR_ERRSTEN_3				BIT(15)
#define BIT_WMAC_TCR_ERRSTEN_2				BIT(14)
#define BIT_WMAC_TCR_ERRSTEN_1				BIT(13)
#define BIT_WMAC_TCR_ERRSTEN_0				BIT(12)
#define BIT_WMAC_TCR_TXSK_PERPKT			BIT(11)
#define BIT_WMAC_TCR_ICV				BIT(10)
#define BIT_WMAC_CFENDFOR				BIT(9)
#define BIT_WMAC_TCR_CRC				BIT(8)
#define BIT_WMAC_TCR_PWRMGT_CTL			BIT(7)
#define BIT_WMAC_TCR_PWRMGT_VAL			BIT(6)
#define BIT_WMAC_TCR_UPD_TIMIE				BIT(5)
#define BIT_WMAC_TCR_UPD_HGQMD				BIT(4)
#define BIT_WMAC_TCR_VHTSIGA1_TXPS			BIT(3)
#define BIT_WMAC_TCR_PADSEL				BIT(2)
#define BIT_WMAC_TCR_DISGCLK				BIT(1)

/* 2 REG_RCR					(Offset 0x0608) */

#define BIT_APP_FCS					BIT(31)
#define BIT_APP_MIC					BIT(30)
#define BIT_APP_ICV					BIT(29)
#define BIT_APP_PHYSTS					BIT(28)
#define BIT_APP_BASSN					BIT(27)
#define BIT_VHT_DACK					BIT(26)
#define BIT_TCPOFLD_EN					BIT(25)
#define BIT_ENMBID					BIT(24)
#define BIT_LSIGEN					BIT(23)
#define BIT_MFBEN					BIT(22)
#define BIT_DISCHKPPDLLEN				BIT(21)
#define BIT_PKTCTL_DLKEN				BIT(20)
#define BIT_DISGCLK					BIT(19)
#define BIT_TIMPSR_EN					BIT(18)
#define BIT_BCMDINT_EN					BIT(17)
#define BIT_UCMDINT_EN					BIT(16)
#define BIT_RXSK_PERPKT				BIT(15)
#define BIT_HTCBFMC					BIT(14)
#define BIT_CHK_PREVTXA2				BIT(13)
#define BIT_ACK_CBSSID					BIT(12)
#define BIT_CHKTA_MGNT					BIT(11)
#define BIT_DISDECNMYPKT				BIT(10)
#define BIT_AICV					BIT(9)
#define BIT_ACRC32					BIT(8)
#define BIT_CBSSID_MGNT				BIT(7)
#define BIT_CBSSID_DATA				BIT(6)
#define BIT_APWRMGT					BIT(5)
#define BIT_ADD3					BIT(4)
#define BIT_AB						BIT(3)
#define BIT_AM						BIT(2)
#define BIT_APM					BIT(1)
#define BIT_AAP					BIT(0)

/* 2 REG_RX_PKT_LIMIT			(Offset 0x060C) */

#define BIT_SHIFT_RXPKTLMT				0
#define BIT_MASK_RXPKTLMT				0x3f
#define BIT_RXPKTLMT(x)				(((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT)
#define BITS_RXPKTLMT					(BIT_MASK_RXPKTLMT << BIT_SHIFT_RXPKTLMT)
#define BIT_CLEAR_RXPKTLMT(x)				((x) & (~BITS_RXPKTLMT))
#define BIT_GET_RXPKTLMT(x)				(((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT)
#define BIT_SET_RXPKTLMT(x, v)				(BIT_CLEAR_RXPKTLMT(x) | BIT_RXPKTLMT(v))

#define BIT_SHIFT_RX_DLK_TIME				0
#define BIT_MASK_RX_DLK_TIME				0xff
#define BIT_RX_DLK_TIME(x)				(((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME)
#define BITS_RX_DLK_TIME				(BIT_MASK_RX_DLK_TIME << BIT_SHIFT_RX_DLK_TIME)
#define BIT_CLEAR_RX_DLK_TIME(x)			((x) & (~BITS_RX_DLK_TIME))
#define BIT_GET_RX_DLK_TIME(x)				(((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME)
#define BIT_SET_RX_DLK_TIME(x, v)			(BIT_CLEAR_RX_DLK_TIME(x) | BIT_RX_DLK_TIME(v))

/* 2 REG_MBIDCTRL				(Offset 0x060E) */

#define BIT_MBID_EN					BIT(7)

#define BIT_SHIFT_MBID_BCNNO				4
#define BIT_MASK_MBID_BCNNO				0x7
#define BIT_MBID_BCNNO(x)				(((x) & BIT_MASK_MBID_BCNNO) << BIT_SHIFT_MBID_BCNNO)
#define BITS_MBID_BCNNO				(BIT_MASK_MBID_BCNNO << BIT_SHIFT_MBID_BCNNO)
#define BIT_CLEAR_MBID_BCNNO(x)			((x) & (~BITS_MBID_BCNNO))
#define BIT_GET_MBID_BCNNO(x)				(((x) >> BIT_SHIFT_MBID_BCNNO) & BIT_MASK_MBID_BCNNO)
#define BIT_SET_MBID_BCNNO(x, v)			(BIT_CLEAR_MBID_BCNNO(x) | BIT_MBID_BCNNO(v))

/* 2 REG_RX_DRVINFO_SZ			(Offset 0x060F) */

#define BIT_APP_PHYSTS_PER_SUBMPDU			BIT(7)
#define BIT_APP_MH_SHIFT_VAL				BIT(6)
#define BIT_WMAC_ENSHIFT				BIT(5)

#define BIT_SHIFT_RX_DRVINFO_SZ			0
#define BIT_MASK_RX_DRVINFO_SZ				0xf
#define BIT_RX_DRVINFO_SZ(x)				(((x) & BIT_MASK_RX_DRVINFO_SZ) << BIT_SHIFT_RX_DRVINFO_SZ)
#define BITS_RX_DRVINFO_SZ				(BIT_MASK_RX_DRVINFO_SZ << BIT_SHIFT_RX_DRVINFO_SZ)
#define BIT_CLEAR_RX_DRVINFO_SZ(x)			((x) & (~BITS_RX_DRVINFO_SZ))
#define BIT_GET_RX_DRVINFO_SZ(x)			(((x) >> BIT_SHIFT_RX_DRVINFO_SZ) & BIT_MASK_RX_DRVINFO_SZ)
#define BIT_SET_RX_DRVINFO_SZ(x, v)			(BIT_CLEAR_RX_DRVINFO_SZ(x) | BIT_RX_DRVINFO_SZ(v))

/* 2 REG_MACID				(Offset 0x0610) */

#define BIT_SHIFT_MACID_V1				0
#define BIT_MASK_MACID_V1				0xffffffffL
#define BIT_MACID_V1(x)				(((x) & BIT_MASK_MACID_V1) << BIT_SHIFT_MACID_V1)
#define BITS_MACID_V1					(BIT_MASK_MACID_V1 << BIT_SHIFT_MACID_V1)
#define BIT_CLEAR_MACID_V1(x)				((x) & (~BITS_MACID_V1))
#define BIT_GET_MACID_V1(x)				(((x) >> BIT_SHIFT_MACID_V1) & BIT_MASK_MACID_V1)
#define BIT_SET_MACID_V1(x, v)				(BIT_CLEAR_MACID_V1(x) | BIT_MACID_V1(v))

/* 2 REG_MACID_H				(Offset 0x0614) */

#define BIT_AP_BSSID_FIT_UC				BIT(21)
#define BIT_EN_PORT4					BIT(20)
#define BIT_EN_PORT3					BIT(19)
#define BIT_EN_PORT2					BIT(18)
#define BIT_EN_PORT1					BIT(17)
#define BIT_EN_PORT0					BIT(16)

#define BIT_SHIFT_MACID_H				0
#define BIT_MASK_MACID_H				0xffff
#define BIT_MACID_H(x)					(((x) & BIT_MASK_MACID_H) << BIT_SHIFT_MACID_H)
#define BITS_MACID_H					(BIT_MASK_MACID_H << BIT_SHIFT_MACID_H)
#define BIT_CLEAR_MACID_H(x)				((x) & (~BITS_MACID_H))
#define BIT_GET_MACID_H(x)				(((x) >> BIT_SHIFT_MACID_H) & BIT_MASK_MACID_H)
#define BIT_SET_MACID_H(x, v)				(BIT_CLEAR_MACID_H(x) | BIT_MACID_H(v))

/* 2 REG_BSSID				(Offset 0x0618) */

#define BIT_SHIFT_BSSID_V1				0
#define BIT_MASK_BSSID_V1				0xffffffffL
#define BIT_BSSID_V1(x)				(((x) & BIT_MASK_BSSID_V1) << BIT_SHIFT_BSSID_V1)
#define BITS_BSSID_V1					(BIT_MASK_BSSID_V1 << BIT_SHIFT_BSSID_V1)
#define BIT_CLEAR_BSSID_V1(x)				((x) & (~BITS_BSSID_V1))
#define BIT_GET_BSSID_V1(x)				(((x) >> BIT_SHIFT_BSSID_V1) & BIT_MASK_BSSID_V1)
#define BIT_SET_BSSID_V1(x, v)				(BIT_CLEAR_BSSID_V1(x) | BIT_BSSID_V1(v))

/* 2 REG_BSSID_H				(Offset 0x061C) */

#define BIT_SHIFT_BSSID_H				0
#define BIT_MASK_BSSID_H				0xffff
#define BIT_BSSID_H(x)					(((x) & BIT_MASK_BSSID_H) << BIT_SHIFT_BSSID_H)
#define BITS_BSSID_H					(BIT_MASK_BSSID_H << BIT_SHIFT_BSSID_H)
#define BIT_CLEAR_BSSID_H(x)				((x) & (~BITS_BSSID_H))
#define BIT_GET_BSSID_H(x)				(((x) >> BIT_SHIFT_BSSID_H) & BIT_MASK_BSSID_H)
#define BIT_SET_BSSID_H(x, v)				(BIT_CLEAR_BSSID_H(x) | BIT_BSSID_H(v))

/* 2 REG_MAR					(Offset 0x0620) */

#define BIT_SHIFT_MAR_V1				0
#define BIT_MASK_MAR_V1				0xffffffffL
#define BIT_MAR_V1(x)					(((x) & BIT_MASK_MAR_V1) << BIT_SHIFT_MAR_V1)
#define BITS_MAR_V1					(BIT_MASK_MAR_V1 << BIT_SHIFT_MAR_V1)
#define BIT_CLEAR_MAR_V1(x)				((x) & (~BITS_MAR_V1))
#define BIT_GET_MAR_V1(x)				(((x) >> BIT_SHIFT_MAR_V1) & BIT_MASK_MAR_V1)
#define BIT_SET_MAR_V1(x, v)				(BIT_CLEAR_MAR_V1(x) | BIT_MAR_V1(v))

/* 2 REG_MAR_H				(Offset 0x0624) */

#define BIT_SHIFT_MAR_H				0
#define BIT_MASK_MAR_H					0xffffffffL
#define BIT_MAR_H(x)					(((x) & BIT_MASK_MAR_H) << BIT_SHIFT_MAR_H)
#define BITS_MAR_H					(BIT_MASK_MAR_H << BIT_SHIFT_MAR_H)
#define BIT_CLEAR_MAR_H(x)				((x) & (~BITS_MAR_H))
#define BIT_GET_MAR_H(x)				(((x) >> BIT_SHIFT_MAR_H) & BIT_MASK_MAR_H)
#define BIT_SET_MAR_H(x, v)				(BIT_CLEAR_MAR_H(x) | BIT_MAR_H(v))

/* 2 REG_MBIDCAMCFG_1			(Offset 0x0628) */

#define BIT_SHIFT_MBIDCAM_WDATA_L			0
#define BIT_MASK_MBIDCAM_WDATA_L			0xffffffffL
#define BIT_MBIDCAM_WDATA_L(x)				(((x) & BIT_MASK_MBIDCAM_WDATA_L) << BIT_SHIFT_MBIDCAM_WDATA_L)
#define BITS_MBIDCAM_WDATA_L				(BIT_MASK_MBIDCAM_WDATA_L << BIT_SHIFT_MBIDCAM_WDATA_L)
#define BIT_CLEAR_MBIDCAM_WDATA_L(x)			((x) & (~BITS_MBIDCAM_WDATA_L))
#define BIT_GET_MBIDCAM_WDATA_L(x)			(((x) >> BIT_SHIFT_MBIDCAM_WDATA_L) & BIT_MASK_MBIDCAM_WDATA_L)
#define BIT_SET_MBIDCAM_WDATA_L(x, v)			(BIT_CLEAR_MBIDCAM_WDATA_L(x) | BIT_MBIDCAM_WDATA_L(v))

/* 2 REG_MBIDCAMCFG_2			(Offset 0x062C) */

#define BIT_MBIDCAM_POLL				BIT(31)
#define BIT_MBIDCAM_WT_EN				BIT(30)
#define BIT_MBIDCAM_DA_EN				BIT(29)

#define BIT_SHIFT_MBIDCAM_ADDR_V1			24
#define BIT_MASK_MBIDCAM_ADDR_V1			0x1f
#define BIT_MBIDCAM_ADDR_V1(x)				(((x) & BIT_MASK_MBIDCAM_ADDR_V1) << BIT_SHIFT_MBIDCAM_ADDR_V1)
#define BITS_MBIDCAM_ADDR_V1				(BIT_MASK_MBIDCAM_ADDR_V1 << BIT_SHIFT_MBIDCAM_ADDR_V1)
#define BIT_CLEAR_MBIDCAM_ADDR_V1(x)			((x) & (~BITS_MBIDCAM_ADDR_V1))
#define BIT_GET_MBIDCAM_ADDR_V1(x)			(((x) >> BIT_SHIFT_MBIDCAM_ADDR_V1) & BIT_MASK_MBIDCAM_ADDR_V1)
#define BIT_SET_MBIDCAM_ADDR_V1(x, v)			(BIT_CLEAR_MBIDCAM_ADDR_V1(x) | BIT_MBIDCAM_ADDR_V1(v))

#define BIT_MBIDCAM_VALID				BIT(23)
#define BIT_LSIC_TXOP_EN				BIT(17)
#define BIT_CTS_EN					BIT(16)

#define BIT_SHIFT_MBIDCAM_RWDATA_H			0
#define BIT_MASK_MBIDCAM_RWDATA_H			0xffff
#define BIT_MBIDCAM_RWDATA_H(x)			(((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H)
#define BITS_MBIDCAM_RWDATA_H				(BIT_MASK_MBIDCAM_RWDATA_H << BIT_SHIFT_MBIDCAM_RWDATA_H)
#define BIT_CLEAR_MBIDCAM_RWDATA_H(x)			((x) & (~BITS_MBIDCAM_RWDATA_H))
#define BIT_GET_MBIDCAM_RWDATA_H(x)			(((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H)
#define BIT_SET_MBIDCAM_RWDATA_H(x, v)			(BIT_CLEAR_MBIDCAM_RWDATA_H(x) | BIT_MBIDCAM_RWDATA_H(v))

/* 2 REG_WMAC_TCR_TSFT_OFS			(Offset 0x0630) */

#define BIT_SHIFT_WMAC_TCR_TSFT_OFS			0
#define BIT_MASK_WMAC_TCR_TSFT_OFS			0xffff
#define BIT_WMAC_TCR_TSFT_OFS(x)			(((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS)
#define BITS_WMAC_TCR_TSFT_OFS				(BIT_MASK_WMAC_TCR_TSFT_OFS << BIT_SHIFT_WMAC_TCR_TSFT_OFS)
#define BIT_CLEAR_WMAC_TCR_TSFT_OFS(x)			((x) & (~BITS_WMAC_TCR_TSFT_OFS))
#define BIT_GET_WMAC_TCR_TSFT_OFS(x)			(((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS)
#define BIT_SET_WMAC_TCR_TSFT_OFS(x, v)		(BIT_CLEAR_WMAC_TCR_TSFT_OFS(x) | BIT_WMAC_TCR_TSFT_OFS(v))

/* 2 REG_UDF_THSD				(Offset 0x0632) */

#define BIT_UDF_THSD_V1				BIT(7)

#define BIT_SHIFT_UDF_THSD_VALUE			0
#define BIT_MASK_UDF_THSD_VALUE			0x7f
#define BIT_UDF_THSD_VALUE(x)				(((x) & BIT_MASK_UDF_THSD_VALUE) << BIT_SHIFT_UDF_THSD_VALUE)
#define BITS_UDF_THSD_VALUE				(BIT_MASK_UDF_THSD_VALUE << BIT_SHIFT_UDF_THSD_VALUE)
#define BIT_CLEAR_UDF_THSD_VALUE(x)			((x) & (~BITS_UDF_THSD_VALUE))
#define BIT_GET_UDF_THSD_VALUE(x)			(((x) >> BIT_SHIFT_UDF_THSD_VALUE) & BIT_MASK_UDF_THSD_VALUE)
#define BIT_SET_UDF_THSD_VALUE(x, v)			(BIT_CLEAR_UDF_THSD_VALUE(x) | BIT_UDF_THSD_VALUE(v))

/* 2 REG_ZLD_NUM				(Offset 0x0633) */

#define BIT_SHIFT_ZLD_NUM				0
#define BIT_MASK_ZLD_NUM				0xff
#define BIT_ZLD_NUM(x)					(((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM)
#define BITS_ZLD_NUM					(BIT_MASK_ZLD_NUM << BIT_SHIFT_ZLD_NUM)
#define BIT_CLEAR_ZLD_NUM(x)				((x) & (~BITS_ZLD_NUM))
#define BIT_GET_ZLD_NUM(x)				(((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM)
#define BIT_SET_ZLD_NUM(x, v)				(BIT_CLEAR_ZLD_NUM(x) | BIT_ZLD_NUM(v))

/* 2 REG_STMP_THSD				(Offset 0x0634) */

#define BIT_SHIFT_STMP_THSD				0
#define BIT_MASK_STMP_THSD				0xff
#define BIT_STMP_THSD(x)				(((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD)
#define BITS_STMP_THSD					(BIT_MASK_STMP_THSD << BIT_SHIFT_STMP_THSD)
#define BIT_CLEAR_STMP_THSD(x)				((x) & (~BITS_STMP_THSD))
#define BIT_GET_STMP_THSD(x)				(((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD)
#define BIT_SET_STMP_THSD(x, v)			(BIT_CLEAR_STMP_THSD(x) | BIT_STMP_THSD(v))

/* 2 REG_WMAC_TXTIMEOUT			(Offset 0x0635) */

#define BIT_SHIFT_WMAC_TXTIMEOUT			0
#define BIT_MASK_WMAC_TXTIMEOUT			0xff
#define BIT_WMAC_TXTIMEOUT(x)				(((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT)
#define BITS_WMAC_TXTIMEOUT				(BIT_MASK_WMAC_TXTIMEOUT << BIT_SHIFT_WMAC_TXTIMEOUT)
#define BIT_CLEAR_WMAC_TXTIMEOUT(x)			((x) & (~BITS_WMAC_TXTIMEOUT))
#define BIT_GET_WMAC_TXTIMEOUT(x)			(((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT)
#define BIT_SET_WMAC_TXTIMEOUT(x, v)			(BIT_CLEAR_WMAC_TXTIMEOUT(x) | BIT_WMAC_TXTIMEOUT(v))

/* 2 REG_USTIME_EDCA				(Offset 0x0638) */

#define BIT_SHIFT_USTIME_EDCA				0
#define BIT_MASK_USTIME_EDCA				0xff
#define BIT_USTIME_EDCA(x)				(((x) & BIT_MASK_USTIME_EDCA) << BIT_SHIFT_USTIME_EDCA)
#define BITS_USTIME_EDCA				(BIT_MASK_USTIME_EDCA << BIT_SHIFT_USTIME_EDCA)
#define BIT_CLEAR_USTIME_EDCA(x)			((x) & (~BITS_USTIME_EDCA))
#define BIT_GET_USTIME_EDCA(x)				(((x) >> BIT_SHIFT_USTIME_EDCA) & BIT_MASK_USTIME_EDCA)
#define BIT_SET_USTIME_EDCA(x, v)			(BIT_CLEAR_USTIME_EDCA(x) | BIT_USTIME_EDCA(v))

/* 2 REG_ACKTO_CCK				(Offset 0x0639) */

#define BIT_SHIFT_ACKTO_CCK				0
#define BIT_MASK_ACKTO_CCK				0xff
#define BIT_ACKTO_CCK(x)				(((x) & BIT_MASK_ACKTO_CCK) << BIT_SHIFT_ACKTO_CCK)
#define BITS_ACKTO_CCK					(BIT_MASK_ACKTO_CCK << BIT_SHIFT_ACKTO_CCK)
#define BIT_CLEAR_ACKTO_CCK(x)				((x) & (~BITS_ACKTO_CCK))
#define BIT_GET_ACKTO_CCK(x)				(((x) >> BIT_SHIFT_ACKTO_CCK) & BIT_MASK_ACKTO_CCK)
#define BIT_SET_ACKTO_CCK(x, v)			(BIT_CLEAR_ACKTO_CCK(x) | BIT_ACKTO_CCK(v))

/* 2 REG_MAC_SPEC_SIFS			(Offset 0x063A) */

#define BIT_SHIFT_SPEC_SIFS_OFDM			8
#define BIT_MASK_SPEC_SIFS_OFDM			0xff
#define BIT_SPEC_SIFS_OFDM(x)				(((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM)
#define BITS_SPEC_SIFS_OFDM				(BIT_MASK_SPEC_SIFS_OFDM << BIT_SHIFT_SPEC_SIFS_OFDM)
#define BIT_CLEAR_SPEC_SIFS_OFDM(x)			((x) & (~BITS_SPEC_SIFS_OFDM))
#define BIT_GET_SPEC_SIFS_OFDM(x)			(((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM)
#define BIT_SET_SPEC_SIFS_OFDM(x, v)			(BIT_CLEAR_SPEC_SIFS_OFDM(x) | BIT_SPEC_SIFS_OFDM(v))

#define BIT_SHIFT_SPEC_SIFS_CCK			0
#define BIT_MASK_SPEC_SIFS_CCK				0xff
#define BIT_SPEC_SIFS_CCK(x)				(((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK)
#define BITS_SPEC_SIFS_CCK				(BIT_MASK_SPEC_SIFS_CCK << BIT_SHIFT_SPEC_SIFS_CCK)
#define BIT_CLEAR_SPEC_SIFS_CCK(x)			((x) & (~BITS_SPEC_SIFS_CCK))
#define BIT_GET_SPEC_SIFS_CCK(x)			(((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK)
#define BIT_SET_SPEC_SIFS_CCK(x, v)			(BIT_CLEAR_SPEC_SIFS_CCK(x) | BIT_SPEC_SIFS_CCK(v))

/* 2 REG_RESP_SIFS_CCK			(Offset 0x063C) */

#define BIT_SHIFT_R2T_SIFS_CCK				8
#define BIT_MASK_R2T_SIFS_CCK				0xff
#define BIT_R2T_SIFS_CCK(x)				(((x) & BIT_MASK_R2T_SIFS_CCK) << BIT_SHIFT_R2T_SIFS_CCK)
#define BITS_R2T_SIFS_CCK				(BIT_MASK_R2T_SIFS_CCK << BIT_SHIFT_R2T_SIFS_CCK)
#define BIT_CLEAR_R2T_SIFS_CCK(x)			((x) & (~BITS_R2T_SIFS_CCK))
#define BIT_GET_R2T_SIFS_CCK(x)			(((x) >> BIT_SHIFT_R2T_SIFS_CCK) & BIT_MASK_R2T_SIFS_CCK)
#define BIT_SET_R2T_SIFS_CCK(x, v)			(BIT_CLEAR_R2T_SIFS_CCK(x) | BIT_R2T_SIFS_CCK(v))

#define BIT_SHIFT_T2T_SIFS_CCK				0
#define BIT_MASK_T2T_SIFS_CCK				0xff
#define BIT_T2T_SIFS_CCK(x)				(((x) & BIT_MASK_T2T_SIFS_CCK) << BIT_SHIFT_T2T_SIFS_CCK)
#define BITS_T2T_SIFS_CCK				(BIT_MASK_T2T_SIFS_CCK << BIT_SHIFT_T2T_SIFS_CCK)
#define BIT_CLEAR_T2T_SIFS_CCK(x)			((x) & (~BITS_T2T_SIFS_CCK))
#define BIT_GET_T2T_SIFS_CCK(x)			(((x) >> BIT_SHIFT_T2T_SIFS_CCK) & BIT_MASK_T2T_SIFS_CCK)
#define BIT_SET_T2T_SIFS_CCK(x, v)			(BIT_CLEAR_T2T_SIFS_CCK(x) | BIT_T2T_SIFS_CCK(v))

/* 2 REG_RESP_SIFS_OFDM			(Offset 0x063E) */

#define BIT_SHIFT_R2T_SIFS_OFDM			8
#define BIT_MASK_R2T_SIFS_OFDM				0xff
#define BIT_R2T_SIFS_OFDM(x)				(((x) & BIT_MASK_R2T_SIFS_OFDM) << BIT_SHIFT_R2T_SIFS_OFDM)
#define BITS_R2T_SIFS_OFDM				(BIT_MASK_R2T_SIFS_OFDM << BIT_SHIFT_R2T_SIFS_OFDM)
#define BIT_CLEAR_R2T_SIFS_OFDM(x)			((x) & (~BITS_R2T_SIFS_OFDM))
#define BIT_GET_R2T_SIFS_OFDM(x)			(((x) >> BIT_SHIFT_R2T_SIFS_OFDM) & BIT_MASK_R2T_SIFS_OFDM)
#define BIT_SET_R2T_SIFS_OFDM(x, v)			(BIT_CLEAR_R2T_SIFS_OFDM(x) | BIT_R2T_SIFS_OFDM(v))

#define BIT_SHIFT_T2T_SIFS_OFDM			0
#define BIT_MASK_T2T_SIFS_OFDM				0xff
#define BIT_T2T_SIFS_OFDM(x)				(((x) & BIT_MASK_T2T_SIFS_OFDM) << BIT_SHIFT_T2T_SIFS_OFDM)
#define BITS_T2T_SIFS_OFDM				(BIT_MASK_T2T_SIFS_OFDM << BIT_SHIFT_T2T_SIFS_OFDM)
#define BIT_CLEAR_T2T_SIFS_OFDM(x)			((x) & (~BITS_T2T_SIFS_OFDM))
#define BIT_GET_T2T_SIFS_OFDM(x)			(((x) >> BIT_SHIFT_T2T_SIFS_OFDM) & BIT_MASK_T2T_SIFS_OFDM)
#define BIT_SET_T2T_SIFS_OFDM(x, v)			(BIT_CLEAR_T2T_SIFS_OFDM(x) | BIT_T2T_SIFS_OFDM(v))

/* 2 REG_ACKTO				(Offset 0x0640) */

#define BIT_SHIFT_ACKTO				0
#define BIT_MASK_ACKTO					0xff
#define BIT_ACKTO(x)					(((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO)
#define BITS_ACKTO					(BIT_MASK_ACKTO << BIT_SHIFT_ACKTO)
#define BIT_CLEAR_ACKTO(x)				((x) & (~BITS_ACKTO))
#define BIT_GET_ACKTO(x)				(((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO)
#define BIT_SET_ACKTO(x, v)				(BIT_CLEAR_ACKTO(x) | BIT_ACKTO(v))

/* 2 REG_CTS2TO				(Offset 0x0641) */

#define BIT_SHIFT_CTS2TO				0
#define BIT_MASK_CTS2TO				0xff
#define BIT_CTS2TO(x)					(((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO)
#define BITS_CTS2TO					(BIT_MASK_CTS2TO << BIT_SHIFT_CTS2TO)
#define BIT_CLEAR_CTS2TO(x)				((x) & (~BITS_CTS2TO))
#define BIT_GET_CTS2TO(x)				(((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO)
#define BIT_SET_CTS2TO(x, v)				(BIT_CLEAR_CTS2TO(x) | BIT_CTS2TO(v))

/* 2 REG_EIFS				(Offset 0x0642) */

#define BIT_SHIFT_EIFS					0
#define BIT_MASK_EIFS					0xffff
#define BIT_EIFS(x)					(((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS)
#define BITS_EIFS					(BIT_MASK_EIFS << BIT_SHIFT_EIFS)
#define BIT_CLEAR_EIFS(x)				((x) & (~BITS_EIFS))
#define BIT_GET_EIFS(x)				(((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS)
#define BIT_SET_EIFS(x, v)				(BIT_CLEAR_EIFS(x) | BIT_EIFS(v))

/* 2 REG_RPFM_MAP				(Offset 0x0644) */

#define BIT_SHIFT_PRFM_MAP1				16
#define BIT_MASK_PRFM_MAP1				0xffff
#define BIT_PRFM_MAP1(x)				(((x) & BIT_MASK_PRFM_MAP1) << BIT_SHIFT_PRFM_MAP1)
#define BITS_PRFM_MAP1					(BIT_MASK_PRFM_MAP1 << BIT_SHIFT_PRFM_MAP1)
#define BIT_CLEAR_PRFM_MAP1(x)				((x) & (~BITS_PRFM_MAP1))
#define BIT_GET_PRFM_MAP1(x)				(((x) >> BIT_SHIFT_PRFM_MAP1) & BIT_MASK_PRFM_MAP1)
#define BIT_SET_PRFM_MAP1(x, v)			(BIT_CLEAR_PRFM_MAP1(x) | BIT_PRFM_MAP1(v))

#define BIT_SHIFT_PRFM_MAP0				0
#define BIT_MASK_PRFM_MAP0				0xffff
#define BIT_PRFM_MAP0(x)				(((x) & BIT_MASK_PRFM_MAP0) << BIT_SHIFT_PRFM_MAP0)
#define BITS_PRFM_MAP0					(BIT_MASK_PRFM_MAP0 << BIT_SHIFT_PRFM_MAP0)
#define BIT_CLEAR_PRFM_MAP0(x)				((x) & (~BITS_PRFM_MAP0))
#define BIT_GET_PRFM_MAP0(x)				(((x) >> BIT_SHIFT_PRFM_MAP0) & BIT_MASK_PRFM_MAP0)
#define BIT_SET_PRFM_MAP0(x, v)			(BIT_CLEAR_PRFM_MAP0(x) | BIT_PRFM_MAP0(v))

/* 2 REG_RPFMCAM_CMD				(Offset 0x0648) */

#define BIT_RPFMCAM_WE					BIT(16)

#define BIT_SHIFT_RPFMCAM_ADD				0
#define BIT_MASK_RPFMCAM_ADD				0x7f
#define BIT_RPFMCAM_ADD(x)				(((x) & BIT_MASK_RPFMCAM_ADD) << BIT_SHIFT_RPFMCAM_ADD)
#define BITS_RPFMCAM_ADD				(BIT_MASK_RPFMCAM_ADD << BIT_SHIFT_RPFMCAM_ADD)
#define BIT_CLEAR_RPFMCAM_ADD(x)			((x) & (~BITS_RPFMCAM_ADD))
#define BIT_GET_RPFMCAM_ADD(x)				(((x) >> BIT_SHIFT_RPFMCAM_ADD) & BIT_MASK_RPFMCAM_ADD)
#define BIT_SET_RPFMCAM_ADD(x, v)			(BIT_CLEAR_RPFMCAM_ADD(x) | BIT_RPFMCAM_ADD(v))

/* 2 REG_RPFMCAM_WD				(Offset 0x064C) */

#define BIT_SHIFT_RPFMCAM_WD				0
#define BIT_MASK_RPFMCAM_WD				0xffffffffL
#define BIT_RPFMCAM_WD(x)				(((x) & BIT_MASK_RPFMCAM_WD) << BIT_SHIFT_RPFMCAM_WD)
#define BITS_RPFMCAM_WD				(BIT_MASK_RPFMCAM_WD << BIT_SHIFT_RPFMCAM_WD)
#define BIT_CLEAR_RPFMCAM_WD(x)			((x) & (~BITS_RPFMCAM_WD))
#define BIT_GET_RPFMCAM_WD(x)				(((x) >> BIT_SHIFT_RPFMCAM_WD) & BIT_MASK_RPFMCAM_WD)
#define BIT_SET_RPFMCAM_WD(x, v)			(BIT_CLEAR_RPFMCAM_WD(x) | BIT_RPFMCAM_WD(v))

/* 2 REG_NAV_CTRL				(Offset 0x0650) */

#define BIT_SHIFT_NAV_UPBDY				16
#define BIT_MASK_NAV_UPBDY				0xff
#define BIT_NAV_UPBDY(x)				(((x) & BIT_MASK_NAV_UPBDY) << BIT_SHIFT_NAV_UPBDY)
#define BITS_NAV_UPBDY					(BIT_MASK_NAV_UPBDY << BIT_SHIFT_NAV_UPBDY)
#define BIT_CLEAR_NAV_UPBDY(x)				((x) & (~BITS_NAV_UPBDY))
#define BIT_GET_NAV_UPBDY(x)				(((x) >> BIT_SHIFT_NAV_UPBDY) & BIT_MASK_NAV_UPBDY)
#define BIT_SET_NAV_UPBDY(x, v)			(BIT_CLEAR_NAV_UPBDY(x) | BIT_NAV_UPBDY(v))

#define BIT_SHIFT_NAV_UPPER				16
#define BIT_MASK_NAV_UPPER				0xff
#define BIT_NAV_UPPER(x)				(((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER)
#define BITS_NAV_UPPER					(BIT_MASK_NAV_UPPER << BIT_SHIFT_NAV_UPPER)
#define BIT_CLEAR_NAV_UPPER(x)				((x) & (~BITS_NAV_UPPER))
#define BIT_GET_NAV_UPPER(x)				(((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER)
#define BIT_SET_NAV_UPPER(x, v)			(BIT_CLEAR_NAV_UPPER(x) | BIT_NAV_UPPER(v))

#define BIT_SHIFT_RXMYRTS_NAV				8
#define BIT_MASK_RXMYRTS_NAV				0xf
#define BIT_RXMYRTS_NAV(x)				(((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV)
#define BITS_RXMYRTS_NAV				(BIT_MASK_RXMYRTS_NAV << BIT_SHIFT_RXMYRTS_NAV)
#define BIT_CLEAR_RXMYRTS_NAV(x)			((x) & (~BITS_RXMYRTS_NAV))
#define BIT_GET_RXMYRTS_NAV(x)				(((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV)
#define BIT_SET_RXMYRTS_NAV(x, v)			(BIT_CLEAR_RXMYRTS_NAV(x) | BIT_RXMYRTS_NAV(v))

#define BIT_SHIFT_RTS_RST_DUR				0
#define BIT_MASK_RTS_RST_DUR				0xff
#define BIT_RTS_RST_DUR(x)				(((x) & BIT_MASK_RTS_RST_DUR) << BIT_SHIFT_RTS_RST_DUR)
#define BITS_RTS_RST_DUR				(BIT_MASK_RTS_RST_DUR << BIT_SHIFT_RTS_RST_DUR)
#define BIT_CLEAR_RTS_RST_DUR(x)			((x) & (~BITS_RTS_RST_DUR))
#define BIT_GET_RTS_RST_DUR(x)				(((x) >> BIT_SHIFT_RTS_RST_DUR) & BIT_MASK_RTS_RST_DUR)
#define BIT_SET_RTS_RST_DUR(x, v)			(BIT_CLEAR_RTS_RST_DUR(x) | BIT_RTS_RST_DUR(v))

#define BIT_SHIFT_RTSRST				0
#define BIT_MASK_RTSRST				0xff
#define BIT_RTSRST(x)					(((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST)
#define BITS_RTSRST					(BIT_MASK_RTSRST << BIT_SHIFT_RTSRST)
#define BIT_CLEAR_RTSRST(x)				((x) & (~BITS_RTSRST))
#define BIT_GET_RTSRST(x)				(((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST)
#define BIT_SET_RTSRST(x, v)				(BIT_CLEAR_RTSRST(x) | BIT_RTSRST(v))

/* 2 REG_BACAMCMD				(Offset 0x0654) */

#define BIT_BACAM_POLL					BIT(31)
#define BIT_BACAM_RST					BIT(17)
#define BIT_BACAM_RW					BIT(16)

#define BIT_SHIFT_TXSBMPMOD				14
#define BIT_MASK_TXSBMPMOD				0x3
#define BIT_TXSBMPMOD(x)				(((x) & BIT_MASK_TXSBMPMOD) << BIT_SHIFT_TXSBMPMOD)
#define BITS_TXSBMPMOD					(BIT_MASK_TXSBMPMOD << BIT_SHIFT_TXSBMPMOD)
#define BIT_CLEAR_TXSBMPMOD(x)				((x) & (~BITS_TXSBMPMOD))
#define BIT_GET_TXSBMPMOD(x)				(((x) >> BIT_SHIFT_TXSBMPMOD) & BIT_MASK_TXSBMPMOD)
#define BIT_SET_TXSBMPMOD(x, v)			(BIT_CLEAR_TXSBMPMOD(x) | BIT_TXSBMPMOD(v))

#define BIT_RXBACAM_DA_EN				BIT(13)

#define BIT_SHIFT_BACAM_AD				0
#define BIT_MASK_BACAM_AD				0x3f
#define BIT_BACAM_AD(x)				(((x) & BIT_MASK_BACAM_AD) << BIT_SHIFT_BACAM_AD)
#define BITS_BACAM_AD					(BIT_MASK_BACAM_AD << BIT_SHIFT_BACAM_AD)
#define BIT_CLEAR_BACAM_AD(x)				((x) & (~BITS_BACAM_AD))
#define BIT_GET_BACAM_AD(x)				(((x) >> BIT_SHIFT_BACAM_AD) & BIT_MASK_BACAM_AD)
#define BIT_SET_BACAM_AD(x, v)				(BIT_CLEAR_BACAM_AD(x) | BIT_BACAM_AD(v))

/* 2 REG_BACAM_WD_L				(Offset 0x0658) */

#define BIT_SHIFT_BA_CONTENT_L				0
#define BIT_MASK_BA_CONTENT_L				0xffffffffL
#define BIT_BA_CONTENT_L(x)				(((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L)
#define BITS_BA_CONTENT_L				(BIT_MASK_BA_CONTENT_L << BIT_SHIFT_BA_CONTENT_L)
#define BIT_CLEAR_BA_CONTENT_L(x)			((x) & (~BITS_BA_CONTENT_L))
#define BIT_GET_BA_CONTENT_L(x)			(((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L)
#define BIT_SET_BA_CONTENT_L(x, v)			(BIT_CLEAR_BA_CONTENT_L(x) | BIT_BA_CONTENT_L(v))

/* 2 REG_BACAM_WD_H				(Offset 0x065C) */

#define BIT_SHIFT_BA_CONTENT_H				0
#define BIT_MASK_BA_CONTENT_H				0xffffffffL
#define BIT_BA_CONTENT_H(x)				(((x) & BIT_MASK_BA_CONTENT_H) << BIT_SHIFT_BA_CONTENT_H)
#define BITS_BA_CONTENT_H				(BIT_MASK_BA_CONTENT_H << BIT_SHIFT_BA_CONTENT_H)
#define BIT_CLEAR_BA_CONTENT_H(x)			((x) & (~BITS_BA_CONTENT_H))
#define BIT_GET_BA_CONTENT_H(x)			(((x) >> BIT_SHIFT_BA_CONTENT_H) & BIT_MASK_BA_CONTENT_H)
#define BIT_SET_BA_CONTENT_H(x, v)			(BIT_CLEAR_BA_CONTENT_H(x) | BIT_BA_CONTENT_H(v))

/* 2 REG_LBK_DLY				(Offset 0x0660) */

#define BIT_SHIFT_LBK_DLY				0
#define BIT_MASK_LBK_DLY				0x1f
#define BIT_LBK_DLY(x)					(((x) & BIT_MASK_LBK_DLY) << BIT_SHIFT_LBK_DLY)
#define BITS_LBK_DLY					(BIT_MASK_LBK_DLY << BIT_SHIFT_LBK_DLY)
#define BIT_CLEAR_LBK_DLY(x)				((x) & (~BITS_LBK_DLY))
#define BIT_GET_LBK_DLY(x)				(((x) >> BIT_SHIFT_LBK_DLY) & BIT_MASK_LBK_DLY)
#define BIT_SET_LBK_DLY(x, v)				(BIT_CLEAR_LBK_DLY(x) | BIT_LBK_DLY(v))

/* 2 REG_BITMAP_CMD				(Offset 0x0661) */

#define BIT_SHIFT_BITMAP_SSNBK_COUNTER			2
#define BIT_MASK_BITMAP_SSNBK_COUNTER			0x3f
#define BIT_BITMAP_SSNBK_COUNTER(x)			(((x) & BIT_MASK_BITMAP_SSNBK_COUNTER) << BIT_SHIFT_BITMAP_SSNBK_COUNTER)
#define BITS_BITMAP_SSNBK_COUNTER			(BIT_MASK_BITMAP_SSNBK_COUNTER << BIT_SHIFT_BITMAP_SSNBK_COUNTER)
#define BIT_CLEAR_BITMAP_SSNBK_COUNTER(x)		((x) & (~BITS_BITMAP_SSNBK_COUNTER))
#define BIT_GET_BITMAP_SSNBK_COUNTER(x)		(((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) & BIT_MASK_BITMAP_SSNBK_COUNTER)
#define BIT_SET_BITMAP_SSNBK_COUNTER(x, v)		(BIT_CLEAR_BITMAP_SSNBK_COUNTER(x) | BIT_BITMAP_SSNBK_COUNTER(v))

#define BIT_BITMAP_EN					BIT(1)
#define BIT_BACAM_RPMEN				BIT(0)

/* 2 REG_TX_RX				(Offset 0x0662) */

#define BIT_SHIFT_RXPKT_TYPE				2
#define BIT_MASK_RXPKT_TYPE				0x3f
#define BIT_RXPKT_TYPE(x)				(((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE)
#define BITS_RXPKT_TYPE				(BIT_MASK_RXPKT_TYPE << BIT_SHIFT_RXPKT_TYPE)
#define BIT_CLEAR_RXPKT_TYPE(x)			((x) & (~BITS_RXPKT_TYPE))
#define BIT_GET_RXPKT_TYPE(x)				(((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE)
#define BIT_SET_RXPKT_TYPE(x, v)			(BIT_CLEAR_RXPKT_TYPE(x) | BIT_RXPKT_TYPE(v))

#define BIT_TXACT_IND					BIT(1)
#define BIT_RXACT_IND					BIT(0)

/* 2 REG_WMAC_BITMAP_CTL			(Offset 0x0663) */

#define BIT_BITMAP_FLAG_VO				BIT(7)
#define BIT_BITMAP_FLAG_VI				BIT(6)
#define BIT_BITMAP_FLAG_BE				BIT(5)
#define BIT_BITMAP_FLAG_BK				BIT(4)

#define BIT_SHIFT_BITMAP_CONDITION			2
#define BIT_MASK_BITMAP_CONDITION			0x3
#define BIT_BITMAP_CONDITION(x)			(((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION)
#define BITS_BITMAP_CONDITION				(BIT_MASK_BITMAP_CONDITION << BIT_SHIFT_BITMAP_CONDITION)
#define BIT_CLEAR_BITMAP_CONDITION(x)			((x) & (~BITS_BITMAP_CONDITION))
#define BIT_GET_BITMAP_CONDITION(x)			(((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION)
#define BIT_SET_BITMAP_CONDITION(x, v)			(BIT_CLEAR_BITMAP_CONDITION(x) | BIT_BITMAP_CONDITION(v))

#define BIT_BITMAP_SSNBK_COUNTER_CLR			BIT(1)
#define BIT_BITMAP_FORCE				BIT(0)

/* 2 REG_RXERR_RPT				(Offset 0x0664) */

#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0			28
#define BIT_MASK_RXERR_RPT_SEL_V1_3_0			0xf
#define BIT_RXERR_RPT_SEL_V1_3_0(x)			(((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0)
#define BITS_RXERR_RPT_SEL_V1_3_0			(BIT_MASK_RXERR_RPT_SEL_V1_3_0 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0)
#define BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x)		((x) & (~BITS_RXERR_RPT_SEL_V1_3_0))
#define BIT_GET_RXERR_RPT_SEL_V1_3_0(x)		(((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) & BIT_MASK_RXERR_RPT_SEL_V1_3_0)
#define BIT_SET_RXERR_RPT_SEL_V1_3_0(x, v)		(BIT_CLEAR_RXERR_RPT_SEL_V1_3_0(x) | BIT_RXERR_RPT_SEL_V1_3_0(v))

#define BIT_RXERR_RPT_RST				BIT(27)
#define BIT_RXERR_RPT_SEL_V1_4				BIT(26)

#define BIT_SHIFT_UD_SELECT_BSSID_2_1			24
#define BIT_MASK_UD_SELECT_BSSID_2_1			0x3
#define BIT_UD_SELECT_BSSID_2_1(x)			(((x) & BIT_MASK_UD_SELECT_BSSID_2_1) << BIT_SHIFT_UD_SELECT_BSSID_2_1)
#define BITS_UD_SELECT_BSSID_2_1			(BIT_MASK_UD_SELECT_BSSID_2_1 << BIT_SHIFT_UD_SELECT_BSSID_2_1)
#define BIT_CLEAR_UD_SELECT_BSSID_2_1(x)		((x) & (~BITS_UD_SELECT_BSSID_2_1))
#define BIT_GET_UD_SELECT_BSSID_2_1(x)			(((x) >> BIT_SHIFT_UD_SELECT_BSSID_2_1) & BIT_MASK_UD_SELECT_BSSID_2_1)
#define BIT_SET_UD_SELECT_BSSID_2_1(x, v)		(BIT_CLEAR_UD_SELECT_BSSID_2_1(x) | BIT_UD_SELECT_BSSID_2_1(v))

#define BIT_W1S					BIT(23)
#define BIT_UD_SELECT_BSSID				BIT(22)

#define BIT_SHIFT_UD_SUB_TYPE				18
#define BIT_MASK_UD_SUB_TYPE				0xf
#define BIT_UD_SUB_TYPE(x)				(((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE)
#define BITS_UD_SUB_TYPE				(BIT_MASK_UD_SUB_TYPE << BIT_SHIFT_UD_SUB_TYPE)
#define BIT_CLEAR_UD_SUB_TYPE(x)			((x) & (~BITS_UD_SUB_TYPE))
#define BIT_GET_UD_SUB_TYPE(x)				(((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE)
#define BIT_SET_UD_SUB_TYPE(x, v)			(BIT_CLEAR_UD_SUB_TYPE(x) | BIT_UD_SUB_TYPE(v))

#define BIT_SHIFT_UD_TYPE				16
#define BIT_MASK_UD_TYPE				0x3
#define BIT_UD_TYPE(x)					(((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE)
#define BITS_UD_TYPE					(BIT_MASK_UD_TYPE << BIT_SHIFT_UD_TYPE)
#define BIT_CLEAR_UD_TYPE(x)				((x) & (~BITS_UD_TYPE))
#define BIT_GET_UD_TYPE(x)				(((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE)
#define BIT_SET_UD_TYPE(x, v)				(BIT_CLEAR_UD_TYPE(x) | BIT_UD_TYPE(v))

#define BIT_SHIFT_RPT_COUNTER				0
#define BIT_MASK_RPT_COUNTER				0xffff
#define BIT_RPT_COUNTER(x)				(((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER)
#define BITS_RPT_COUNTER				(BIT_MASK_RPT_COUNTER << BIT_SHIFT_RPT_COUNTER)
#define BIT_CLEAR_RPT_COUNTER(x)			((x) & (~BITS_RPT_COUNTER))
#define BIT_GET_RPT_COUNTER(x)				(((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER)
#define BIT_SET_RPT_COUNTER(x, v)			(BIT_CLEAR_RPT_COUNTER(x) | BIT_RPT_COUNTER(v))

/* 2 REG_WMAC_TRXPTCL_CTL			(Offset 0x0668) */

#define BIT_BLK_EDCA_BBSLP				BIT(31)
#define BIT_BLK_EDCA_BBSBY				BIT(30)
#define BIT_EN_STOP_UPDNAV				BIT(28)
#define BIT_RST_EDCA_ACKTO				BIT(27)
#define BIT_RST_EDCA_EIFS				BIT(26)
#define BIT_PLCPCHK_RST_EIFS				BIT(25)
#define BIT_CCA_RST_EIFS				BIT(24)
#define BIT_DIS_UPD_MYRXPKTNAV				BIT(23)
#define BIT_EARLY_TXBA					BIT(22)

#define BIT_SHIFT_RESP_CHNBUSY				20
#define BIT_MASK_RESP_CHNBUSY				0x3
#define BIT_RESP_CHNBUSY(x)				(((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY)
#define BITS_RESP_CHNBUSY				(BIT_MASK_RESP_CHNBUSY << BIT_SHIFT_RESP_CHNBUSY)
#define BIT_CLEAR_RESP_CHNBUSY(x)			((x) & (~BITS_RESP_CHNBUSY))
#define BIT_GET_RESP_CHNBUSY(x)			(((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY)
#define BIT_SET_RESP_CHNBUSY(x, v)			(BIT_CLEAR_RESP_CHNBUSY(x) | BIT_RESP_CHNBUSY(v))

#define BIT_RESP_DCTS_EN				BIT(19)
#define BIT_RESP_DCFE_EN				BIT(18)
#define BIT_RESP_SPLCPEN				BIT(17)
#define BIT_RESP_SGIEN					BIT(16)
#define BIT_RESP_LDPC_EN				BIT(15)
#define BIT_DIS_RESP_ACKINCCA				BIT(14)
#define BIT_DIS_RESP_CTSINCCA				BIT(13)

#define BIT_SHIFT_SECOND_CCA_TIMER			10
#define BIT_MASK_SECOND_CCA_TIMER			0x7
#define BIT_SECOND_CCA_TIMER(x)			(((x) & BIT_MASK_SECOND_CCA_TIMER) << BIT_SHIFT_SECOND_CCA_TIMER)
#define BITS_SECOND_CCA_TIMER				(BIT_MASK_SECOND_CCA_TIMER << BIT_SHIFT_SECOND_CCA_TIMER)
#define BIT_CLEAR_SECOND_CCA_TIMER(x)			((x) & (~BITS_SECOND_CCA_TIMER))
#define BIT_GET_SECOND_CCA_TIMER(x)			(((x) >> BIT_SHIFT_SECOND_CCA_TIMER) & BIT_MASK_SECOND_CCA_TIMER)
#define BIT_SET_SECOND_CCA_TIMER(x, v)			(BIT_CLEAR_SECOND_CCA_TIMER(x) | BIT_SECOND_CCA_TIMER(v))

#define BIT_SHIFT_RFMOD				7
#define BIT_MASK_RFMOD					0x3
#define BIT_RFMOD(x)					(((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD)
#define BITS_RFMOD					(BIT_MASK_RFMOD << BIT_SHIFT_RFMOD)
#define BIT_CLEAR_RFMOD(x)				((x) & (~BITS_RFMOD))
#define BIT_GET_RFMOD(x)				(((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD)
#define BIT_SET_RFMOD(x, v)				(BIT_CLEAR_RFMOD(x) | BIT_RFMOD(v))

#define BIT_SHIFT_RESP_CTS_DYNBW_SEL			5
#define BIT_MASK_RESP_CTS_DYNBW_SEL			0x3
#define BIT_RESP_CTS_DYNBW_SEL(x)			(((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL)
#define BITS_RESP_CTS_DYNBW_SEL			(BIT_MASK_RESP_CTS_DYNBW_SEL << BIT_SHIFT_RESP_CTS_DYNBW_SEL)
#define BIT_CLEAR_RESP_CTS_DYNBW_SEL(x)		((x) & (~BITS_RESP_CTS_DYNBW_SEL))
#define BIT_GET_RESP_CTS_DYNBW_SEL(x)			(((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL)
#define BIT_SET_RESP_CTS_DYNBW_SEL(x, v)		(BIT_CLEAR_RESP_CTS_DYNBW_SEL(x) | BIT_RESP_CTS_DYNBW_SEL(v))

#define BIT_DLY_TX_WAIT_RXANTSEL			BIT(4)
#define BIT_TXRESP_BY_RXANTSEL				BIT(3)

#define BIT_SHIFT_ORIG_DCTS_CHK			0
#define BIT_MASK_ORIG_DCTS_CHK				0x3
#define BIT_ORIG_DCTS_CHK(x)				(((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK)
#define BITS_ORIG_DCTS_CHK				(BIT_MASK_ORIG_DCTS_CHK << BIT_SHIFT_ORIG_DCTS_CHK)
#define BIT_CLEAR_ORIG_DCTS_CHK(x)			((x) & (~BITS_ORIG_DCTS_CHK))
#define BIT_GET_ORIG_DCTS_CHK(x)			(((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK)
#define BIT_SET_ORIG_DCTS_CHK(x, v)			(BIT_CLEAR_ORIG_DCTS_CHK(x) | BIT_ORIG_DCTS_CHK(v))

/* 2 REG_WMAC_TRXPTCL_CTL_H			(Offset 0x066C) */

#define BIT_SHIFT_ACKBA_TYPSEL				28
#define BIT_MASK_ACKBA_TYPSEL				0xf
#define BIT_ACKBA_TYPSEL(x)				(((x) & BIT_MASK_ACKBA_TYPSEL) << BIT_SHIFT_ACKBA_TYPSEL)
#define BITS_ACKBA_TYPSEL				(BIT_MASK_ACKBA_TYPSEL << BIT_SHIFT_ACKBA_TYPSEL)
#define BIT_CLEAR_ACKBA_TYPSEL(x)			((x) & (~BITS_ACKBA_TYPSEL))
#define BIT_GET_ACKBA_TYPSEL(x)			(((x) >> BIT_SHIFT_ACKBA_TYPSEL) & BIT_MASK_ACKBA_TYPSEL)
#define BIT_SET_ACKBA_TYPSEL(x, v)			(BIT_CLEAR_ACKBA_TYPSEL(x) | BIT_ACKBA_TYPSEL(v))

#define BIT_SHIFT_ACKBA_ACKPCHK			24
#define BIT_MASK_ACKBA_ACKPCHK				0xf
#define BIT_ACKBA_ACKPCHK(x)				(((x) & BIT_MASK_ACKBA_ACKPCHK) << BIT_SHIFT_ACKBA_ACKPCHK)
#define BITS_ACKBA_ACKPCHK				(BIT_MASK_ACKBA_ACKPCHK << BIT_SHIFT_ACKBA_ACKPCHK)
#define BIT_CLEAR_ACKBA_ACKPCHK(x)			((x) & (~BITS_ACKBA_ACKPCHK))
#define BIT_GET_ACKBA_ACKPCHK(x)			(((x) >> BIT_SHIFT_ACKBA_ACKPCHK) & BIT_MASK_ACKBA_ACKPCHK)
#define BIT_SET_ACKBA_ACKPCHK(x, v)			(BIT_CLEAR_ACKBA_ACKPCHK(x) | BIT_ACKBA_ACKPCHK(v))

#define BIT_SHIFT_ACKBAR_TYPESEL			16
#define BIT_MASK_ACKBAR_TYPESEL			0xff
#define BIT_ACKBAR_TYPESEL(x)				(((x) & BIT_MASK_ACKBAR_TYPESEL) << BIT_SHIFT_ACKBAR_TYPESEL)
#define BITS_ACKBAR_TYPESEL				(BIT_MASK_ACKBAR_TYPESEL << BIT_SHIFT_ACKBAR_TYPESEL)
#define BIT_CLEAR_ACKBAR_TYPESEL(x)			((x) & (~BITS_ACKBAR_TYPESEL))
#define BIT_GET_ACKBAR_TYPESEL(x)			(((x) >> BIT_SHIFT_ACKBAR_TYPESEL) & BIT_MASK_ACKBAR_TYPESEL)
#define BIT_SET_ACKBAR_TYPESEL(x, v)			(BIT_CLEAR_ACKBAR_TYPESEL(x) | BIT_ACKBAR_TYPESEL(v))

#define BIT_SHIFT_ACKBAR_ACKPCHK			12
#define BIT_MASK_ACKBAR_ACKPCHK			0xf
#define BIT_ACKBAR_ACKPCHK(x)				(((x) & BIT_MASK_ACKBAR_ACKPCHK) << BIT_SHIFT_ACKBAR_ACKPCHK)
#define BITS_ACKBAR_ACKPCHK				(BIT_MASK_ACKBAR_ACKPCHK << BIT_SHIFT_ACKBAR_ACKPCHK)
#define BIT_CLEAR_ACKBAR_ACKPCHK(x)			((x) & (~BITS_ACKBAR_ACKPCHK))
#define BIT_GET_ACKBAR_ACKPCHK(x)			(((x) >> BIT_SHIFT_ACKBAR_ACKPCHK) & BIT_MASK_ACKBAR_ACKPCHK)
#define BIT_SET_ACKBAR_ACKPCHK(x, v)			(BIT_CLEAR_ACKBAR_ACKPCHK(x) | BIT_ACKBAR_ACKPCHK(v))

#define BIT_RXBA_IGNOREA2_V1				BIT(10)
#define BIT_EN_SAVE_ALL_TXOPADDR_V1			BIT(9)
#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_V1		BIT(8)
#define BIT_DIS_TXBA_AMPDUFCSERR_V1			BIT(7)
#define BIT_DIS_TXBA_RXBARINFULL_V1			BIT(6)
#define BIT_DIS_TXCFE_INFULL_V1			BIT(5)
#define BIT_DIS_TXCTS_INFULL_V1			BIT(4)
#define BIT_EN_TXACKBA_INTX_RDG_V1			BIT(3)
#define BIT_EN_TXACKBA_INTXOP_V1			BIT(2)
#define BIT_EN_TXCTS_INRXNAV_V1			BIT(1)
#define BIT_EN_TXCTS_INTXOP_V1				BIT(0)

/* 2 REG_KEYCAMCMD				(Offset 0x0670) */

#define BIT_KEYCAM_POLLING				BIT(31)
#define BIT_KEYCAM_CLEAR				BIT(30)
#define BIT_MFBCAM_CLEAR				BIT(29)
#define BIT_KEYCAM_DA_EN				BIT(17)
#define BIT_SECCAM_WE					BIT(16)

#define BIT_SHIFT_KEYCAM_AD				0
#define BIT_MASK_KEYCAM_AD				0x3ff
#define BIT_KEYCAM_AD(x)				(((x) & BIT_MASK_KEYCAM_AD) << BIT_SHIFT_KEYCAM_AD)
#define BITS_KEYCAM_AD					(BIT_MASK_KEYCAM_AD << BIT_SHIFT_KEYCAM_AD)
#define BIT_CLEAR_KEYCAM_AD(x)				((x) & (~BITS_KEYCAM_AD))
#define BIT_GET_KEYCAM_AD(x)				(((x) >> BIT_SHIFT_KEYCAM_AD) & BIT_MASK_KEYCAM_AD)
#define BIT_SET_KEYCAM_AD(x, v)			(BIT_CLEAR_KEYCAM_AD(x) | BIT_KEYCAM_AD(v))

/* 2 REG_KEYCAM_WD				(Offset 0x0674) */

#define BIT_SHIFT_KEYCAM_WDATA				0
#define BIT_MASK_KEYCAM_WDATA				0xffffffffL
#define BIT_KEYCAM_WDATA(x)				(((x) & BIT_MASK_KEYCAM_WDATA) << BIT_SHIFT_KEYCAM_WDATA)
#define BITS_KEYCAM_WDATA				(BIT_MASK_KEYCAM_WDATA << BIT_SHIFT_KEYCAM_WDATA)
#define BIT_CLEAR_KEYCAM_WDATA(x)			((x) & (~BITS_KEYCAM_WDATA))
#define BIT_GET_KEYCAM_WDATA(x)			(((x) >> BIT_SHIFT_KEYCAM_WDATA) & BIT_MASK_KEYCAM_WDATA)
#define BIT_SET_KEYCAM_WDATA(x, v)			(BIT_CLEAR_KEYCAM_WDATA(x) | BIT_KEYCAM_WDATA(v))

/* 2 REG_CAMREAD				(Offset 0x0678) */

#define BIT_SHIFT_CAMR_DATA				0
#define BIT_MASK_CAMR_DATA				0xffffffffL
#define BIT_CAMR_DATA(x)				(((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA)
#define BITS_CAMR_DATA					(BIT_MASK_CAMR_DATA << BIT_SHIFT_CAMR_DATA)
#define BIT_CLEAR_CAMR_DATA(x)				((x) & (~BITS_CAMR_DATA))
#define BIT_GET_CAMR_DATA(x)				(((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA)
#define BIT_SET_CAMR_DATA(x, v)			(BIT_CLEAR_CAMR_DATA(x) | BIT_CAMR_DATA(v))

/* 2 REG_CAMDBG				(Offset 0x067C) */

#define BIT_KEYCAM_DBGSEL				BIT(31)
#define BIT_SEC_KEYFOUND_V1				BIT(15)

#define BIT_SHIFT_CAMDBG_SEC_TYPE_V1			12
#define BIT_MASK_CAMDBG_SEC_TYPE_V1			0x7
#define BIT_CAMDBG_SEC_TYPE_V1(x)			(((x) & BIT_MASK_CAMDBG_SEC_TYPE_V1) << BIT_SHIFT_CAMDBG_SEC_TYPE_V1)
#define BITS_CAMDBG_SEC_TYPE_V1			(BIT_MASK_CAMDBG_SEC_TYPE_V1 << BIT_SHIFT_CAMDBG_SEC_TYPE_V1)
#define BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x)		((x) & (~BITS_CAMDBG_SEC_TYPE_V1))
#define BIT_GET_CAMDBG_SEC_TYPE_V1(x)			(((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_V1) & BIT_MASK_CAMDBG_SEC_TYPE_V1)
#define BIT_SET_CAMDBG_SEC_TYPE_V1(x, v)		(BIT_CLEAR_CAMDBG_SEC_TYPE_V1(x) | BIT_CAMDBG_SEC_TYPE_V1(v))

#define BIT_EXT_SECTYPE				BIT(11)

#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V3		5
#define BIT_MASK_CAMDBG_MIC_KEY_IDX_V3			0x1f
#define BIT_CAMDBG_MIC_KEY_IDX_V3(x)			(((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_V3) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V3)
#define BITS_CAMDBG_MIC_KEY_IDX_V3			(BIT_MASK_CAMDBG_MIC_KEY_IDX_V3 << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V3)
#define BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V3(x)		((x) & (~BITS_CAMDBG_MIC_KEY_IDX_V3))
#define BIT_GET_CAMDBG_MIC_KEY_IDX_V3(x)		(((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_V3) & BIT_MASK_CAMDBG_MIC_KEY_IDX_V3)
#define BIT_SET_CAMDBG_MIC_KEY_IDX_V3(x, v)		(BIT_CLEAR_CAMDBG_MIC_KEY_IDX_V3(x) | BIT_CAMDBG_MIC_KEY_IDX_V3(v))

#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V2		0
#define BIT_MASK_CAMDBG_SEC_KEY_IDX_V2			0x1f
#define BIT_CAMDBG_SEC_KEY_IDX_V2(x)			(((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_V2) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V2)
#define BITS_CAMDBG_SEC_KEY_IDX_V2			(BIT_MASK_CAMDBG_SEC_KEY_IDX_V2 << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V2)
#define BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V2(x)		((x) & (~BITS_CAMDBG_SEC_KEY_IDX_V2))
#define BIT_GET_CAMDBG_SEC_KEY_IDX_V2(x)		(((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_V2) & BIT_MASK_CAMDBG_SEC_KEY_IDX_V2)
#define BIT_SET_CAMDBG_SEC_KEY_IDX_V2(x, v)		(BIT_CLEAR_CAMDBG_SEC_KEY_IDX_V2(x) | BIT_CAMDBG_SEC_KEY_IDX_V2(v))

/* 2 REG_SECCFG				(Offset 0x0680) */

#define BIT_DIS_GCLK_WAPI				BIT(15)
#define BIT_DIS_GCLK_AES				BIT(14)
#define BIT_DIS_GCLK_TKIP				BIT(13)
#define BIT_AES_SEL_QC_1				BIT(12)
#define BIT_AES_SEL_QC_0				BIT(11)
#define BIT_WMAC_CKECK_BMC				BIT(9)
#define BIT_CHK_KEYID					BIT(8)
#define BIT_RXBCUSEDK					BIT(7)
#define BIT_TXBCUSEDK					BIT(6)
#define BIT_NOSKMC					BIT(5)
#define BIT_SKBYA2					BIT(4)
#define BIT_RXDEC					BIT(3)
#define BIT_TXENC					BIT(2)
#define BIT_RXUHUSEDK					BIT(1)
#define BIT_TXUHUSEDK					BIT(0)

#define BIT_SHIFT_RXFILTER_CATEGORY_1			0
#define BIT_MASK_RXFILTER_CATEGORY_1			0xff
#define BIT_RXFILTER_CATEGORY_1(x)			(((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1)
#define BITS_RXFILTER_CATEGORY_1			(BIT_MASK_RXFILTER_CATEGORY_1 << BIT_SHIFT_RXFILTER_CATEGORY_1)
#define BIT_CLEAR_RXFILTER_CATEGORY_1(x)		((x) & (~BITS_RXFILTER_CATEGORY_1))
#define BIT_GET_RXFILTER_CATEGORY_1(x)			(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1)
#define BIT_SET_RXFILTER_CATEGORY_1(x, v)		(BIT_CLEAR_RXFILTER_CATEGORY_1(x) | BIT_RXFILTER_CATEGORY_1(v))

#define BIT_SHIFT_RXFILTER_ACTION_1			0
#define BIT_MASK_RXFILTER_ACTION_1			0xff
#define BIT_RXFILTER_ACTION_1(x)			(((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1)
#define BITS_RXFILTER_ACTION_1				(BIT_MASK_RXFILTER_ACTION_1 << BIT_SHIFT_RXFILTER_ACTION_1)
#define BIT_CLEAR_RXFILTER_ACTION_1(x)			((x) & (~BITS_RXFILTER_ACTION_1))
#define BIT_GET_RXFILTER_ACTION_1(x)			(((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1)
#define BIT_SET_RXFILTER_ACTION_1(x, v)		(BIT_CLEAR_RXFILTER_ACTION_1(x) | BIT_RXFILTER_ACTION_1(v))

/* 2 REG_RXFILTER_CATEGORY_ACTION		(Offset 0x0684) */

#define BIT_SHIFT_RXFILTER_ACTION_3			24
#define BIT_MASK_RXFILTER_ACTION_3			0xff
#define BIT_RXFILTER_ACTION_3(x)			(((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3)
#define BITS_RXFILTER_ACTION_3				(BIT_MASK_RXFILTER_ACTION_3 << BIT_SHIFT_RXFILTER_ACTION_3)
#define BIT_CLEAR_RXFILTER_ACTION_3(x)			((x) & (~BITS_RXFILTER_ACTION_3))
#define BIT_GET_RXFILTER_ACTION_3(x)			(((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3)
#define BIT_SET_RXFILTER_ACTION_3(x, v)		(BIT_CLEAR_RXFILTER_ACTION_3(x) | BIT_RXFILTER_ACTION_3(v))

#define BIT_SHIFT_RXFILTER_CATEGORY_3			16
#define BIT_MASK_RXFILTER_CATEGORY_3			0xff
#define BIT_RXFILTER_CATEGORY_3(x)			(((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3)
#define BITS_RXFILTER_CATEGORY_3			(BIT_MASK_RXFILTER_CATEGORY_3 << BIT_SHIFT_RXFILTER_CATEGORY_3)
#define BIT_CLEAR_RXFILTER_CATEGORY_3(x)		((x) & (~BITS_RXFILTER_CATEGORY_3))
#define BIT_GET_RXFILTER_CATEGORY_3(x)			(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3)
#define BIT_SET_RXFILTER_CATEGORY_3(x, v)		(BIT_CLEAR_RXFILTER_CATEGORY_3(x) | BIT_RXFILTER_CATEGORY_3(v))

#define BIT_SHIFT_RXFILTER_ACTION_2			8
#define BIT_MASK_RXFILTER_ACTION_2			0xff
#define BIT_RXFILTER_ACTION_2(x)			(((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2)
#define BITS_RXFILTER_ACTION_2				(BIT_MASK_RXFILTER_ACTION_2 << BIT_SHIFT_RXFILTER_ACTION_2)
#define BIT_CLEAR_RXFILTER_ACTION_2(x)			((x) & (~BITS_RXFILTER_ACTION_2))
#define BIT_GET_RXFILTER_ACTION_2(x)			(((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2)
#define BIT_SET_RXFILTER_ACTION_2(x, v)		(BIT_CLEAR_RXFILTER_ACTION_2(x) | BIT_RXFILTER_ACTION_2(v))

#define BIT_SHIFT_RXFILTER_CATEGORY_2			0
#define BIT_MASK_RXFILTER_CATEGORY_2			0xff
#define BIT_RXFILTER_CATEGORY_2(x)			(((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2)
#define BITS_RXFILTER_CATEGORY_2			(BIT_MASK_RXFILTER_CATEGORY_2 << BIT_SHIFT_RXFILTER_CATEGORY_2)
#define BIT_CLEAR_RXFILTER_CATEGORY_2(x)		((x) & (~BITS_RXFILTER_CATEGORY_2))
#define BIT_GET_RXFILTER_CATEGORY_2(x)			(((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2)
#define BIT_SET_RXFILTER_CATEGORY_2(x, v)		(BIT_CLEAR_RXFILTER_CATEGORY_2(x) | BIT_RXFILTER_CATEGORY_2(v))

/* 2 REG_RXFLTMAP3				(Offset 0x0688) */

#define BIT_MGTFLT15EN_FW				BIT(15)
#define BIT_MGTFLT14EN_FW				BIT(14)
#define BIT_MGTFLT13EN_FW				BIT(13)
#define BIT_MGTFLT12EN_FW				BIT(12)
#define BIT_MGTFLT11EN_FW				BIT(11)
#define BIT_MGTFLT10EN_FW				BIT(10)
#define BIT_MGTFLT9EN_FW				BIT(9)
#define BIT_MGTFLT8EN_FW				BIT(8)
#define BIT_MGTFLT7EN_FW				BIT(7)
#define BIT_MGTFLT6EN_FW				BIT(6)
#define BIT_MGTFLT5EN_FW				BIT(5)
#define BIT_MGTFLT4EN_FW				BIT(4)
#define BIT_MGTFLT3EN_FW				BIT(3)
#define BIT_MGTFLT2EN_FW				BIT(2)
#define BIT_MGTFLT1EN_FW				BIT(1)
#define BIT_MGTFLT0EN_FW				BIT(0)

/* 2 REG_RXFLTMAP4				(Offset 0x068A) */

#define BIT_CTRLFLT15EN_FW				BIT(15)
#define BIT_CTRLFLT14EN_FW				BIT(14)
#define BIT_CTRLFLT13EN_FW				BIT(13)
#define BIT_CTRLFLT12EN_FW				BIT(12)
#define BIT_CTRLFLT11EN_FW				BIT(11)
#define BIT_CTRLFLT10EN_FW				BIT(10)
#define BIT_CTRLFLT9EN_FW				BIT(9)
#define BIT_CTRLFLT8EN_FW				BIT(8)
#define BIT_CTRLFLT7EN_FW				BIT(7)
#define BIT_CTRLFLT6EN_FW				BIT(6)
#define BIT_CTRLFLT5EN_FW				BIT(5)
#define BIT_CTRLFLT4EN_FW				BIT(4)
#define BIT_CTRLFLT3EN_FW				BIT(3)
#define BIT_CTRLFLT2EN_FW				BIT(2)
#define BIT_CTRLFLT1EN_FW				BIT(1)
#define BIT_CTRLFLT0EN_FW				BIT(0)

/* 2 REG_RXFLTMAP5				(Offset 0x068C) */

#define BIT_DATAFLT15EN_FW				BIT(15)
#define BIT_DATAFLT14EN_FW				BIT(14)
#define BIT_DATAFLT13EN_FW				BIT(13)
#define BIT_DATAFLT12EN_FW				BIT(12)
#define BIT_DATAFLT11EN_FW				BIT(11)
#define BIT_DATAFLT10EN_FW				BIT(10)
#define BIT_DATAFLT9EN_FW				BIT(9)
#define BIT_DATAFLT8EN_FW				BIT(8)
#define BIT_DATAFLT7EN_FW				BIT(7)
#define BIT_DATAFLT6EN_FW				BIT(6)
#define BIT_DATAFLT5EN_FW				BIT(5)
#define BIT_DATAFLT4EN_FW				BIT(4)
#define BIT_DATAFLT3EN_FW				BIT(3)
#define BIT_DATAFLT2EN_FW				BIT(2)
#define BIT_DATAFLT1EN_FW				BIT(1)
#define BIT_DATAFLT0EN_FW				BIT(0)

/* 2 REG_RXFLTMAP6				(Offset 0x068E) */

#define BIT_ACTIONFLT15EN_FW				BIT(15)
#define BIT_ACTIONFLT14EN_FW				BIT(14)
#define BIT_ACTIONFLT13EN_FW				BIT(13)
#define BIT_ACTIONFLT12EN_FW				BIT(12)
#define BIT_ACTIONFLT11EN_FW				BIT(11)
#define BIT_ACTIONFLT10EN_FW				BIT(10)
#define BIT_ACTIONFLT9EN_FW				BIT(9)
#define BIT_ACTIONFLT8EN_FW				BIT(8)
#define BIT_ACTIONFLT7EN_FW				BIT(7)
#define BIT_ACTIONFLT6EN_FW				BIT(6)
#define BIT_ACTIONFLT5EN_FW				BIT(5)
#define BIT_ACTIONFLT4EN_FW				BIT(4)
#define BIT_ACTIONFLT3EN_FW				BIT(3)
#define BIT_ACTIONFLT2EN_FW				BIT(2)
#define BIT_ACTIONFLT1EN_FW				BIT(1)
#define BIT_ACTIONFLT0EN_FW				BIT(0)

/* 2 REG_WOW_CTRL				(Offset 0x0690) */

#define BIT_SHIFT_PSF_BSSIDSEL_H			6
#define BIT_MASK_PSF_BSSIDSEL_H			0x3
#define BIT_PSF_BSSIDSEL_H(x)				(((x) & BIT_MASK_PSF_BSSIDSEL_H) << BIT_SHIFT_PSF_BSSIDSEL_H)
#define BITS_PSF_BSSIDSEL_H				(BIT_MASK_PSF_BSSIDSEL_H << BIT_SHIFT_PSF_BSSIDSEL_H)
#define BIT_CLEAR_PSF_BSSIDSEL_H(x)			((x) & (~BITS_PSF_BSSIDSEL_H))
#define BIT_GET_PSF_BSSIDSEL_H(x)			(((x) >> BIT_SHIFT_PSF_BSSIDSEL_H) & BIT_MASK_PSF_BSSIDSEL_H)
#define BIT_SET_PSF_BSSIDSEL_H(x, v)			(BIT_CLEAR_PSF_BSSIDSEL_H(x) | BIT_PSF_BSSIDSEL_H(v))

#define BIT_WOWHCI					BIT(5)
#define BIT_PSF_BSSIDSEL_L				BIT(4)
#define BIT_UWF					BIT(3)
#define BIT_MAGIC					BIT(2)
#define BIT_WFMSK					BIT(1)

/* 2 REG_NAN_RX_FILTER			(Offset 0x0691) */

#define BIT_NAN_RX_CHKTA				BIT(2)
#define BIT_NAN_RX_CHKBSSID				BIT(1)
#define BIT_NAN_RX_FILTER_EN				BIT(0)

/* 2 REG_PS_RX_INFO				(Offset 0x0692) */

#define BIT_SHIFT_PORTSEL__PS_RX_INFO			5
#define BIT_MASK_PORTSEL__PS_RX_INFO			0x7
#define BIT_PORTSEL__PS_RX_INFO(x)			(((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO)
#define BITS_PORTSEL__PS_RX_INFO			(BIT_MASK_PORTSEL__PS_RX_INFO << BIT_SHIFT_PORTSEL__PS_RX_INFO)
#define BIT_CLEAR_PORTSEL__PS_RX_INFO(x)		((x) & (~BITS_PORTSEL__PS_RX_INFO))
#define BIT_GET_PORTSEL__PS_RX_INFO(x)			(((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO)
#define BIT_SET_PORTSEL__PS_RX_INFO(x, v)		(BIT_CLEAR_PORTSEL__PS_RX_INFO(x) | BIT_PORTSEL__PS_RX_INFO(v))

#define BIT_RXCTRLIN0					BIT(4)
#define BIT_RXMGTIN0					BIT(3)
#define BIT_RXDATAIN2					BIT(2)
#define BIT_RXDATAIN1					BIT(1)
#define BIT_RXDATAIN0					BIT(0)

/* 2 REG_WMMPS_UAPSD_TID			(Offset 0x0693) */

#define BIT_WMMPS_UAPSD_TID7				BIT(7)
#define BIT_WMMPS_UAPSD_TID6				BIT(6)
#define BIT_WMMPS_UAPSD_TID5				BIT(5)
#define BIT_WMMPS_UAPSD_TID4				BIT(4)
#define BIT_WMMPS_UAPSD_TID3				BIT(3)
#define BIT_WMMPS_UAPSD_TID2				BIT(2)
#define BIT_WMMPS_UAPSD_TID1				BIT(1)
#define BIT_WMMPS_UAPSD_TID0				BIT(0)

/* 2 REG_LPNAV_CTRL				(Offset 0x0694) */

#define BIT_LPNAV_EN					BIT(31)

#define BIT_SHIFT_LPNAV_EARLY				16
#define BIT_MASK_LPNAV_EARLY				0x7fff
#define BIT_LPNAV_EARLY(x)				(((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY)
#define BITS_LPNAV_EARLY				(BIT_MASK_LPNAV_EARLY << BIT_SHIFT_LPNAV_EARLY)
#define BIT_CLEAR_LPNAV_EARLY(x)			((x) & (~BITS_LPNAV_EARLY))
#define BIT_GET_LPNAV_EARLY(x)				(((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY)
#define BIT_SET_LPNAV_EARLY(x, v)			(BIT_CLEAR_LPNAV_EARLY(x) | BIT_LPNAV_EARLY(v))

#define BIT_SHIFT_LPNAV_THR				0
#define BIT_MASK_LPNAV_THR				0xffff
#define BIT_LPNAV_THR(x)				(((x) & BIT_MASK_LPNAV_THR) << BIT_SHIFT_LPNAV_THR)
#define BITS_LPNAV_THR					(BIT_MASK_LPNAV_THR << BIT_SHIFT_LPNAV_THR)
#define BIT_CLEAR_LPNAV_THR(x)				((x) & (~BITS_LPNAV_THR))
#define BIT_GET_LPNAV_THR(x)				(((x) >> BIT_SHIFT_LPNAV_THR) & BIT_MASK_LPNAV_THR)
#define BIT_SET_LPNAV_THR(x, v)			(BIT_CLEAR_LPNAV_THR(x) | BIT_LPNAV_THR(v))

/* 2 REG_WKFMCAM_CMD				(Offset 0x0698) */

#define BIT_WKFMCAM_WE					BIT(16)

#define BIT_SHIFT_WKFMCAM_AD				8
#define BIT_MASK_WKFMCAM_AD				0xff
#define BIT_WKFMCAM_AD(x)				(((x) & BIT_MASK_WKFMCAM_AD) << BIT_SHIFT_WKFMCAM_AD)
#define BITS_WKFMCAM_AD				(BIT_MASK_WKFMCAM_AD << BIT_SHIFT_WKFMCAM_AD)
#define BIT_CLEAR_WKFMCAM_AD(x)			((x) & (~BITS_WKFMCAM_AD))
#define BIT_GET_WKFMCAM_AD(x)				(((x) >> BIT_SHIFT_WKFMCAM_AD) & BIT_MASK_WKFMCAM_AD)
#define BIT_SET_WKFMCAM_AD(x, v)			(BIT_CLEAR_WKFMCAM_AD(x) | BIT_WKFMCAM_AD(v))

#define BIT_SHIFT_CAM_NUM				0
#define BIT_MASK_CAM_NUM				0xff
#define BIT_CAM_NUM(x)					(((x) & BIT_MASK_CAM_NUM) << BIT_SHIFT_CAM_NUM)
#define BITS_CAM_NUM					(BIT_MASK_CAM_NUM << BIT_SHIFT_CAM_NUM)
#define BIT_CLEAR_CAM_NUM(x)				((x) & (~BITS_CAM_NUM))
#define BIT_GET_CAM_NUM(x)				(((x) >> BIT_SHIFT_CAM_NUM) & BIT_MASK_CAM_NUM)
#define BIT_SET_CAM_NUM(x, v)				(BIT_CLEAR_CAM_NUM(x) | BIT_CAM_NUM(v))

/* 2 REG_WKFMCAM_WD				(Offset 0x069C) */

#define BIT_SHIFT_WKFMCAM_WD				0
#define BIT_MASK_WKFMCAM_WD				0xffffffffL
#define BIT_WKFMCAM_WD(x)				(((x) & BIT_MASK_WKFMCAM_WD) << BIT_SHIFT_WKFMCAM_WD)
#define BITS_WKFMCAM_WD				(BIT_MASK_WKFMCAM_WD << BIT_SHIFT_WKFMCAM_WD)
#define BIT_CLEAR_WKFMCAM_WD(x)			((x) & (~BITS_WKFMCAM_WD))
#define BIT_GET_WKFMCAM_WD(x)				(((x) >> BIT_SHIFT_WKFMCAM_WD) & BIT_MASK_WKFMCAM_WD)
#define BIT_SET_WKFMCAM_WD(x, v)			(BIT_CLEAR_WKFMCAM_WD(x) | BIT_WKFMCAM_WD(v))

/* 2 REG_RXFLTMAP0				(Offset 0x06A0) */

#define BIT_MGTFLT15EN					BIT(15)
#define BIT_MGTFLT14EN					BIT(14)
#define BIT_MGTFLT13EN					BIT(13)
#define BIT_MGTFLT12EN					BIT(12)
#define BIT_MGTFLT11EN					BIT(11)
#define BIT_MGTFLT10EN					BIT(10)
#define BIT_MGTFLT9EN					BIT(9)
#define BIT_MGTFLT8EN					BIT(8)
#define BIT_MGTFLT7EN					BIT(7)
#define BIT_MGTFLT6EN					BIT(6)
#define BIT_MGTFLT5EN					BIT(5)
#define BIT_MGTFLT4EN					BIT(4)
#define BIT_MGTFLT3EN					BIT(3)
#define BIT_MGTFLT2EN					BIT(2)
#define BIT_MGTFLT1EN					BIT(1)
#define BIT_MGTFLT0EN					BIT(0)

/* 2 REG_RXFLTMAP1				(Offset 0x06A2) */

#define BIT_CTRLFLT15EN				BIT(15)
#define BIT_CTRLFLT14EN				BIT(14)
#define BIT_CTRLFLT13EN				BIT(13)
#define BIT_CTRLFLT12EN				BIT(12)
#define BIT_CTRLFLT11EN				BIT(11)
#define BIT_CTRLFLT10EN				BIT(10)
#define BIT_CTRLFLT9EN					BIT(9)
#define BIT_CTRLFLT8EN					BIT(8)
#define BIT_CTRLFLT7EN					BIT(7)
#define BIT_CTRLFLT6EN					BIT(6)
#define BIT_CTRLFLT5EN					BIT(5)
#define BIT_CTRLFLT4EN					BIT(4)
#define BIT_CTRLFLT3EN					BIT(3)
#define BIT_CTRLFLT2EN					BIT(2)
#define BIT_CTRLFLT1EN					BIT(1)
#define BIT_CTRLFLT0EN					BIT(0)

/* 2 REG_RXFLTMAP2				(Offset 0x06A4) */

#define BIT_DATAFLT15EN				BIT(15)
#define BIT_DATAFLT14EN				BIT(14)
#define BIT_DATAFLT13EN				BIT(13)
#define BIT_DATAFLT12EN				BIT(12)
#define BIT_DATAFLT11EN				BIT(11)
#define BIT_DATAFLT10EN				BIT(10)
#define BIT_DATAFLT9EN					BIT(9)
#define BIT_DATAFLT8EN					BIT(8)
#define BIT_DATAFLT7EN					BIT(7)
#define BIT_DATAFLT6EN					BIT(6)
#define BIT_DATAFLT5EN					BIT(5)
#define BIT_DATAFLT4EN					BIT(4)
#define BIT_DATAFLT3EN					BIT(3)
#define BIT_DATAFLT2EN					BIT(2)
#define BIT_DATAFLT1EN					BIT(1)
#define BIT_DATAFLT0EN					BIT(0)

/* 2 REG_BCN_PSR_RPT				(Offset 0x06A8) */

#define BIT_SHIFT_DTIM_CNT				24
#define BIT_MASK_DTIM_CNT				0xff
#define BIT_DTIM_CNT(x)				(((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT)
#define BITS_DTIM_CNT					(BIT_MASK_DTIM_CNT << BIT_SHIFT_DTIM_CNT)
#define BIT_CLEAR_DTIM_CNT(x)				((x) & (~BITS_DTIM_CNT))
#define BIT_GET_DTIM_CNT(x)				(((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT)
#define BIT_SET_DTIM_CNT(x, v)				(BIT_CLEAR_DTIM_CNT(x) | BIT_DTIM_CNT(v))

#define BIT_SHIFT_DTIM_PERIOD				16
#define BIT_MASK_DTIM_PERIOD				0xff
#define BIT_DTIM_PERIOD(x)				(((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD)
#define BITS_DTIM_PERIOD				(BIT_MASK_DTIM_PERIOD << BIT_SHIFT_DTIM_PERIOD)
#define BIT_CLEAR_DTIM_PERIOD(x)			((x) & (~BITS_DTIM_PERIOD))
#define BIT_GET_DTIM_PERIOD(x)				(((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD)
#define BIT_SET_DTIM_PERIOD(x, v)			(BIT_CLEAR_DTIM_PERIOD(x) | BIT_DTIM_PERIOD(v))

#define BIT_DTIM					BIT(15)
#define BIT_TIM					BIT(14)
#define BIT_FLAG					BIT(13)

#define BIT_SHIFT_PS_AID_0				0
#define BIT_MASK_PS_AID_0				0x7ff
#define BIT_PS_AID_0(x)				(((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0)
#define BITS_PS_AID_0					(BIT_MASK_PS_AID_0 << BIT_SHIFT_PS_AID_0)
#define BIT_CLEAR_PS_AID_0(x)				((x) & (~BITS_PS_AID_0))
#define BIT_GET_PS_AID_0(x)				(((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0)
#define BIT_SET_PS_AID_0(x, v)				(BIT_CLEAR_PS_AID_0(x) | BIT_PS_AID_0(v))

/* 2 REG_FLC_CTRL				(Offset 0x06AC) */

#define BIT_SHIFT_FLC_RPC				0
#define BIT_MASK_FLC_RPC				0xff
#define BIT_FLC_RPC(x)					(((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC)
#define BITS_FLC_RPC					(BIT_MASK_FLC_RPC << BIT_SHIFT_FLC_RPC)
#define BIT_CLEAR_FLC_RPC(x)				((x) & (~BITS_FLC_RPC))
#define BIT_GET_FLC_RPC(x)				(((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC)
#define BIT_SET_FLC_RPC(x, v)				(BIT_CLEAR_FLC_RPC(x) | BIT_FLC_RPC(v))

/* 2 REG_FLC_RPCT				(Offset 0x06AD) */

#define BIT_SHIFT_FLC_PKTTH				0
#define BIT_MASK_FLC_PKTTH				0xff
#define BIT_FLC_PKTTH(x)				(((x) & BIT_MASK_FLC_PKTTH) << BIT_SHIFT_FLC_PKTTH)
#define BITS_FLC_PKTTH					(BIT_MASK_FLC_PKTTH << BIT_SHIFT_FLC_PKTTH)
#define BIT_CLEAR_FLC_PKTTH(x)				((x) & (~BITS_FLC_PKTTH))
#define BIT_GET_FLC_PKTTH(x)				(((x) >> BIT_SHIFT_FLC_PKTTH) & BIT_MASK_FLC_PKTTH)
#define BIT_SET_FLC_PKTTH(x, v)			(BIT_CLEAR_FLC_PKTTH(x) | BIT_FLC_PKTTH(v))

/* 2 REG_FLC_PTS				(Offset 0x06AE) */

#define BIT_FLC_CMFEN					BIT(2)
#define BIT_FLC_CCFEN					BIT(1)
#define BIT_FLC_CDFEN					BIT(0)

/* 2 REG_FLC_TRPC				(Offset 0x06AF) */

#define BIT_FLC_RPCT_V1				BIT(7)
#define BIT_FLC_MODSL					BIT(6)

#define BIT_SHIFT_TORRD				0
#define BIT_MASK_TORRD					0x3f
#define BIT_TORRD(x)					(((x) & BIT_MASK_TORRD) << BIT_SHIFT_TORRD)
#define BITS_TORRD					(BIT_MASK_TORRD << BIT_SHIFT_TORRD)
#define BIT_CLEAR_TORRD(x)				((x) & (~BITS_TORRD))
#define BIT_GET_TORRD(x)				(((x) >> BIT_SHIFT_TORRD) & BIT_MASK_TORRD)
#define BIT_SET_TORRD(x, v)				(BIT_CLEAR_TORRD(x) | BIT_TORRD(v))

/* 2 REG_RXPKTMON_CTRL			(Offset 0x06B0) */

#define BIT_SHIFT_RXBKQPKT_SEQ				20
#define BIT_MASK_RXBKQPKT_SEQ				0xf
#define BIT_RXBKQPKT_SEQ(x)				(((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ)
#define BITS_RXBKQPKT_SEQ				(BIT_MASK_RXBKQPKT_SEQ << BIT_SHIFT_RXBKQPKT_SEQ)
#define BIT_CLEAR_RXBKQPKT_SEQ(x)			((x) & (~BITS_RXBKQPKT_SEQ))
#define BIT_GET_RXBKQPKT_SEQ(x)			(((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ)
#define BIT_SET_RXBKQPKT_SEQ(x, v)			(BIT_CLEAR_RXBKQPKT_SEQ(x) | BIT_RXBKQPKT_SEQ(v))

#define BIT_SHIFT_RXBEQPKT_SEQ				16
#define BIT_MASK_RXBEQPKT_SEQ				0xf
#define BIT_RXBEQPKT_SEQ(x)				(((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ)
#define BITS_RXBEQPKT_SEQ				(BIT_MASK_RXBEQPKT_SEQ << BIT_SHIFT_RXBEQPKT_SEQ)
#define BIT_CLEAR_RXBEQPKT_SEQ(x)			((x) & (~BITS_RXBEQPKT_SEQ))
#define BIT_GET_RXBEQPKT_SEQ(x)			(((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ)
#define BIT_SET_RXBEQPKT_SEQ(x, v)			(BIT_CLEAR_RXBEQPKT_SEQ(x) | BIT_RXBEQPKT_SEQ(v))

#define BIT_SHIFT_RXVIQPKT_SEQ				12
#define BIT_MASK_RXVIQPKT_SEQ				0xf
#define BIT_RXVIQPKT_SEQ(x)				(((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ)
#define BITS_RXVIQPKT_SEQ				(BIT_MASK_RXVIQPKT_SEQ << BIT_SHIFT_RXVIQPKT_SEQ)
#define BIT_CLEAR_RXVIQPKT_SEQ(x)			((x) & (~BITS_RXVIQPKT_SEQ))
#define BIT_GET_RXVIQPKT_SEQ(x)			(((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ)
#define BIT_SET_RXVIQPKT_SEQ(x, v)			(BIT_CLEAR_RXVIQPKT_SEQ(x) | BIT_RXVIQPKT_SEQ(v))

#define BIT_SHIFT_RXVOQPKT_SEQ				8
#define BIT_MASK_RXVOQPKT_SEQ				0xf
#define BIT_RXVOQPKT_SEQ(x)				(((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ)
#define BITS_RXVOQPKT_SEQ				(BIT_MASK_RXVOQPKT_SEQ << BIT_SHIFT_RXVOQPKT_SEQ)
#define BIT_CLEAR_RXVOQPKT_SEQ(x)			((x) & (~BITS_RXVOQPKT_SEQ))
#define BIT_GET_RXVOQPKT_SEQ(x)			(((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ)
#define BIT_SET_RXVOQPKT_SEQ(x, v)			(BIT_CLEAR_RXVOQPKT_SEQ(x) | BIT_RXVOQPKT_SEQ(v))

#define BIT_RXBKQPKT_ERR				BIT(7)
#define BIT_RXBEQPKT_ERR				BIT(6)
#define BIT_RXVIQPKT_ERR				BIT(5)
#define BIT_RXVOQPKT_ERR				BIT(4)
#define BIT_RXDMA_MON_EN				BIT(2)
#define BIT_RXPKT_MON_EN				BIT(0)

/* 2 REG_STATE_MON				(Offset 0x06B4) */

#define BIT_SHIFT_STATE_SEL				24
#define BIT_MASK_STATE_SEL				0x1f
#define BIT_STATE_SEL(x)				(((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL)
#define BITS_STATE_SEL					(BIT_MASK_STATE_SEL << BIT_SHIFT_STATE_SEL)
#define BIT_CLEAR_STATE_SEL(x)				((x) & (~BITS_STATE_SEL))
#define BIT_GET_STATE_SEL(x)				(((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL)
#define BIT_SET_STATE_SEL(x, v)			(BIT_CLEAR_STATE_SEL(x) | BIT_STATE_SEL(v))

#define BIT_SHIFT_STATE_INFO				8
#define BIT_MASK_STATE_INFO				0xff
#define BIT_STATE_INFO(x)				(((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO)
#define BITS_STATE_INFO				(BIT_MASK_STATE_INFO << BIT_SHIFT_STATE_INFO)
#define BIT_CLEAR_STATE_INFO(x)			((x) & (~BITS_STATE_INFO))
#define BIT_GET_STATE_INFO(x)				(((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO)
#define BIT_SET_STATE_INFO(x, v)			(BIT_CLEAR_STATE_INFO(x) | BIT_STATE_INFO(v))

#define BIT_SHIFT_CUR_STATE				0
#define BIT_MASK_CUR_STATE				0x7f
#define BIT_CUR_STATE(x)				(((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE)
#define BITS_CUR_STATE					(BIT_MASK_CUR_STATE << BIT_SHIFT_CUR_STATE)
#define BIT_CLEAR_CUR_STATE(x)				((x) & (~BITS_CUR_STATE))
#define BIT_GET_CUR_STATE(x)				(((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE)
#define BIT_SET_CUR_STATE(x, v)			(BIT_CLEAR_CUR_STATE(x) | BIT_CUR_STATE(v))

/* 2 REG_ERROR_EVT_CTL			(Offset 0x06B8) */

#define BIT_CSIRPT_LEN_BB_MORE_THAN_MAC		BIT(23)
#define BIT_CSI_CHKSUM_ERROR				BIT(22)
#define BIT_MACRX_ERR_4				BIT(20)
#define BIT_MACRX_ERR_3				BIT(19)
#define BIT_MACRX_ERR_2				BIT(18)
#define BIT_MACRX_ERR_1				BIT(17)
#define BIT_MACRX_ERR_0				BIT(16)
#define BIT_PRETX_ERRHDL_EN				BIT(15)
#define BIT_MACTX_ERR_4				BIT(4)
#define BIT_MACTX_ERR_3				BIT(3)
#define BIT_MACTX_ERR_2				BIT(2)
#define BIT_MACTX_ERR_1				BIT(1)
#define BIT_MACTX_ERR_0				BIT(0)

/* 2 REG_SEARCH_MACID			(Offset 0x06BC) */

#define BIT_EN_TXRPTBUF_CLK				BIT(31)

#define BIT_SHIFT_INFO_INDEX_OFFSET			16
#define BIT_MASK_INFO_INDEX_OFFSET			0x1fff
#define BIT_INFO_INDEX_OFFSET(x)			(((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET)
#define BITS_INFO_INDEX_OFFSET				(BIT_MASK_INFO_INDEX_OFFSET << BIT_SHIFT_INFO_INDEX_OFFSET)
#define BIT_CLEAR_INFO_INDEX_OFFSET(x)			((x) & (~BITS_INFO_INDEX_OFFSET))
#define BIT_GET_INFO_INDEX_OFFSET(x)			(((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET)
#define BIT_SET_INFO_INDEX_OFFSET(x, v)		(BIT_CLEAR_INFO_INDEX_OFFSET(x) | BIT_INFO_INDEX_OFFSET(v))

#define BIT_WMAC_SRCH_FIFOFULL				BIT(15)
#define BIT_DIS_INFOSRCH				BIT(14)
#define BIT_DISABLE_B0					BIT(13)

#define BIT_SHIFT_INFO_ADDR_OFFSET			0
#define BIT_MASK_INFO_ADDR_OFFSET			0x1fff
#define BIT_INFO_ADDR_OFFSET(x)			(((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET)
#define BITS_INFO_ADDR_OFFSET				(BIT_MASK_INFO_ADDR_OFFSET << BIT_SHIFT_INFO_ADDR_OFFSET)
#define BIT_CLEAR_INFO_ADDR_OFFSET(x)			((x) & (~BITS_INFO_ADDR_OFFSET))
#define BIT_GET_INFO_ADDR_OFFSET(x)			(((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET)
#define BIT_SET_INFO_ADDR_OFFSET(x, v)			(BIT_CLEAR_INFO_ADDR_OFFSET(x) | BIT_INFO_ADDR_OFFSET(v))

/* 2 REG_BT_COEX_TABLE_V1			(Offset 0x06C0) */

#define BIT_SHIFT_COEX_TABLE_1				0
#define BIT_MASK_COEX_TABLE_1				0xffffffffL
#define BIT_COEX_TABLE_1(x)				(((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1)
#define BITS_COEX_TABLE_1				(BIT_MASK_COEX_TABLE_1 << BIT_SHIFT_COEX_TABLE_1)
#define BIT_CLEAR_COEX_TABLE_1(x)			((x) & (~BITS_COEX_TABLE_1))
#define BIT_GET_COEX_TABLE_1(x)			(((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1)
#define BIT_SET_COEX_TABLE_1(x, v)			(BIT_CLEAR_COEX_TABLE_1(x) | BIT_COEX_TABLE_1(v))

/* 2 REG_BT_COEX_TABLE2_V1			(Offset 0x06C4) */

#define BIT_SHIFT_COEX_TABLE_2				0
#define BIT_MASK_COEX_TABLE_2				0xffffffffL
#define BIT_COEX_TABLE_2(x)				(((x) & BIT_MASK_COEX_TABLE_2) << BIT_SHIFT_COEX_TABLE_2)
#define BITS_COEX_TABLE_2				(BIT_MASK_COEX_TABLE_2 << BIT_SHIFT_COEX_TABLE_2)
#define BIT_CLEAR_COEX_TABLE_2(x)			((x) & (~BITS_COEX_TABLE_2))
#define BIT_GET_COEX_TABLE_2(x)			(((x) >> BIT_SHIFT_COEX_TABLE_2) & BIT_MASK_COEX_TABLE_2)
#define BIT_SET_COEX_TABLE_2(x, v)			(BIT_CLEAR_COEX_TABLE_2(x) | BIT_COEX_TABLE_2(v))

/* 2 REG_BT_COEX_BREAK_TABLE			(Offset 0x06C8) */

#define BIT_SHIFT_BREAK_TABLE_2			16
#define BIT_MASK_BREAK_TABLE_2				0xffff
#define BIT_BREAK_TABLE_2(x)				(((x) & BIT_MASK_BREAK_TABLE_2) << BIT_SHIFT_BREAK_TABLE_2)
#define BITS_BREAK_TABLE_2				(BIT_MASK_BREAK_TABLE_2 << BIT_SHIFT_BREAK_TABLE_2)
#define BIT_CLEAR_BREAK_TABLE_2(x)			((x) & (~BITS_BREAK_TABLE_2))
#define BIT_GET_BREAK_TABLE_2(x)			(((x) >> BIT_SHIFT_BREAK_TABLE_2) & BIT_MASK_BREAK_TABLE_2)
#define BIT_SET_BREAK_TABLE_2(x, v)			(BIT_CLEAR_BREAK_TABLE_2(x) | BIT_BREAK_TABLE_2(v))

#define BIT_SHIFT_BREAK_TABLE_1			0
#define BIT_MASK_BREAK_TABLE_1				0xffff
#define BIT_BREAK_TABLE_1(x)				(((x) & BIT_MASK_BREAK_TABLE_1) << BIT_SHIFT_BREAK_TABLE_1)
#define BITS_BREAK_TABLE_1				(BIT_MASK_BREAK_TABLE_1 << BIT_SHIFT_BREAK_TABLE_1)
#define BIT_CLEAR_BREAK_TABLE_1(x)			((x) & (~BITS_BREAK_TABLE_1))
#define BIT_GET_BREAK_TABLE_1(x)			(((x) >> BIT_SHIFT_BREAK_TABLE_1) & BIT_MASK_BREAK_TABLE_1)
#define BIT_SET_BREAK_TABLE_1(x, v)			(BIT_CLEAR_BREAK_TABLE_1(x) | BIT_BREAK_TABLE_1(v))

/* 2 REG_BT_COEX_TABLE_H_V1			(Offset 0x06CC) */

#define BIT_PRI_MASK_RX_RESP_V1			BIT(30)
#define BIT_PRI_MASK_RXOFDM_V1				BIT(29)
#define BIT_PRI_MASK_RXCCK_V1				BIT(28)

#define BIT_SHIFT_PRI_MASK_TXAC			21
#define BIT_MASK_PRI_MASK_TXAC				0x7f
#define BIT_PRI_MASK_TXAC(x)				(((x) & BIT_MASK_PRI_MASK_TXAC) << BIT_SHIFT_PRI_MASK_TXAC)
#define BITS_PRI_MASK_TXAC				(BIT_MASK_PRI_MASK_TXAC << BIT_SHIFT_PRI_MASK_TXAC)
#define BIT_CLEAR_PRI_MASK_TXAC(x)			((x) & (~BITS_PRI_MASK_TXAC))
#define BIT_GET_PRI_MASK_TXAC(x)			(((x) >> BIT_SHIFT_PRI_MASK_TXAC) & BIT_MASK_PRI_MASK_TXAC)
#define BIT_SET_PRI_MASK_TXAC(x, v)			(BIT_CLEAR_PRI_MASK_TXAC(x) | BIT_PRI_MASK_TXAC(v))

#define BIT_SHIFT_PRI_MASK_NAV				13
#define BIT_MASK_PRI_MASK_NAV				0xff
#define BIT_PRI_MASK_NAV(x)				(((x) & BIT_MASK_PRI_MASK_NAV) << BIT_SHIFT_PRI_MASK_NAV)
#define BITS_PRI_MASK_NAV				(BIT_MASK_PRI_MASK_NAV << BIT_SHIFT_PRI_MASK_NAV)
#define BIT_CLEAR_PRI_MASK_NAV(x)			((x) & (~BITS_PRI_MASK_NAV))
#define BIT_GET_PRI_MASK_NAV(x)			(((x) >> BIT_SHIFT_PRI_MASK_NAV) & BIT_MASK_PRI_MASK_NAV)
#define BIT_SET_PRI_MASK_NAV(x, v)			(BIT_CLEAR_PRI_MASK_NAV(x) | BIT_PRI_MASK_NAV(v))

#define BIT_PRI_MASK_CCK_V1				BIT(12)
#define BIT_PRI_MASK_OFDM_V1				BIT(11)
#define BIT_PRI_MASK_RTY_V1				BIT(10)

#define BIT_SHIFT_PRI_MASK_NUM				6
#define BIT_MASK_PRI_MASK_NUM				0xf
#define BIT_PRI_MASK_NUM(x)				(((x) & BIT_MASK_PRI_MASK_NUM) << BIT_SHIFT_PRI_MASK_NUM)
#define BITS_PRI_MASK_NUM				(BIT_MASK_PRI_MASK_NUM << BIT_SHIFT_PRI_MASK_NUM)
#define BIT_CLEAR_PRI_MASK_NUM(x)			((x) & (~BITS_PRI_MASK_NUM))
#define BIT_GET_PRI_MASK_NUM(x)			(((x) >> BIT_SHIFT_PRI_MASK_NUM) & BIT_MASK_PRI_MASK_NUM)
#define BIT_SET_PRI_MASK_NUM(x, v)			(BIT_CLEAR_PRI_MASK_NUM(x) | BIT_PRI_MASK_NUM(v))

#define BIT_SHIFT_PRI_MASK_TYPE			2
#define BIT_MASK_PRI_MASK_TYPE				0xf
#define BIT_PRI_MASK_TYPE(x)				(((x) & BIT_MASK_PRI_MASK_TYPE) << BIT_SHIFT_PRI_MASK_TYPE)
#define BITS_PRI_MASK_TYPE				(BIT_MASK_PRI_MASK_TYPE << BIT_SHIFT_PRI_MASK_TYPE)
#define BIT_CLEAR_PRI_MASK_TYPE(x)			((x) & (~BITS_PRI_MASK_TYPE))
#define BIT_GET_PRI_MASK_TYPE(x)			(((x) >> BIT_SHIFT_PRI_MASK_TYPE) & BIT_MASK_PRI_MASK_TYPE)
#define BIT_SET_PRI_MASK_TYPE(x, v)			(BIT_CLEAR_PRI_MASK_TYPE(x) | BIT_PRI_MASK_TYPE(v))

#define BIT_OOB_V1					BIT(1)
#define BIT_ANT_SEL_V1					BIT(0)

/* 2 REG_RXCMD_0				(Offset 0x06D0) */

#define BIT_RXCMD_EN					BIT(31)

#define BIT_SHIFT_RXCMD_INFO				0
#define BIT_MASK_RXCMD_INFO				0x7fffffffL
#define BIT_RXCMD_INFO(x)				(((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO)
#define BITS_RXCMD_INFO				(BIT_MASK_RXCMD_INFO << BIT_SHIFT_RXCMD_INFO)
#define BIT_CLEAR_RXCMD_INFO(x)			((x) & (~BITS_RXCMD_INFO))
#define BIT_GET_RXCMD_INFO(x)				(((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO)
#define BIT_SET_RXCMD_INFO(x, v)			(BIT_CLEAR_RXCMD_INFO(x) | BIT_RXCMD_INFO(v))

/* 2 REG_RXCMD_1				(Offset 0x06D4) */

#define BIT_SHIFT_RXCMD_PRD				0
#define BIT_MASK_RXCMD_PRD				0xffff
#define BIT_RXCMD_PRD(x)				(((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD)
#define BITS_RXCMD_PRD					(BIT_MASK_RXCMD_PRD << BIT_SHIFT_RXCMD_PRD)
#define BIT_CLEAR_RXCMD_PRD(x)				((x) & (~BITS_RXCMD_PRD))
#define BIT_GET_RXCMD_PRD(x)				(((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD)
#define BIT_SET_RXCMD_PRD(x, v)			(BIT_CLEAR_RXCMD_PRD(x) | BIT_RXCMD_PRD(v))

/* 2 REG_RESP_TXINFO_CFG			(Offset 0x06D8) */

#define BIT_SHIFT_RESP_MFB				25
#define BIT_MASK_RESP_MFB				0x7f
#define BIT_RESP_MFB(x)				(((x) & BIT_MASK_RESP_MFB) << BIT_SHIFT_RESP_MFB)
#define BITS_RESP_MFB					(BIT_MASK_RESP_MFB << BIT_SHIFT_RESP_MFB)
#define BIT_CLEAR_RESP_MFB(x)				((x) & (~BITS_RESP_MFB))
#define BIT_GET_RESP_MFB(x)				(((x) >> BIT_SHIFT_RESP_MFB) & BIT_MASK_RESP_MFB)
#define BIT_SET_RESP_MFB(x, v)				(BIT_CLEAR_RESP_MFB(x) | BIT_RESP_MFB(v))

#define BIT_SHIFT_ANTINF_SEL				23
#define BIT_MASK_ANTINF_SEL				0x3
#define BIT_ANTINF_SEL(x)				(((x) & BIT_MASK_ANTINF_SEL) << BIT_SHIFT_ANTINF_SEL)
#define BITS_ANTINF_SEL				(BIT_MASK_ANTINF_SEL << BIT_SHIFT_ANTINF_SEL)
#define BIT_CLEAR_ANTINF_SEL(x)			((x) & (~BITS_ANTINF_SEL))
#define BIT_GET_ANTINF_SEL(x)				(((x) >> BIT_SHIFT_ANTINF_SEL) & BIT_MASK_ANTINF_SEL)
#define BIT_SET_ANTINF_SEL(x, v)			(BIT_CLEAR_ANTINF_SEL(x) | BIT_ANTINF_SEL(v))

#define BIT_SHIFT_ANTSEL_SEL				21
#define BIT_MASK_ANTSEL_SEL				0x3
#define BIT_ANTSEL_SEL(x)				(((x) & BIT_MASK_ANTSEL_SEL) << BIT_SHIFT_ANTSEL_SEL)
#define BITS_ANTSEL_SEL				(BIT_MASK_ANTSEL_SEL << BIT_SHIFT_ANTSEL_SEL)
#define BIT_CLEAR_ANTSEL_SEL(x)			((x) & (~BITS_ANTSEL_SEL))
#define BIT_GET_ANTSEL_SEL(x)				(((x) >> BIT_SHIFT_ANTSEL_SEL) & BIT_MASK_ANTSEL_SEL)
#define BIT_SET_ANTSEL_SEL(x, v)			(BIT_CLEAR_ANTSEL_SEL(x) | BIT_ANTSEL_SEL(v))

#define BIT_SHIFT_RESP_TXPOWER				18
#define BIT_MASK_RESP_TXPOWER				0x7
#define BIT_RESP_TXPOWER(x)				(((x) & BIT_MASK_RESP_TXPOWER) << BIT_SHIFT_RESP_TXPOWER)
#define BITS_RESP_TXPOWER				(BIT_MASK_RESP_TXPOWER << BIT_SHIFT_RESP_TXPOWER)
#define BIT_CLEAR_RESP_TXPOWER(x)			((x) & (~BITS_RESP_TXPOWER))
#define BIT_GET_RESP_TXPOWER(x)			(((x) >> BIT_SHIFT_RESP_TXPOWER) & BIT_MASK_RESP_TXPOWER)
#define BIT_SET_RESP_TXPOWER(x, v)			(BIT_CLEAR_RESP_TXPOWER(x) | BIT_RESP_TXPOWER(v))

#define BIT_SHIFT_RESP_TXANT				0
#define BIT_MASK_RESP_TXANT				0x3ffff
#define BIT_RESP_TXANT(x)				(((x) & BIT_MASK_RESP_TXANT) << BIT_SHIFT_RESP_TXANT)
#define BITS_RESP_TXANT				(BIT_MASK_RESP_TXANT << BIT_SHIFT_RESP_TXANT)
#define BIT_CLEAR_RESP_TXANT(x)			((x) & (~BITS_RESP_TXANT))
#define BIT_GET_RESP_TXANT(x)				(((x) >> BIT_SHIFT_RESP_TXANT) & BIT_MASK_RESP_TXANT)
#define BIT_SET_RESP_TXANT(x, v)			(BIT_CLEAR_RESP_TXANT(x) | BIT_RESP_TXANT(v))

/* 2 REG_BBPSF_CTRL				(Offset 0x06DC) */

#define BIT_WMAC_CSI_RATE_FORCE_EN			BIT(15)

#define BIT_SHIFT_WMAC_CSI_RSC_FORCE			13
#define BIT_MASK_WMAC_CSI_RSC_FORCE			0x3
#define BIT_WMAC_CSI_RSC_FORCE(x)			(((x) & BIT_MASK_WMAC_CSI_RSC_FORCE) << BIT_SHIFT_WMAC_CSI_RSC_FORCE)
#define BITS_WMAC_CSI_RSC_FORCE			(BIT_MASK_WMAC_CSI_RSC_FORCE << BIT_SHIFT_WMAC_CSI_RSC_FORCE)
#define BIT_CLEAR_WMAC_CSI_RSC_FORCE(x)		((x) & (~BITS_WMAC_CSI_RSC_FORCE))
#define BIT_GET_WMAC_CSI_RSC_FORCE(x)			(((x) >> BIT_SHIFT_WMAC_CSI_RSC_FORCE) & BIT_MASK_WMAC_CSI_RSC_FORCE)
#define BIT_SET_WMAC_CSI_RSC_FORCE(x, v)		(BIT_CLEAR_WMAC_CSI_RSC_FORCE(x) | BIT_WMAC_CSI_RSC_FORCE(v))

#define BIT_CSI_GID_SEL				BIT(12)
#define BIT_RDCSIMD_FLAG_TRIG_SEL			BIT(11)
#define BIT_NDPVLD_POS_RST_FFPTR_DIS_V1		BIT(10)
#define BIT_NDPVLD_PROTECT_RDRDY_DIS			BIT(9)
#define BIT_CSIRD_EMPTY_APPZERO			BIT(8)
#define BIT_WMC_CSI_RATE_FB_EN				BIT(7)
#define BIT_RXFIFO_WRPTR_WO_CHKSUM			BIT(6)

/* 2 REG_RESP_TXINFO_RATE			(Offset 0x06DE) */

#define BIT_CTL_IDLE_CLR_CSI_RPT_V1			BIT(15)
#define BIT_USE_NDPARATE				BIT(14)

#define BIT_SHIFT_WMAC_CSI_RATE			8
#define BIT_MASK_WMAC_CSI_RATE				0x3f
#define BIT_WMAC_CSI_RATE(x)				(((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE)
#define BITS_WMAC_CSI_RATE				(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE)
#define BIT_CLEAR_WMAC_CSI_RATE(x)			((x) & (~BITS_WMAC_CSI_RATE))
#define BIT_GET_WMAC_CSI_RATE(x)			(((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE)
#define BIT_SET_WMAC_CSI_RATE(x, v)			(BIT_CLEAR_WMAC_CSI_RATE(x) | BIT_WMAC_CSI_RATE(v))

#define BIT_SHIFT_RESP_TXRATE				0
#define BIT_MASK_RESP_TXRATE				0xff
#define BIT_RESP_TXRATE(x)				(((x) & BIT_MASK_RESP_TXRATE) << BIT_SHIFT_RESP_TXRATE)
#define BITS_RESP_TXRATE				(BIT_MASK_RESP_TXRATE << BIT_SHIFT_RESP_TXRATE)
#define BIT_CLEAR_RESP_TXRATE(x)			((x) & (~BITS_RESP_TXRATE))
#define BIT_GET_RESP_TXRATE(x)				(((x) >> BIT_SHIFT_RESP_TXRATE) & BIT_MASK_RESP_TXRATE)
#define BIT_SET_RESP_TXRATE(x, v)			(BIT_CLEAR_RESP_TXRATE(x) | BIT_RESP_TXRATE(v))

/* 2 REG_P2P_RX_BCN_NOA			(Offset 0x06E0) */

#define BIT_P2P_NOA_PARSER_EN				BIT(15)

#define BIT_SHIFT_P2P_BSSID_SEL_V1			12
#define BIT_MASK_P2P_BSSID_SEL_V1			0x7
#define BIT_P2P_BSSID_SEL_V1(x)			(((x) & BIT_MASK_P2P_BSSID_SEL_V1) << BIT_SHIFT_P2P_BSSID_SEL_V1)
#define BITS_P2P_BSSID_SEL_V1				(BIT_MASK_P2P_BSSID_SEL_V1 << BIT_SHIFT_P2P_BSSID_SEL_V1)
#define BIT_CLEAR_P2P_BSSID_SEL_V1(x)			((x) & (~BITS_P2P_BSSID_SEL_V1))
#define BIT_GET_P2P_BSSID_SEL_V1(x)			(((x) >> BIT_SHIFT_P2P_BSSID_SEL_V1) & BIT_MASK_P2P_BSSID_SEL_V1)
#define BIT_SET_P2P_BSSID_SEL_V1(x, v)			(BIT_CLEAR_P2P_BSSID_SEL_V1(x) | BIT_P2P_BSSID_SEL_V1(v))

#define BIT_SHIFT_P2P_OUI_TYPE				0
#define BIT_MASK_P2P_OUI_TYPE				0xff
#define BIT_P2P_OUI_TYPE(x)				(((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE)
#define BITS_P2P_OUI_TYPE				(BIT_MASK_P2P_OUI_TYPE << BIT_SHIFT_P2P_OUI_TYPE)
#define BIT_CLEAR_P2P_OUI_TYPE(x)			((x) & (~BITS_P2P_OUI_TYPE))
#define BIT_GET_P2P_OUI_TYPE(x)			(((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE)
#define BIT_SET_P2P_OUI_TYPE(x, v)			(BIT_CLEAR_P2P_OUI_TYPE(x) | BIT_P2P_OUI_TYPE(v))

/* 2 REG_ASSOCIATED_BFMER0_INFO		(Offset 0x06E4) */

#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1		0
#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1		0xffffffffL
#define BIT_R_WMAC_SOUNDING_RXADD_R0_V1(x)		(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1)
#define BITS_R_WMAC_SOUNDING_RXADD_R0_V1		(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1)
#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x)	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_V1))
#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_V1(x)	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_V1) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_V1)
#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_V1(x, v)	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_V1(x) | BIT_R_WMAC_SOUNDING_RXADD_R0_V1(v))

/* 2 REG_SOUNDING_CFG1			(Offset 0x06E8) */

#define BIT_SHIFT_R_WMAC_TXCSI_AID0			16
#define BIT_MASK_R_WMAC_TXCSI_AID0			0x1ff
#define BIT_R_WMAC_TXCSI_AID0(x)			(((x) & BIT_MASK_R_WMAC_TXCSI_AID0) << BIT_SHIFT_R_WMAC_TXCSI_AID0)
#define BITS_R_WMAC_TXCSI_AID0				(BIT_MASK_R_WMAC_TXCSI_AID0 << BIT_SHIFT_R_WMAC_TXCSI_AID0)
#define BIT_CLEAR_R_WMAC_TXCSI_AID0(x)			((x) & (~BITS_R_WMAC_TXCSI_AID0))
#define BIT_GET_R_WMAC_TXCSI_AID0(x)			(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0) & BIT_MASK_R_WMAC_TXCSI_AID0)
#define BIT_SET_R_WMAC_TXCSI_AID0(x, v)		(BIT_CLEAR_R_WMAC_TXCSI_AID0(x) | BIT_R_WMAC_TXCSI_AID0(v))

#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H		0
#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H		0xffff
#define BIT_R_WMAC_SOUNDING_RXADD_R0_H(x)		(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H)
#define BITS_R_WMAC_SOUNDING_RXADD_R0_H		(BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H)
#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H(x)	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R0_H))
#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_H(x)		(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_H) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_H)
#define BIT_SET_R_WMAC_SOUNDING_RXADD_R0_H(x, v)	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R0_H(x) | BIT_R_WMAC_SOUNDING_RXADD_R0_H(v))

/* 2 REG_SOUNDING_CFG2			(Offset 0x06EC) */

#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2		0
#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2		0xffffffffL
#define BIT_R_WMAC_SOUNDING_RXADD_R1_V2(x)		(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2)
#define BITS_R_WMAC_SOUNDING_RXADD_R1_V2		(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2)
#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V2(x)	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_V2))
#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_V2(x)	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_V2) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_V2)
#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_V2(x, v)	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_V2(x) | BIT_R_WMAC_SOUNDING_RXADD_R1_V2(v))

/* 2 REG_SOUNDING_CFG3			(Offset 0x06F0) */

#define BIT_SHIFT_R_WMAC_TXCSI_AID1			16
#define BIT_MASK_R_WMAC_TXCSI_AID1			0x1ff
#define BIT_R_WMAC_TXCSI_AID1(x)			(((x) & BIT_MASK_R_WMAC_TXCSI_AID1) << BIT_SHIFT_R_WMAC_TXCSI_AID1)
#define BITS_R_WMAC_TXCSI_AID1				(BIT_MASK_R_WMAC_TXCSI_AID1 << BIT_SHIFT_R_WMAC_TXCSI_AID1)
#define BIT_CLEAR_R_WMAC_TXCSI_AID1(x)			((x) & (~BITS_R_WMAC_TXCSI_AID1))
#define BIT_GET_R_WMAC_TXCSI_AID1(x)			(((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1) & BIT_MASK_R_WMAC_TXCSI_AID1)
#define BIT_SET_R_WMAC_TXCSI_AID1(x, v)		(BIT_CLEAR_R_WMAC_TXCSI_AID1(x) | BIT_R_WMAC_TXCSI_AID1(v))

#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2	0
#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2	0xffff
#define BIT_R_WMAC_SOUNDING_RXADD_R1_H_V2(x)		(((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2)
#define BITS_R_WMAC_SOUNDING_RXADD_R1_H_V2		(BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2)
#define BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V2(x)	((x) & (~BITS_R_WMAC_SOUNDING_RXADD_R1_H_V2))
#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_H_V2(x)	(((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_H_V2) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_H_V2)
#define BIT_SET_R_WMAC_SOUNDING_RXADD_R1_H_V2(x, v)	(BIT_CLEAR_R_WMAC_SOUNDING_RXADD_R1_H_V2(x) | BIT_R_WMAC_SOUNDING_RXADD_R1_H_V2(v))

/* 2 REG_SOUNDING_CFG0			(Offset 0x06F4) */

#define BIT_SHIFT_R_WMAC_BFINFO_20M_1			16
#define BIT_MASK_R_WMAC_BFINFO_20M_1			0xfff
#define BIT_R_WMAC_BFINFO_20M_1(x)			(((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1)
#define BITS_R_WMAC_BFINFO_20M_1			(BIT_MASK_R_WMAC_BFINFO_20M_1 << BIT_SHIFT_R_WMAC_BFINFO_20M_1)
#define BIT_CLEAR_R_WMAC_BFINFO_20M_1(x)		((x) & (~BITS_R_WMAC_BFINFO_20M_1))
#define BIT_GET_R_WMAC_BFINFO_20M_1(x)			(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1)
#define BIT_SET_R_WMAC_BFINFO_20M_1(x, v)		(BIT_CLEAR_R_WMAC_BFINFO_20M_1(x) | BIT_R_WMAC_BFINFO_20M_1(v))

#define BIT_SHIFT_R_WMAC_BFINFO_20M_0			0
#define BIT_MASK_R_WMAC_BFINFO_20M_0			0xfff
#define BIT_R_WMAC_BFINFO_20M_0(x)			(((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0)
#define BITS_R_WMAC_BFINFO_20M_0			(BIT_MASK_R_WMAC_BFINFO_20M_0 << BIT_SHIFT_R_WMAC_BFINFO_20M_0)
#define BIT_CLEAR_R_WMAC_BFINFO_20M_0(x)		((x) & (~BITS_R_WMAC_BFINFO_20M_0))
#define BIT_GET_R_WMAC_BFINFO_20M_0(x)			(((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0)
#define BIT_SET_R_WMAC_BFINFO_20M_0(x, v)		(BIT_CLEAR_R_WMAC_BFINFO_20M_0(x) | BIT_R_WMAC_BFINFO_20M_0(v))

/* 2 REG_ANTCD_INFO				(Offset 0x06F8) */

#define BIT_SHIFT_WMAC_RESP_ANTD			12
#define BIT_MASK_WMAC_RESP_ANTD			0xf
#define BIT_WMAC_RESP_ANTD(x)				(((x) & BIT_MASK_WMAC_RESP_ANTD) << BIT_SHIFT_WMAC_RESP_ANTD)
#define BITS_WMAC_RESP_ANTD				(BIT_MASK_WMAC_RESP_ANTD << BIT_SHIFT_WMAC_RESP_ANTD)
#define BIT_CLEAR_WMAC_RESP_ANTD(x)			((x) & (~BITS_WMAC_RESP_ANTD))
#define BIT_GET_WMAC_RESP_ANTD(x)			(((x) >> BIT_SHIFT_WMAC_RESP_ANTD) & BIT_MASK_WMAC_RESP_ANTD)
#define BIT_SET_WMAC_RESP_ANTD(x, v)			(BIT_CLEAR_WMAC_RESP_ANTD(x) | BIT_WMAC_RESP_ANTD(v))

#define BIT_SHIFT_WMAC_RESP_ANTC			8
#define BIT_MASK_WMAC_RESP_ANTC			0xf
#define BIT_WMAC_RESP_ANTC(x)				(((x) & BIT_MASK_WMAC_RESP_ANTC) << BIT_SHIFT_WMAC_RESP_ANTC)
#define BITS_WMAC_RESP_ANTC				(BIT_MASK_WMAC_RESP_ANTC << BIT_SHIFT_WMAC_RESP_ANTC)
#define BIT_CLEAR_WMAC_RESP_ANTC(x)			((x) & (~BITS_WMAC_RESP_ANTC))
#define BIT_GET_WMAC_RESP_ANTC(x)			(((x) >> BIT_SHIFT_WMAC_RESP_ANTC) & BIT_MASK_WMAC_RESP_ANTC)
#define BIT_SET_WMAC_RESP_ANTC(x, v)			(BIT_CLEAR_WMAC_RESP_ANTC(x) | BIT_WMAC_RESP_ANTC(v))

#define BIT_SHIFT_WMAC_RESP_ANTB			4
#define BIT_MASK_WMAC_RESP_ANTB			0xf
#define BIT_WMAC_RESP_ANTB(x)				(((x) & BIT_MASK_WMAC_RESP_ANTB) << BIT_SHIFT_WMAC_RESP_ANTB)
#define BITS_WMAC_RESP_ANTB				(BIT_MASK_WMAC_RESP_ANTB << BIT_SHIFT_WMAC_RESP_ANTB)
#define BIT_CLEAR_WMAC_RESP_ANTB(x)			((x) & (~BITS_WMAC_RESP_ANTB))
#define BIT_GET_WMAC_RESP_ANTB(x)			(((x) >> BIT_SHIFT_WMAC_RESP_ANTB) & BIT_MASK_WMAC_RESP_ANTB)
#define BIT_SET_WMAC_RESP_ANTB(x, v)			(BIT_CLEAR_WMAC_RESP_ANTB(x) | BIT_WMAC_RESP_ANTB(v))

#define BIT_SHIFT_WMAC_RESP_ANTA			0
#define BIT_MASK_WMAC_RESP_ANTA			0xf
#define BIT_WMAC_RESP_ANTA(x)				(((x) & BIT_MASK_WMAC_RESP_ANTA) << BIT_SHIFT_WMAC_RESP_ANTA)
#define BITS_WMAC_RESP_ANTA				(BIT_MASK_WMAC_RESP_ANTA << BIT_SHIFT_WMAC_RESP_ANTA)
#define BIT_CLEAR_WMAC_RESP_ANTA(x)			((x) & (~BITS_WMAC_RESP_ANTA))
#define BIT_GET_WMAC_RESP_ANTA(x)			(((x) >> BIT_SHIFT_WMAC_RESP_ANTA) & BIT_MASK_WMAC_RESP_ANTA)
#define BIT_SET_WMAC_RESP_ANTA(x, v)			(BIT_CLEAR_WMAC_RESP_ANTA(x) | BIT_WMAC_RESP_ANTA(v))

/* 2 REG_CSI_PTR				(Offset 0x06FC) */

#define BIT_SHIFT_CSI_RADDR_LATCH_V2			16
#define BIT_MASK_CSI_RADDR_LATCH_V2			0xffff
#define BIT_CSI_RADDR_LATCH_V2(x)			(((x) & BIT_MASK_CSI_RADDR_LATCH_V2) << BIT_SHIFT_CSI_RADDR_LATCH_V2)
#define BITS_CSI_RADDR_LATCH_V2			(BIT_MASK_CSI_RADDR_LATCH_V2 << BIT_SHIFT_CSI_RADDR_LATCH_V2)
#define BIT_CLEAR_CSI_RADDR_LATCH_V2(x)		((x) & (~BITS_CSI_RADDR_LATCH_V2))
#define BIT_GET_CSI_RADDR_LATCH_V2(x)			(((x) >> BIT_SHIFT_CSI_RADDR_LATCH_V2) & BIT_MASK_CSI_RADDR_LATCH_V2)
#define BIT_SET_CSI_RADDR_LATCH_V2(x, v)		(BIT_CLEAR_CSI_RADDR_LATCH_V2(x) | BIT_CSI_RADDR_LATCH_V2(v))

#define BIT_SHIFT_CSI_WADDR_LATCH_V2			0
#define BIT_MASK_CSI_WADDR_LATCH_V2			0xffff
#define BIT_CSI_WADDR_LATCH_V2(x)			(((x) & BIT_MASK_CSI_WADDR_LATCH_V2) << BIT_SHIFT_CSI_WADDR_LATCH_V2)
#define BITS_CSI_WADDR_LATCH_V2			(BIT_MASK_CSI_WADDR_LATCH_V2 << BIT_SHIFT_CSI_WADDR_LATCH_V2)
#define BIT_CLEAR_CSI_WADDR_LATCH_V2(x)		((x) & (~BITS_CSI_WADDR_LATCH_V2))
#define BIT_GET_CSI_WADDR_LATCH_V2(x)			(((x) >> BIT_SHIFT_CSI_WADDR_LATCH_V2) & BIT_MASK_CSI_WADDR_LATCH_V2)
#define BIT_SET_CSI_WADDR_LATCH_V2(x, v)		(BIT_CLEAR_CSI_WADDR_LATCH_V2(x) | BIT_CSI_WADDR_LATCH_V2(v))

/* 2 REG_MACID1				(Offset 0x0700) */

#define BIT_SHIFT_MACID1_0				0
#define BIT_MASK_MACID1_0				0xffffffffL
#define BIT_MACID1_0(x)				(((x) & BIT_MASK_MACID1_0) << BIT_SHIFT_MACID1_0)
#define BITS_MACID1_0					(BIT_MASK_MACID1_0 << BIT_SHIFT_MACID1_0)
#define BIT_CLEAR_MACID1_0(x)				((x) & (~BITS_MACID1_0))
#define BIT_GET_MACID1_0(x)				(((x) >> BIT_SHIFT_MACID1_0) & BIT_MASK_MACID1_0)
#define BIT_SET_MACID1_0(x, v)				(BIT_CLEAR_MACID1_0(x) | BIT_MACID1_0(v))

/* 2 REG_MACID1_1				(Offset 0x0704) */

#define BIT_SHIFT_MACID1_1				0
#define BIT_MASK_MACID1_1				0xffff
#define BIT_MACID1_1(x)				(((x) & BIT_MASK_MACID1_1) << BIT_SHIFT_MACID1_1)
#define BITS_MACID1_1					(BIT_MASK_MACID1_1 << BIT_SHIFT_MACID1_1)
#define BIT_CLEAR_MACID1_1(x)				((x) & (~BITS_MACID1_1))
#define BIT_GET_MACID1_1(x)				(((x) >> BIT_SHIFT_MACID1_1) & BIT_MASK_MACID1_1)
#define BIT_SET_MACID1_1(x, v)				(BIT_CLEAR_MACID1_1(x) | BIT_MACID1_1(v))

/* 2 REG_BSSID1				(Offset 0x0708) */

#define BIT_SHIFT_BSSID1_0				0
#define BIT_MASK_BSSID1_0				0xffffffffL
#define BIT_BSSID1_0(x)				(((x) & BIT_MASK_BSSID1_0) << BIT_SHIFT_BSSID1_0)
#define BITS_BSSID1_0					(BIT_MASK_BSSID1_0 << BIT_SHIFT_BSSID1_0)
#define BIT_CLEAR_BSSID1_0(x)				((x) & (~BITS_BSSID1_0))
#define BIT_GET_BSSID1_0(x)				(((x) >> BIT_SHIFT_BSSID1_0) & BIT_MASK_BSSID1_0)
#define BIT_SET_BSSID1_0(x, v)				(BIT_CLEAR_BSSID1_0(x) | BIT_BSSID1_0(v))

/* 2 REG_BSSID1_1				(Offset 0x070C) */

#define BIT_SHIFT_BSSID1_1				0
#define BIT_MASK_BSSID1_1				0xffff
#define BIT_BSSID1_1(x)				(((x) & BIT_MASK_BSSID1_1) << BIT_SHIFT_BSSID1_1)
#define BITS_BSSID1_1					(BIT_MASK_BSSID1_1 << BIT_SHIFT_BSSID1_1)
#define BIT_CLEAR_BSSID1_1(x)				((x) & (~BITS_BSSID1_1))
#define BIT_GET_BSSID1_1(x)				(((x) >> BIT_SHIFT_BSSID1_1) & BIT_MASK_BSSID1_1)
#define BIT_SET_BSSID1_1(x, v)				(BIT_CLEAR_BSSID1_1(x) | BIT_BSSID1_1(v))

/* 2 REG_BCN_PSR_RPT1			(Offset 0x0710) */

#define BIT_SHIFT_DTIM_CNT1				24
#define BIT_MASK_DTIM_CNT1				0xff
#define BIT_DTIM_CNT1(x)				(((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1)
#define BITS_DTIM_CNT1					(BIT_MASK_DTIM_CNT1 << BIT_SHIFT_DTIM_CNT1)
#define BIT_CLEAR_DTIM_CNT1(x)				((x) & (~BITS_DTIM_CNT1))
#define BIT_GET_DTIM_CNT1(x)				(((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1)
#define BIT_SET_DTIM_CNT1(x, v)			(BIT_CLEAR_DTIM_CNT1(x) | BIT_DTIM_CNT1(v))

#define BIT_SHIFT_DTIM_PERIOD1				16
#define BIT_MASK_DTIM_PERIOD1				0xff
#define BIT_DTIM_PERIOD1(x)				(((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1)
#define BITS_DTIM_PERIOD1				(BIT_MASK_DTIM_PERIOD1 << BIT_SHIFT_DTIM_PERIOD1)
#define BIT_CLEAR_DTIM_PERIOD1(x)			((x) & (~BITS_DTIM_PERIOD1))
#define BIT_GET_DTIM_PERIOD1(x)			(((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1)
#define BIT_SET_DTIM_PERIOD1(x, v)			(BIT_CLEAR_DTIM_PERIOD1(x) | BIT_DTIM_PERIOD1(v))

#define BIT_DTIM1					BIT(15)
#define BIT_TIM1					BIT(14)

#define BIT_SHIFT_PS_AID_1				0
#define BIT_MASK_PS_AID_1				0x7ff
#define BIT_PS_AID_1(x)				(((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1)
#define BITS_PS_AID_1					(BIT_MASK_PS_AID_1 << BIT_SHIFT_PS_AID_1)
#define BIT_CLEAR_PS_AID_1(x)				((x) & (~BITS_PS_AID_1))
#define BIT_GET_PS_AID_1(x)				(((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1)
#define BIT_SET_PS_AID_1(x, v)				(BIT_CLEAR_PS_AID_1(x) | BIT_PS_AID_1(v))

/* 2 REG_ASSOCIATED_BFMEE_SEL		(Offset 0x0714) */

#define BIT_TXUSER_ID1					BIT(25)

#define BIT_SHIFT_AID1					16
#define BIT_MASK_AID1					0x1ff
#define BIT_AID1(x)					(((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1)
#define BITS_AID1					(BIT_MASK_AID1 << BIT_SHIFT_AID1)
#define BIT_CLEAR_AID1(x)				((x) & (~BITS_AID1))
#define BIT_GET_AID1(x)				(((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1)
#define BIT_SET_AID1(x, v)				(BIT_CLEAR_AID1(x) | BIT_AID1(v))

#define BIT_TXUSER_ID0					BIT(9)

#define BIT_SHIFT_AID0					0
#define BIT_MASK_AID0					0x1ff
#define BIT_AID0(x)					(((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0)
#define BITS_AID0					(BIT_MASK_AID0 << BIT_SHIFT_AID0)
#define BIT_CLEAR_AID0(x)				((x) & (~BITS_AID0))
#define BIT_GET_AID0(x)				(((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0)
#define BIT_SET_AID0(x, v)				(BIT_CLEAR_AID0(x) | BIT_AID0(v))

/* 2 REG_SND_PTCL_CTRL			(Offset 0x0718) */

#define BIT_SHIFT_NDP_RX_STANDBY_TIMER			24
#define BIT_MASK_NDP_RX_STANDBY_TIMER			0xff
#define BIT_NDP_RX_STANDBY_TIMER(x)			(((x) & BIT_MASK_NDP_RX_STANDBY_TIMER) << BIT_SHIFT_NDP_RX_STANDBY_TIMER)
#define BITS_NDP_RX_STANDBY_TIMER			(BIT_MASK_NDP_RX_STANDBY_TIMER << BIT_SHIFT_NDP_RX_STANDBY_TIMER)
#define BIT_CLEAR_NDP_RX_STANDBY_TIMER(x)		((x) & (~BITS_NDP_RX_STANDBY_TIMER))
#define BIT_GET_NDP_RX_STANDBY_TIMER(x)		(((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) & BIT_MASK_NDP_RX_STANDBY_TIMER)
#define BIT_SET_NDP_RX_STANDBY_TIMER(x, v)		(BIT_CLEAR_NDP_RX_STANDBY_TIMER(x) | BIT_NDP_RX_STANDBY_TIMER(v))

#define BIT_R_WMAC_CHK_RPTPOLL_A2_DIS			BIT(23)
#define BIT_R_WMAC_CHK_UCNDPA_A2_DIS			BIT(22)

#define BIT_SHIFT_CSI_RPT_OFFSET_HT_V1			16
#define BIT_MASK_CSI_RPT_OFFSET_HT_V1			0x3f
#define BIT_CSI_RPT_OFFSET_HT_V1(x)			(((x) & BIT_MASK_CSI_RPT_OFFSET_HT_V1) << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1)
#define BITS_CSI_RPT_OFFSET_HT_V1			(BIT_MASK_CSI_RPT_OFFSET_HT_V1 << BIT_SHIFT_CSI_RPT_OFFSET_HT_V1)
#define BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x)		((x) & (~BITS_CSI_RPT_OFFSET_HT_V1))
#define BIT_GET_CSI_RPT_OFFSET_HT_V1(x)		(((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_V1) & BIT_MASK_CSI_RPT_OFFSET_HT_V1)
#define BIT_SET_CSI_RPT_OFFSET_HT_V1(x, v)		(BIT_CLEAR_CSI_RPT_OFFSET_HT_V1(x) | BIT_CSI_RPT_OFFSET_HT_V1(v))

#define BIT_R_WMAC_OFFSET_RPTPOLL_EN			BIT(15)
#define BIT_R_WMAC_CSI_CHKSUM_DIS			BIT(14)

#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1		8
#define BIT_MASK_R_WMAC_VHT_CATEGORY_V1		0x3f
#define BIT_R_WMAC_VHT_CATEGORY_V1(x)			(((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1)
#define BITS_R_WMAC_VHT_CATEGORY_V1			(BIT_MASK_R_WMAC_VHT_CATEGORY_V1 << BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1)
#define BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x)		((x) & (~BITS_R_WMAC_VHT_CATEGORY_V1))
#define BIT_GET_R_WMAC_VHT_CATEGORY_V1(x)		(((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_V1) & BIT_MASK_R_WMAC_VHT_CATEGORY_V1)
#define BIT_SET_R_WMAC_VHT_CATEGORY_V1(x, v)		(BIT_CLEAR_R_WMAC_VHT_CATEGORY_V1(x) | BIT_R_WMAC_VHT_CATEGORY_V1(v))

#define BIT_R_WMAC_USE_NSTS				BIT(7)
#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC		BIT(6)
#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC		BIT(5)
#define BIT_R_WMAC_BFPARAM_SEL				BIT(4)
#define BIT_R_WMAC_CSISEQ_SEL				BIT(3)
#define BIT_R_WMAC_CSI_WITHHTC_EN			BIT(2)
#define BIT_R_WMAC_HT_NDPA_EN				BIT(1)
#define BIT_R_WMAC_VHT_NDPA_EN				BIT(0)

/* 2 REG_BEAMFORM_STATUS			(Offset 0x071C) */

#define BIT_WRITE_ENABLE				BIT(31)
#define BIT_WMAC_CHECK_SOUNDING_SEQ			BIT(30)

#define BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD		1
#define BIT_MASK_VHTHT_MIMO_CTRL_FIELD			0xffffff
#define BIT_VHTHT_MIMO_CTRL_FIELD(x)			(((x) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD) << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD)
#define BITS_VHTHT_MIMO_CTRL_FIELD			(BIT_MASK_VHTHT_MIMO_CTRL_FIELD << BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD)
#define BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x)		((x) & (~BITS_VHTHT_MIMO_CTRL_FIELD))
#define BIT_GET_VHTHT_MIMO_CTRL_FIELD(x)		(((x) >> BIT_SHIFT_VHTHT_MIMO_CTRL_FIELD) & BIT_MASK_VHTHT_MIMO_CTRL_FIELD)
#define BIT_SET_VHTHT_MIMO_CTRL_FIELD(x, v)		(BIT_CLEAR_VHTHT_MIMO_CTRL_FIELD(x) | BIT_VHTHT_MIMO_CTRL_FIELD(v))

#define BIT_CSI_INTRRUPT_STATUS			BIT(0)

/* 2 REG_NSARP_CFG				(Offset 0x0720) */

#define BIT_NSARP_RESPEN				BIT(15)
#define BIT_NSARP_PARP					BIT(9)
#define BIT_NSARP_RIPV6				BIT(8)

#define BIT_SHIFT_NSARP_MODEN				6
#define BIT_MASK_NSARP_MODEN				0x3
#define BIT_NSARP_MODEN(x)				(((x) & BIT_MASK_NSARP_MODEN) << BIT_SHIFT_NSARP_MODEN)
#define BITS_NSARP_MODEN				(BIT_MASK_NSARP_MODEN << BIT_SHIFT_NSARP_MODEN)
#define BIT_CLEAR_NSARP_MODEN(x)			((x) & (~BITS_NSARP_MODEN))
#define BIT_GET_NSARP_MODEN(x)				(((x) >> BIT_SHIFT_NSARP_MODEN) & BIT_MASK_NSARP_MODEN)
#define BIT_SET_NSARP_MODEN(x, v)			(BIT_CLEAR_NSARP_MODEN(x) | BIT_NSARP_MODEN(v))

#define BIT_SHIFT_NSARP_RSPFTP				4
#define BIT_MASK_NSARP_RSPFTP				0x3
#define BIT_NSARP_RSPFTP(x)				(((x) & BIT_MASK_NSARP_RSPFTP) << BIT_SHIFT_NSARP_RSPFTP)
#define BITS_NSARP_RSPFTP				(BIT_MASK_NSARP_RSPFTP << BIT_SHIFT_NSARP_RSPFTP)
#define BIT_CLEAR_NSARP_RSPFTP(x)			((x) & (~BITS_NSARP_RSPFTP))
#define BIT_GET_NSARP_RSPFTP(x)			(((x) >> BIT_SHIFT_NSARP_RSPFTP) & BIT_MASK_NSARP_RSPFTP)
#define BIT_SET_NSARP_RSPFTP(x, v)			(BIT_CLEAR_NSARP_RSPFTP(x) | BIT_NSARP_RSPFTP(v))

#define BIT_SHIFT_NSARP_RSPSEC				0
#define BIT_MASK_NSARP_RSPSEC				0xf
#define BIT_NSARP_RSPSEC(x)				(((x) & BIT_MASK_NSARP_RSPSEC) << BIT_SHIFT_NSARP_RSPSEC)
#define BITS_NSARP_RSPSEC				(BIT_MASK_NSARP_RSPSEC << BIT_SHIFT_NSARP_RSPSEC)
#define BIT_CLEAR_NSARP_RSPSEC(x)			((x) & (~BITS_NSARP_RSPSEC))
#define BIT_GET_NSARP_RSPSEC(x)			(((x) >> BIT_SHIFT_NSARP_RSPSEC) & BIT_MASK_NSARP_RSPSEC)
#define BIT_SET_NSARP_RSPSEC(x, v)			(BIT_CLEAR_NSARP_RSPSEC(x) | BIT_NSARP_RSPSEC(v))

/* 2 REG_BEAMFORMING_INFO_NSARP		(Offset 0x072C) */

#define BIT_SHIFT_UPD_BFMEE_USERID			13
#define BIT_MASK_UPD_BFMEE_USERID			0x7
#define BIT_UPD_BFMEE_USERID(x)			(((x) & BIT_MASK_UPD_BFMEE_USERID) << BIT_SHIFT_UPD_BFMEE_USERID)
#define BITS_UPD_BFMEE_USERID				(BIT_MASK_UPD_BFMEE_USERID << BIT_SHIFT_UPD_BFMEE_USERID)
#define BIT_CLEAR_UPD_BFMEE_USERID(x)			((x) & (~BITS_UPD_BFMEE_USERID))
#define BIT_GET_UPD_BFMEE_USERID(x)			(((x) >> BIT_SHIFT_UPD_BFMEE_USERID) & BIT_MASK_UPD_BFMEE_USERID)
#define BIT_SET_UPD_BFMEE_USERID(x, v)			(BIT_CLEAR_UPD_BFMEE_USERID(x) | BIT_UPD_BFMEE_USERID(v))

#define BIT_UPD_BFMEE_FBTP				BIT(12)

#define BIT_SHIFT_UPD_BFMEE_BW				10
#define BIT_MASK_UPD_BFMEE_BW				0x3
#define BIT_UPD_BFMEE_BW(x)				(((x) & BIT_MASK_UPD_BFMEE_BW) << BIT_SHIFT_UPD_BFMEE_BW)
#define BITS_UPD_BFMEE_BW				(BIT_MASK_UPD_BFMEE_BW << BIT_SHIFT_UPD_BFMEE_BW)
#define BIT_CLEAR_UPD_BFMEE_BW(x)			((x) & (~BITS_UPD_BFMEE_BW))
#define BIT_GET_UPD_BFMEE_BW(x)			(((x) >> BIT_SHIFT_UPD_BFMEE_BW) & BIT_MASK_UPD_BFMEE_BW)
#define BIT_SET_UPD_BFMEE_BW(x, v)			(BIT_CLEAR_UPD_BFMEE_BW(x) | BIT_UPD_BFMEE_BW(v))

#define BIT_SHIFT_UPD_BFMEE_CB				8
#define BIT_MASK_UPD_BFMEE_CB				0x3
#define BIT_UPD_BFMEE_CB(x)				(((x) & BIT_MASK_UPD_BFMEE_CB) << BIT_SHIFT_UPD_BFMEE_CB)
#define BITS_UPD_BFMEE_CB				(BIT_MASK_UPD_BFMEE_CB << BIT_SHIFT_UPD_BFMEE_CB)
#define BIT_CLEAR_UPD_BFMEE_CB(x)			((x) & (~BITS_UPD_BFMEE_CB))
#define BIT_GET_UPD_BFMEE_CB(x)			(((x) >> BIT_SHIFT_UPD_BFMEE_CB) & BIT_MASK_UPD_BFMEE_CB)
#define BIT_SET_UPD_BFMEE_CB(x, v)			(BIT_CLEAR_UPD_BFMEE_CB(x) | BIT_UPD_BFMEE_CB(v))

#define BIT_SHIFT_UPD_BFMEE_NG				6
#define BIT_MASK_UPD_BFMEE_NG				0x3
#define BIT_UPD_BFMEE_NG(x)				(((x) & BIT_MASK_UPD_BFMEE_NG) << BIT_SHIFT_UPD_BFMEE_NG)
#define BITS_UPD_BFMEE_NG				(BIT_MASK_UPD_BFMEE_NG << BIT_SHIFT_UPD_BFMEE_NG)
#define BIT_CLEAR_UPD_BFMEE_NG(x)			((x) & (~BITS_UPD_BFMEE_NG))
#define BIT_GET_UPD_BFMEE_NG(x)			(((x) >> BIT_SHIFT_UPD_BFMEE_NG) & BIT_MASK_UPD_BFMEE_NG)
#define BIT_SET_UPD_BFMEE_NG(x, v)			(BIT_CLEAR_UPD_BFMEE_NG(x) | BIT_UPD_BFMEE_NG(v))

#define BIT_SHIFT_UPD_BFMEE_NR				3
#define BIT_MASK_UPD_BFMEE_NR				0x7
#define BIT_UPD_BFMEE_NR(x)				(((x) & BIT_MASK_UPD_BFMEE_NR) << BIT_SHIFT_UPD_BFMEE_NR)
#define BITS_UPD_BFMEE_NR				(BIT_MASK_UPD_BFMEE_NR << BIT_SHIFT_UPD_BFMEE_NR)
#define BIT_CLEAR_UPD_BFMEE_NR(x)			((x) & (~BITS_UPD_BFMEE_NR))
#define BIT_GET_UPD_BFMEE_NR(x)			(((x) >> BIT_SHIFT_UPD_BFMEE_NR) & BIT_MASK_UPD_BFMEE_NR)
#define BIT_SET_UPD_BFMEE_NR(x, v)			(BIT_CLEAR_UPD_BFMEE_NR(x) | BIT_UPD_BFMEE_NR(v))

#define BIT_SHIFT_UPD_BFMEE_NC				0
#define BIT_MASK_UPD_BFMEE_NC				0x7
#define BIT_UPD_BFMEE_NC(x)				(((x) & BIT_MASK_UPD_BFMEE_NC) << BIT_SHIFT_UPD_BFMEE_NC)
#define BITS_UPD_BFMEE_NC				(BIT_MASK_UPD_BFMEE_NC << BIT_SHIFT_UPD_BFMEE_NC)
#define BIT_CLEAR_UPD_BFMEE_NC(x)			((x) & (~BITS_UPD_BFMEE_NC))
#define BIT_GET_UPD_BFMEE_NC(x)			(((x) >> BIT_SHIFT_UPD_BFMEE_NC) & BIT_MASK_UPD_BFMEE_NC)
#define BIT_SET_UPD_BFMEE_NC(x, v)			(BIT_CLEAR_UPD_BFMEE_NC(x) | BIT_UPD_BFMEE_NC(v))

/* 2 REG_IPV6_0				(Offset 0x0730) */

#define BIT_SHIFT_IPV6_MYIPAD_0			0
#define BIT_MASK_IPV6_MYIPAD_0				0xffffffffL
#define BIT_IPV6_MYIPAD_0(x)				(((x) & BIT_MASK_IPV6_MYIPAD_0) << BIT_SHIFT_IPV6_MYIPAD_0)
#define BITS_IPV6_MYIPAD_0				(BIT_MASK_IPV6_MYIPAD_0 << BIT_SHIFT_IPV6_MYIPAD_0)
#define BIT_CLEAR_IPV6_MYIPAD_0(x)			((x) & (~BITS_IPV6_MYIPAD_0))
#define BIT_GET_IPV6_MYIPAD_0(x)			(((x) >> BIT_SHIFT_IPV6_MYIPAD_0) & BIT_MASK_IPV6_MYIPAD_0)
#define BIT_SET_IPV6_MYIPAD_0(x, v)			(BIT_CLEAR_IPV6_MYIPAD_0(x) | BIT_IPV6_MYIPAD_0(v))

/* 2 REG_IPV6_1				(Offset 0x0734) */

#define BIT_SHIFT_IPV6_MYIPAD_1			0
#define BIT_MASK_IPV6_MYIPAD_1				0xffffffffL
#define BIT_IPV6_MYIPAD_1(x)				(((x) & BIT_MASK_IPV6_MYIPAD_1) << BIT_SHIFT_IPV6_MYIPAD_1)
#define BITS_IPV6_MYIPAD_1				(BIT_MASK_IPV6_MYIPAD_1 << BIT_SHIFT_IPV6_MYIPAD_1)
#define BIT_CLEAR_IPV6_MYIPAD_1(x)			((x) & (~BITS_IPV6_MYIPAD_1))
#define BIT_GET_IPV6_MYIPAD_1(x)			(((x) >> BIT_SHIFT_IPV6_MYIPAD_1) & BIT_MASK_IPV6_MYIPAD_1)
#define BIT_SET_IPV6_MYIPAD_1(x, v)			(BIT_CLEAR_IPV6_MYIPAD_1(x) | BIT_IPV6_MYIPAD_1(v))

/* 2 REG_IPV6_2				(Offset 0x0738) */

#define BIT_SHIFT_IPV6_MYIPAD_2			0
#define BIT_MASK_IPV6_MYIPAD_2				0xffffffffL
#define BIT_IPV6_MYIPAD_2(x)				(((x) & BIT_MASK_IPV6_MYIPAD_2) << BIT_SHIFT_IPV6_MYIPAD_2)
#define BITS_IPV6_MYIPAD_2				(BIT_MASK_IPV6_MYIPAD_2 << BIT_SHIFT_IPV6_MYIPAD_2)
#define BIT_CLEAR_IPV6_MYIPAD_2(x)			((x) & (~BITS_IPV6_MYIPAD_2))
#define BIT_GET_IPV6_MYIPAD_2(x)			(((x) >> BIT_SHIFT_IPV6_MYIPAD_2) & BIT_MASK_IPV6_MYIPAD_2)
#define BIT_SET_IPV6_MYIPAD_2(x, v)			(BIT_CLEAR_IPV6_MYIPAD_2(x) | BIT_IPV6_MYIPAD_2(v))

/* 2 REG_IPV6_3				(Offset 0x073C) */

#define BIT_SHIFT_IPV6_MYIPAD_3			0
#define BIT_MASK_IPV6_MYIPAD_3				0xffffffffL
#define BIT_IPV6_MYIPAD_3(x)				(((x) & BIT_MASK_IPV6_MYIPAD_3) << BIT_SHIFT_IPV6_MYIPAD_3)
#define BITS_IPV6_MYIPAD_3				(BIT_MASK_IPV6_MYIPAD_3 << BIT_SHIFT_IPV6_MYIPAD_3)
#define BIT_CLEAR_IPV6_MYIPAD_3(x)			((x) & (~BITS_IPV6_MYIPAD_3))
#define BIT_GET_IPV6_MYIPAD_3(x)			(((x) >> BIT_SHIFT_IPV6_MYIPAD_3) & BIT_MASK_IPV6_MYIPAD_3)
#define BIT_SET_IPV6_MYIPAD_3(x, v)			(BIT_CLEAR_IPV6_MYIPAD_3(x) | BIT_IPV6_MYIPAD_3(v))

/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG		(Offset 0x0750) */

#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE			4
#define BIT_MASK_R_WMAC_CTX_SUBTYPE			0xf
#define BIT_R_WMAC_CTX_SUBTYPE(x)			(((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE)
#define BITS_R_WMAC_CTX_SUBTYPE			(BIT_MASK_R_WMAC_CTX_SUBTYPE << BIT_SHIFT_R_WMAC_CTX_SUBTYPE)
#define BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x)		((x) & (~BITS_R_WMAC_CTX_SUBTYPE))
#define BIT_GET_R_WMAC_CTX_SUBTYPE(x)			(((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE)
#define BIT_SET_R_WMAC_CTX_SUBTYPE(x, v)		(BIT_CLEAR_R_WMAC_CTX_SUBTYPE(x) | BIT_R_WMAC_CTX_SUBTYPE(v))

#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE			0
#define BIT_MASK_R_WMAC_RTX_SUBTYPE			0xf
#define BIT_R_WMAC_RTX_SUBTYPE(x)			(((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE)
#define BITS_R_WMAC_RTX_SUBTYPE			(BIT_MASK_R_WMAC_RTX_SUBTYPE << BIT_SHIFT_R_WMAC_RTX_SUBTYPE)
#define BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x)		((x) & (~BITS_R_WMAC_RTX_SUBTYPE))
#define BIT_GET_R_WMAC_RTX_SUBTYPE(x)			(((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE)
#define BIT_SET_R_WMAC_RTX_SUBTYPE(x, v)		(BIT_CLEAR_R_WMAC_RTX_SUBTYPE(x) | BIT_R_WMAC_RTX_SUBTYPE(v))

/* 2 REG_WMAC_SWAES_CFG			(Offset 0x0760) */

#define BIT_SWAES_REQ					BIT(7)
#define BIT_R_WMAC_SWAES_WE				BIT(3)
#define BIT_R_WMAC_SWAES_SEL				BIT(0)

/* 2 REG_BT_PRI				(Offset 0x0762) */

#define BIT_BTCOEX_SW_RST				BIT(15)
#define BIT_GNT_BOTH_POL				BIT(12)
#define BIT_BT_ARB_INST_EN				BIT(8)

#define BIT_SHIFT_BT_ARB_TIME				0
#define BIT_MASK_BT_ARB_TIME				0xff
#define BIT_BT_ARB_TIME(x)				(((x) & BIT_MASK_BT_ARB_TIME) << BIT_SHIFT_BT_ARB_TIME)
#define BITS_BT_ARB_TIME				(BIT_MASK_BT_ARB_TIME << BIT_SHIFT_BT_ARB_TIME)
#define BIT_CLEAR_BT_ARB_TIME(x)			((x) & (~BITS_BT_ARB_TIME))
#define BIT_GET_BT_ARB_TIME(x)				(((x) >> BIT_SHIFT_BT_ARB_TIME) & BIT_MASK_BT_ARB_TIME)
#define BIT_SET_BT_ARB_TIME(x, v)			(BIT_CLEAR_BT_ARB_TIME(x) | BIT_BT_ARB_TIME(v))

/* 2 REG_BT_COEX_ENH				(Offset 0x0764) */

#define BIT_R_GNT_BT_RFC_SW				BIT(12)
#define BIT_R_GNT_BT_RFC_SW_EN				BIT(11)
#define BIT_R_GNT_BT_BB_SW				BIT(10)
#define BIT_R_GNT_BT_BB_SW_EN				BIT(9)
#define BIT_R_BT_CNT_THREN				BIT(8)

#define BIT_SHIFT_R_BT_CNT_THR				0
#define BIT_MASK_R_BT_CNT_THR				0xff
#define BIT_R_BT_CNT_THR(x)				(((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR)
#define BITS_R_BT_CNT_THR				(BIT_MASK_R_BT_CNT_THR << BIT_SHIFT_R_BT_CNT_THR)
#define BIT_CLEAR_R_BT_CNT_THR(x)			((x) & (~BITS_R_BT_CNT_THR))
#define BIT_GET_R_BT_CNT_THR(x)			(((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR)
#define BIT_SET_R_BT_CNT_THR(x, v)			(BIT_CLEAR_R_BT_CNT_THR(x) | BIT_R_BT_CNT_THR(v))

/* 2 REG_WLAN_ACT_MASK_CTRL			(Offset 0x0768) */

#define BIT_SHIFT_WACTMSK_OFF_DUR			8
#define BIT_MASK_WACTMSK_OFF_DUR			0xff
#define BIT_WACTMSK_OFF_DUR(x)				(((x) & BIT_MASK_WACTMSK_OFF_DUR) << BIT_SHIFT_WACTMSK_OFF_DUR)
#define BITS_WACTMSK_OFF_DUR				(BIT_MASK_WACTMSK_OFF_DUR << BIT_SHIFT_WACTMSK_OFF_DUR)
#define BIT_CLEAR_WACTMSK_OFF_DUR(x)			((x) & (~BITS_WACTMSK_OFF_DUR))
#define BIT_GET_WACTMSK_OFF_DUR(x)			(((x) >> BIT_SHIFT_WACTMSK_OFF_DUR) & BIT_MASK_WACTMSK_OFF_DUR)
#define BIT_SET_WACTMSK_OFF_DUR(x, v)			(BIT_CLEAR_WACTMSK_OFF_DUR(x) | BIT_WACTMSK_OFF_DUR(v))

#define BIT_SHIFT_WACTMSK_ON_DUR			0
#define BIT_MASK_WACTMSK_ON_DUR			0xff
#define BIT_WACTMSK_ON_DUR(x)				(((x) & BIT_MASK_WACTMSK_ON_DUR) << BIT_SHIFT_WACTMSK_ON_DUR)
#define BITS_WACTMSK_ON_DUR				(BIT_MASK_WACTMSK_ON_DUR << BIT_SHIFT_WACTMSK_ON_DUR)
#define BIT_CLEAR_WACTMSK_ON_DUR(x)			((x) & (~BITS_WACTMSK_ON_DUR))
#define BIT_GET_WACTMSK_ON_DUR(x)			(((x) >> BIT_SHIFT_WACTMSK_ON_DUR) & BIT_MASK_WACTMSK_ON_DUR)
#define BIT_SET_WACTMSK_ON_DUR(x, v)			(BIT_CLEAR_WACTMSK_ON_DUR(x) | BIT_WACTMSK_ON_DUR(v))

/* 2 REG_WLAN_ACT_MASK_CTRL_1		(Offset 0x076C) */

#define BIT_WLRX_TER_BY_CTL_1				BIT(11)
#define BIT_WLRX_TER_BY_AD_1				BIT(10)
#define BIT_ANT_DIVERSITY_SEL_1			BIT(9)
#define BIT_ANTSEL_FOR_BT_CTRL_EN_1			BIT(8)
#define BIT_WLACT_LOW_GNTWL_EN_1			BIT(2)
#define BIT_WLACT_HIGH_GNTBT_EN_1			BIT(1)
#define BIT_NAV_UPPER_1_V1				BIT(0)

/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL		(Offset 0x076E) */

#define BIT_SHIFT_BT_STAT_DELAY			12
#define BIT_MASK_BT_STAT_DELAY				0xf
#define BIT_BT_STAT_DELAY(x)				(((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY)
#define BITS_BT_STAT_DELAY				(BIT_MASK_BT_STAT_DELAY << BIT_SHIFT_BT_STAT_DELAY)
#define BIT_CLEAR_BT_STAT_DELAY(x)			((x) & (~BITS_BT_STAT_DELAY))
#define BIT_GET_BT_STAT_DELAY(x)			(((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY)
#define BIT_SET_BT_STAT_DELAY(x, v)			(BIT_CLEAR_BT_STAT_DELAY(x) | BIT_BT_STAT_DELAY(v))

#define BIT_SHIFT_BT_TRX_INIT_DETECT			8
#define BIT_MASK_BT_TRX_INIT_DETECT			0xf
#define BIT_BT_TRX_INIT_DETECT(x)			(((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT)
#define BITS_BT_TRX_INIT_DETECT			(BIT_MASK_BT_TRX_INIT_DETECT << BIT_SHIFT_BT_TRX_INIT_DETECT)
#define BIT_CLEAR_BT_TRX_INIT_DETECT(x)		((x) & (~BITS_BT_TRX_INIT_DETECT))
#define BIT_GET_BT_TRX_INIT_DETECT(x)			(((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT)
#define BIT_SET_BT_TRX_INIT_DETECT(x, v)		(BIT_CLEAR_BT_TRX_INIT_DETECT(x) | BIT_BT_TRX_INIT_DETECT(v))

#define BIT_SHIFT_BT_PRI_DETECT_TO			4
#define BIT_MASK_BT_PRI_DETECT_TO			0xf
#define BIT_BT_PRI_DETECT_TO(x)			(((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO)
#define BITS_BT_PRI_DETECT_TO				(BIT_MASK_BT_PRI_DETECT_TO << BIT_SHIFT_BT_PRI_DETECT_TO)
#define BIT_CLEAR_BT_PRI_DETECT_TO(x)			((x) & (~BITS_BT_PRI_DETECT_TO))
#define BIT_GET_BT_PRI_DETECT_TO(x)			(((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO)
#define BIT_SET_BT_PRI_DETECT_TO(x, v)			(BIT_CLEAR_BT_PRI_DETECT_TO(x) | BIT_BT_PRI_DETECT_TO(v))

#define BIT_R_GRANTALL_WLMASK				BIT(3)
#define BIT_STATIS_BT_EN				BIT(2)
#define BIT_WL_ACT_MASK_ENABLE				BIT(1)
#define BIT_ENHANCED_BT				BIT(0)

/* 2 REG_BT_PROPRI				(Offset 0x0778) */

#define BIT_SHIFT_BT_HID_ISR_SET			6
#define BIT_MASK_BT_HID_ISR_SET			0x3
#define BIT_BT_HID_ISR_SET(x)				(((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET)
#define BITS_BT_HID_ISR_SET				(BIT_MASK_BT_HID_ISR_SET << BIT_SHIFT_BT_HID_ISR_SET)
#define BIT_CLEAR_BT_HID_ISR_SET(x)			((x) & (~BITS_BT_HID_ISR_SET))
#define BIT_GET_BT_HID_ISR_SET(x)			(((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET)
#define BIT_SET_BT_HID_ISR_SET(x, v)			(BIT_CLEAR_BT_HID_ISR_SET(x) | BIT_BT_HID_ISR_SET(v))

#define BIT_TDMA_BT_START_NOTIFY			BIT(5)
#define BIT_ENABLE_TDMA_HW_MODE			BIT(4)
#define BIT_ENABLE_PTA_TDMA_MODE			BIT(3)
#define BIT_ENABLE_COEXIST_TAB_IN_TDMA			BIT(2)
#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA		BIT(1)
#define BIT_RTK_BT_ENABLE				BIT(0)

/* 2 REG_BT_STATUS_REPORT_REGISTER		(Offset 0x077C) */

#define BIT_SHIFT_BT_PROFILE				24
#define BIT_MASK_BT_PROFILE				0xff
#define BIT_BT_PROFILE(x)				(((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE)
#define BITS_BT_PROFILE				(BIT_MASK_BT_PROFILE << BIT_SHIFT_BT_PROFILE)
#define BIT_CLEAR_BT_PROFILE(x)			((x) & (~BITS_BT_PROFILE))
#define BIT_GET_BT_PROFILE(x)				(((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE)
#define BIT_SET_BT_PROFILE(x, v)			(BIT_CLEAR_BT_PROFILE(x) | BIT_BT_PROFILE(v))

#define BIT_SHIFT_BT_POWER				16
#define BIT_MASK_BT_POWER				0xff
#define BIT_BT_POWER(x)				(((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER)
#define BITS_BT_POWER					(BIT_MASK_BT_POWER << BIT_SHIFT_BT_POWER)
#define BIT_CLEAR_BT_POWER(x)				((x) & (~BITS_BT_POWER))
#define BIT_GET_BT_POWER(x)				(((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER)
#define BIT_SET_BT_POWER(x, v)				(BIT_CLEAR_BT_POWER(x) | BIT_BT_POWER(v))

#define BIT_SHIFT_BT_PREDECT_STATUS			8
#define BIT_MASK_BT_PREDECT_STATUS			0xff
#define BIT_BT_PREDECT_STATUS(x)			(((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS)
#define BITS_BT_PREDECT_STATUS				(BIT_MASK_BT_PREDECT_STATUS << BIT_SHIFT_BT_PREDECT_STATUS)
#define BIT_CLEAR_BT_PREDECT_STATUS(x)			((x) & (~BITS_BT_PREDECT_STATUS))
#define BIT_GET_BT_PREDECT_STATUS(x)			(((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS)
#define BIT_SET_BT_PREDECT_STATUS(x, v)		(BIT_CLEAR_BT_PREDECT_STATUS(x) | BIT_BT_PREDECT_STATUS(v))

#define BIT_SHIFT_BT_CMD_ID				0
#define BIT_MASK_BT_CMD_ID				0xff
#define BIT_BT_CMD_ID(x)				(((x) & BIT_MASK_BT_CMD_ID) << BIT_SHIFT_BT_CMD_ID)
#define BITS_BT_CMD_ID					(BIT_MASK_BT_CMD_ID << BIT_SHIFT_BT_CMD_ID)
#define BIT_CLEAR_BT_CMD_ID(x)				((x) & (~BITS_BT_CMD_ID))
#define BIT_GET_BT_CMD_ID(x)				(((x) >> BIT_SHIFT_BT_CMD_ID) & BIT_MASK_BT_CMD_ID)
#define BIT_SET_BT_CMD_ID(x, v)			(BIT_CLEAR_BT_CMD_ID(x) | BIT_BT_CMD_ID(v))

/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER	(Offset 0x0780) */

#define BIT_EN_MAC_NULL_PKT_NOTIFY			BIT(31)
#define BIT_EN_WLAN_RPT_AND_BT_QUERY			BIT(30)
#define BIT_EN_BT_STSTUS_RPT				BIT(29)
#define BIT_EN_BT_POWER				BIT(28)
#define BIT_EN_BT_CHANNEL				BIT(27)
#define BIT_EN_BT_SLOT_CHANGE				BIT(26)
#define BIT_EN_BT_PROFILE_OR_HID			BIT(25)
#define BIT_WLAN_RPT_NOTIFY				BIT(24)

#define BIT_SHIFT_WLAN_RPT_DATA			16
#define BIT_MASK_WLAN_RPT_DATA				0xff
#define BIT_WLAN_RPT_DATA(x)				(((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA)
#define BITS_WLAN_RPT_DATA				(BIT_MASK_WLAN_RPT_DATA << BIT_SHIFT_WLAN_RPT_DATA)
#define BIT_CLEAR_WLAN_RPT_DATA(x)			((x) & (~BITS_WLAN_RPT_DATA))
#define BIT_GET_WLAN_RPT_DATA(x)			(((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA)
#define BIT_SET_WLAN_RPT_DATA(x, v)			(BIT_CLEAR_WLAN_RPT_DATA(x) | BIT_WLAN_RPT_DATA(v))

#define BIT_SHIFT_TO_BT_CMDID				8
#define BIT_MASK_TO_BT_CMDID				0xff
#define BIT_TO_BT_CMDID(x)				(((x) & BIT_MASK_TO_BT_CMDID) << BIT_SHIFT_TO_BT_CMDID)
#define BITS_TO_BT_CMDID				(BIT_MASK_TO_BT_CMDID << BIT_SHIFT_TO_BT_CMDID)
#define BIT_CLEAR_TO_BT_CMDID(x)			((x) & (~BITS_TO_BT_CMDID))
#define BIT_GET_TO_BT_CMDID(x)				(((x) >> BIT_SHIFT_TO_BT_CMDID) & BIT_MASK_TO_BT_CMDID)
#define BIT_SET_TO_BT_CMDID(x, v)			(BIT_CLEAR_TO_BT_CMDID(x) | BIT_TO_BT_CMDID(v))

#define BIT_SHIFT_BT_DATA				0
#define BIT_MASK_BT_DATA				0xff
#define BIT_BT_DATA(x)					(((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA)
#define BITS_BT_DATA					(BIT_MASK_BT_DATA << BIT_SHIFT_BT_DATA)
#define BIT_CLEAR_BT_DATA(x)				((x) & (~BITS_BT_DATA))
#define BIT_GET_BT_DATA(x)				(((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA)
#define BIT_SET_BT_DATA(x, v)				(BIT_CLEAR_BT_DATA(x) | BIT_BT_DATA(v))

/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */

#define BIT_SHIFT_WLAN_RPT_TO				0
#define BIT_MASK_WLAN_RPT_TO				0xff
#define BIT_WLAN_RPT_TO(x)				(((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO)
#define BITS_WLAN_RPT_TO				(BIT_MASK_WLAN_RPT_TO << BIT_SHIFT_WLAN_RPT_TO)
#define BIT_CLEAR_WLAN_RPT_TO(x)			((x) & (~BITS_WLAN_RPT_TO))
#define BIT_GET_WLAN_RPT_TO(x)				(((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO)
#define BIT_SET_WLAN_RPT_TO(x, v)			(BIT_CLEAR_WLAN_RPT_TO(x) | BIT_WLAN_RPT_TO(v))

/* 2 REG_CH_COEXIST				(Offset 0x0785) */

#define BIT_SHIFT_ISOLATION_CHK_0			1
#define BIT_MASK_ISOLATION_CHK_0			0x7fffff
#define BIT_ISOLATION_CHK_0(x)				(((x) & BIT_MASK_ISOLATION_CHK_0) << BIT_SHIFT_ISOLATION_CHK_0)
#define BITS_ISOLATION_CHK_0				(BIT_MASK_ISOLATION_CHK_0 << BIT_SHIFT_ISOLATION_CHK_0)
#define BIT_CLEAR_ISOLATION_CHK_0(x)			((x) & (~BITS_ISOLATION_CHK_0))
#define BIT_GET_ISOLATION_CHK_0(x)			(((x) >> BIT_SHIFT_ISOLATION_CHK_0) & BIT_MASK_ISOLATION_CHK_0)
#define BIT_SET_ISOLATION_CHK_0(x, v)			(BIT_CLEAR_ISOLATION_CHK_0(x) | BIT_ISOLATION_CHK_0(v))

#define BIT_ISOLATION_EN				BIT(0)

/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 (Offset 0x0788) */

#define BIT_SHIFT_ISOLATION_CHK_1			0
#define BIT_MASK_ISOLATION_CHK_1			0xffffffffL
#define BIT_ISOLATION_CHK_1(x)				(((x) & BIT_MASK_ISOLATION_CHK_1) << BIT_SHIFT_ISOLATION_CHK_1)
#define BITS_ISOLATION_CHK_1				(BIT_MASK_ISOLATION_CHK_1 << BIT_SHIFT_ISOLATION_CHK_1)
#define BIT_CLEAR_ISOLATION_CHK_1(x)			((x) & (~BITS_ISOLATION_CHK_1))
#define BIT_GET_ISOLATION_CHK_1(x)			(((x) >> BIT_SHIFT_ISOLATION_CHK_1) & BIT_MASK_ISOLATION_CHK_1)
#define BIT_SET_ISOLATION_CHK_1(x, v)			(BIT_CLEAR_ISOLATION_CHK_1(x) | BIT_ISOLATION_CHK_1(v))

/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 (Offset 0x078C) */

#define BIT_SHIFT_ISOLATION_CHK_2			0
#define BIT_MASK_ISOLATION_CHK_2			0xffffff
#define BIT_ISOLATION_CHK_2(x)				(((x) & BIT_MASK_ISOLATION_CHK_2) << BIT_SHIFT_ISOLATION_CHK_2)
#define BITS_ISOLATION_CHK_2				(BIT_MASK_ISOLATION_CHK_2 << BIT_SHIFT_ISOLATION_CHK_2)
#define BIT_CLEAR_ISOLATION_CHK_2(x)			((x) & (~BITS_ISOLATION_CHK_2))
#define BIT_GET_ISOLATION_CHK_2(x)			(((x) >> BIT_SHIFT_ISOLATION_CHK_2) & BIT_MASK_ISOLATION_CHK_2)
#define BIT_SET_ISOLATION_CHK_2(x, v)			(BIT_CLEAR_ISOLATION_CHK_2(x) | BIT_ISOLATION_CHK_2(v))

/* 2 REG_BT_INTERRUPT_STATUS_REGISTER	(Offset 0x078F) */

#define BIT_BT_HID_ISR					BIT(7)
#define BIT_BT_QUERY_ISR				BIT(6)
#define BIT_MAC_NULL_PKT_NOTIFY_ISR			BIT(5)
#define BIT_WLAN_RPT_ISR				BIT(4)
#define BIT_BT_POWER_ISR				BIT(3)
#define BIT_BT_CHANNEL_ISR				BIT(2)
#define BIT_BT_SLOT_CHANGE_ISR				BIT(1)
#define BIT_BT_PROFILE_ISR				BIT(0)

/* 2 REG_BT_TDMA_TIME_REGISTER		(Offset 0x0790) */

#define BIT_SHIFT_BT_TIME				6
#define BIT_MASK_BT_TIME				0x3ffffff
#define BIT_BT_TIME(x)					(((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME)
#define BITS_BT_TIME					(BIT_MASK_BT_TIME << BIT_SHIFT_BT_TIME)
#define BIT_CLEAR_BT_TIME(x)				((x) & (~BITS_BT_TIME))
#define BIT_GET_BT_TIME(x)				(((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME)
#define BIT_SET_BT_TIME(x, v)				(BIT_CLEAR_BT_TIME(x) | BIT_BT_TIME(v))

#define BIT_SHIFT_BT_RPT_SAMPLE_RATE			0
#define BIT_MASK_BT_RPT_SAMPLE_RATE			0x3f
#define BIT_BT_RPT_SAMPLE_RATE(x)			(((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE)
#define BITS_BT_RPT_SAMPLE_RATE			(BIT_MASK_BT_RPT_SAMPLE_RATE << BIT_SHIFT_BT_RPT_SAMPLE_RATE)
#define BIT_CLEAR_BT_RPT_SAMPLE_RATE(x)		((x) & (~BITS_BT_RPT_SAMPLE_RATE))
#define BIT_GET_BT_RPT_SAMPLE_RATE(x)			(((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE)
#define BIT_SET_BT_RPT_SAMPLE_RATE(x, v)		(BIT_CLEAR_BT_RPT_SAMPLE_RATE(x) | BIT_BT_RPT_SAMPLE_RATE(v))

/* 2 REG_BT_ACT_REGISTER			(Offset 0x0794) */

#define BIT_B_AX_BT_BLE_EN				BIT(24)

#define BIT_SHIFT_BT_EISR_EN				16
#define BIT_MASK_BT_EISR_EN				0xff
#define BIT_BT_EISR_EN(x)				(((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN)
#define BITS_BT_EISR_EN				(BIT_MASK_BT_EISR_EN << BIT_SHIFT_BT_EISR_EN)
#define BIT_CLEAR_BT_EISR_EN(x)			((x) & (~BITS_BT_EISR_EN))
#define BIT_GET_BT_EISR_EN(x)				(((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN)
#define BIT_SET_BT_EISR_EN(x, v)			(BIT_CLEAR_BT_EISR_EN(x) | BIT_BT_EISR_EN(v))

#define BIT_BT_ACT_FALLING_ISR				BIT(10)
#define BIT_BT_ACT_RISING_ISR				BIT(9)
#define BIT_TDMA_TO_ISR				BIT(8)

#define BIT_SHIFT_BT_CH				0
#define BIT_MASK_BT_CH					0x7f
#define BIT_BT_CH(x)					(((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH)
#define BITS_BT_CH					(BIT_MASK_BT_CH << BIT_SHIFT_BT_CH)
#define BIT_CLEAR_BT_CH(x)				((x) & (~BITS_BT_CH))
#define BIT_GET_BT_CH(x)				(((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH)
#define BIT_SET_BT_CH(x, v)				(BIT_CLEAR_BT_CH(x) | BIT_BT_CH(v))

/* 2 REG_LTR_IDLE_LATENCY_V2			(Offset 0x0798) */

#define BIT_SHIFT_LTR_IDLE_LATENCY			0
#define BIT_MASK_LTR_IDLE_LATENCY			0xffffffffL
#define BIT_LTR_IDLE_LATENCY(x)			(((x) & BIT_MASK_LTR_IDLE_LATENCY) << BIT_SHIFT_LTR_IDLE_LATENCY)
#define BITS_LTR_IDLE_LATENCY				(BIT_MASK_LTR_IDLE_LATENCY << BIT_SHIFT_LTR_IDLE_LATENCY)
#define BIT_CLEAR_LTR_IDLE_LATENCY(x)			((x) & (~BITS_LTR_IDLE_LATENCY))
#define BIT_GET_LTR_IDLE_LATENCY(x)			(((x) >> BIT_SHIFT_LTR_IDLE_LATENCY) & BIT_MASK_LTR_IDLE_LATENCY)
#define BIT_SET_LTR_IDLE_LATENCY(x, v)			(BIT_CLEAR_LTR_IDLE_LATENCY(x) | BIT_LTR_IDLE_LATENCY(v))

/* 2 REG_LTR_ACTIVE_LATENCY_V2		(Offset 0x079C) */

#define BIT_SHIFT_LTR_ACTIVE_LATENCY			0
#define BIT_MASK_LTR_ACTIVE_LATENCY			0xffffffffL
#define BIT_LTR_ACTIVE_LATENCY(x)			(((x) & BIT_MASK_LTR_ACTIVE_LATENCY) << BIT_SHIFT_LTR_ACTIVE_LATENCY)
#define BITS_LTR_ACTIVE_LATENCY			(BIT_MASK_LTR_ACTIVE_LATENCY << BIT_SHIFT_LTR_ACTIVE_LATENCY)
#define BIT_CLEAR_LTR_ACTIVE_LATENCY(x)		((x) & (~BITS_LTR_ACTIVE_LATENCY))
#define BIT_GET_LTR_ACTIVE_LATENCY(x)			(((x) >> BIT_SHIFT_LTR_ACTIVE_LATENCY) & BIT_MASK_LTR_ACTIVE_LATENCY)
#define BIT_SET_LTR_ACTIVE_LATENCY(x, v)		(BIT_CLEAR_LTR_ACTIVE_LATENCY(x) | BIT_LTR_ACTIVE_LATENCY(v))

/* 2 REG_OBFF_CTRL				(Offset 0x07A0) */

#define BIT_ODFF_EN					BIT(31)
#define BIT_CFG_OBFF_AUTOACT				BIT(30)

#define BIT_SHIFT_OBFF_STATE				28
#define BIT_MASK_OBFF_STATE				0x3
#define BIT_OBFF_STATE(x)				(((x) & BIT_MASK_OBFF_STATE) << BIT_SHIFT_OBFF_STATE)
#define BITS_OBFF_STATE				(BIT_MASK_OBFF_STATE << BIT_SHIFT_OBFF_STATE)
#define BIT_CLEAR_OBFF_STATE(x)			((x) & (~BITS_OBFF_STATE))
#define BIT_GET_OBFF_STATE(x)				(((x) >> BIT_SHIFT_OBFF_STATE) & BIT_MASK_OBFF_STATE)
#define BIT_SET_OBFF_STATE(x, v)			(BIT_CLEAR_OBFF_STATE(x) | BIT_OBFF_STATE(v))

#define BIT_CFG_OBFF_AUTOIDLE				BIT(27)
#define BIT_CFG_BLOCKINT_EN				BIT(26)

#define BIT_SHIFT_CFG_WK_MAX_PLS			23
#define BIT_MASK_CFG_WK_MAX_PLS			0x7
#define BIT_CFG_WK_MAX_PLS(x)				(((x) & BIT_MASK_CFG_WK_MAX_PLS) << BIT_SHIFT_CFG_WK_MAX_PLS)
#define BITS_CFG_WK_MAX_PLS				(BIT_MASK_CFG_WK_MAX_PLS << BIT_SHIFT_CFG_WK_MAX_PLS)
#define BIT_CLEAR_CFG_WK_MAX_PLS(x)			((x) & (~BITS_CFG_WK_MAX_PLS))
#define BIT_GET_CFG_WK_MAX_PLS(x)			(((x) >> BIT_SHIFT_CFG_WK_MAX_PLS) & BIT_MASK_CFG_WK_MAX_PLS)
#define BIT_SET_CFG_WK_MAX_PLS(x, v)			(BIT_CLEAR_CFG_WK_MAX_PLS(x) | BIT_CFG_WK_MAX_PLS(v))

#define BIT_SHIFT_CFG_WK_MIN_PLS			20
#define BIT_MASK_CFG_WK_MIN_PLS			0x7
#define BIT_CFG_WK_MIN_PLS(x)				(((x) & BIT_MASK_CFG_WK_MIN_PLS) << BIT_SHIFT_CFG_WK_MIN_PLS)
#define BITS_CFG_WK_MIN_PLS				(BIT_MASK_CFG_WK_MIN_PLS << BIT_SHIFT_CFG_WK_MIN_PLS)
#define BIT_CLEAR_CFG_WK_MIN_PLS(x)			((x) & (~BITS_CFG_WK_MIN_PLS))
#define BIT_GET_CFG_WK_MIN_PLS(x)			(((x) >> BIT_SHIFT_CFG_WK_MIN_PLS) & BIT_MASK_CFG_WK_MIN_PLS)
#define BIT_SET_CFG_WK_MIN_PLS(x, v)			(BIT_CLEAR_CFG_WK_MIN_PLS(x) | BIT_CFG_WK_MIN_PLS(v))

#define BIT_SHIFT_CFG_WK_MAX_F2F			17
#define BIT_MASK_CFG_WK_MAX_F2F			0x7
#define BIT_CFG_WK_MAX_F2F(x)				(((x) & BIT_MASK_CFG_WK_MAX_F2F) << BIT_SHIFT_CFG_WK_MAX_F2F)
#define BITS_CFG_WK_MAX_F2F				(BIT_MASK_CFG_WK_MAX_F2F << BIT_SHIFT_CFG_WK_MAX_F2F)
#define BIT_CLEAR_CFG_WK_MAX_F2F(x)			((x) & (~BITS_CFG_WK_MAX_F2F))
#define BIT_GET_CFG_WK_MAX_F2F(x)			(((x) >> BIT_SHIFT_CFG_WK_MAX_F2F) & BIT_MASK_CFG_WK_MAX_F2F)
#define BIT_SET_CFG_WK_MAX_F2F(x, v)			(BIT_CLEAR_CFG_WK_MAX_F2F(x) | BIT_CFG_WK_MAX_F2F(v))

#define BIT_SHIFT_CFG_WK_MIN_F2F			14
#define BIT_MASK_CFG_WK_MIN_F2F			0x7
#define BIT_CFG_WK_MIN_F2F(x)				(((x) & BIT_MASK_CFG_WK_MIN_F2F) << BIT_SHIFT_CFG_WK_MIN_F2F)
#define BITS_CFG_WK_MIN_F2F				(BIT_MASK_CFG_WK_MIN_F2F << BIT_SHIFT_CFG_WK_MIN_F2F)
#define BIT_CLEAR_CFG_WK_MIN_F2F(x)			((x) & (~BITS_CFG_WK_MIN_F2F))
#define BIT_GET_CFG_WK_MIN_F2F(x)			(((x) >> BIT_SHIFT_CFG_WK_MIN_F2F) & BIT_MASK_CFG_WK_MIN_F2F)
#define BIT_SET_CFG_WK_MIN_F2F(x, v)			(BIT_CLEAR_CFG_WK_MIN_F2F(x) | BIT_CFG_WK_MIN_F2F(v))

#define BIT_CFG_TXBLOCK_EN				BIT(13)

#define BIT_SHIFT_OBFF_INT_TIME_ID			10
#define BIT_MASK_OBFF_INT_TIME_ID			0x7
#define BIT_OBFF_INT_TIME_ID(x)			(((x) & BIT_MASK_OBFF_INT_TIME_ID) << BIT_SHIFT_OBFF_INT_TIME_ID)
#define BITS_OBFF_INT_TIME_ID				(BIT_MASK_OBFF_INT_TIME_ID << BIT_SHIFT_OBFF_INT_TIME_ID)
#define BIT_CLEAR_OBFF_INT_TIME_ID(x)			((x) & (~BITS_OBFF_INT_TIME_ID))
#define BIT_GET_OBFF_INT_TIME_ID(x)			(((x) >> BIT_SHIFT_OBFF_INT_TIME_ID) & BIT_MASK_OBFF_INT_TIME_ID)
#define BIT_SET_OBFF_INT_TIME_ID(x, v)			(BIT_CLEAR_OBFF_INT_TIME_ID(x) | BIT_OBFF_INT_TIME_ID(v))

#define BIT_SHIFT_OBFF_TIMER_ID_MEDIA			7
#define BIT_MASK_OBFF_TIMER_ID_MEDIA			0x7
#define BIT_OBFF_TIMER_ID_MEDIA(x)			(((x) & BIT_MASK_OBFF_TIMER_ID_MEDIA) << BIT_SHIFT_OBFF_TIMER_ID_MEDIA)
#define BITS_OBFF_TIMER_ID_MEDIA			(BIT_MASK_OBFF_TIMER_ID_MEDIA << BIT_SHIFT_OBFF_TIMER_ID_MEDIA)
#define BIT_CLEAR_OBFF_TIMER_ID_MEDIA(x)		((x) & (~BITS_OBFF_TIMER_ID_MEDIA))
#define BIT_GET_OBFF_TIMER_ID_MEDIA(x)			(((x) >> BIT_SHIFT_OBFF_TIMER_ID_MEDIA) & BIT_MASK_OBFF_TIMER_ID_MEDIA)
#define BIT_SET_OBFF_TIMER_ID_MEDIA(x, v)		(BIT_CLEAR_OBFF_TIMER_ID_MEDIA(x) | BIT_OBFF_TIMER_ID_MEDIA(v))

#define BIT_SHIFT_OBFF_TIME_ID_LOW			4
#define BIT_MASK_OBFF_TIME_ID_LOW			0x7
#define BIT_OBFF_TIME_ID_LOW(x)			(((x) & BIT_MASK_OBFF_TIME_ID_LOW) << BIT_SHIFT_OBFF_TIME_ID_LOW)
#define BITS_OBFF_TIME_ID_LOW				(BIT_MASK_OBFF_TIME_ID_LOW << BIT_SHIFT_OBFF_TIME_ID_LOW)
#define BIT_CLEAR_OBFF_TIME_ID_LOW(x)			((x) & (~BITS_OBFF_TIME_ID_LOW))
#define BIT_GET_OBFF_TIME_ID_LOW(x)			(((x) >> BIT_SHIFT_OBFF_TIME_ID_LOW) & BIT_MASK_OBFF_TIME_ID_LOW)
#define BIT_SET_OBFF_TIME_ID_LOW(x, v)			(BIT_CLEAR_OBFF_TIME_ID_LOW(x) | BIT_OBFF_TIME_ID_LOW(v))

#define BIT_APP_CPU_ACT				BIT(3)
#define BIT_APP_OBFF					BIT(2)
#define BIT_APP_IDLE					BIT(1)
#define BIT__APP_INIT					BIT(0)

/* 2 REG_LTR_CTRL				(Offset 0x07A4) */

#define BIT_SHIFT_LTR_RPBACC_ID_HIGH			25
#define BIT_MASK_LTR_RPBACC_ID_HIGH			0x7
#define BIT_LTR_RPBACC_ID_HIGH(x)			(((x) & BIT_MASK_LTR_RPBACC_ID_HIGH) << BIT_SHIFT_LTR_RPBACC_ID_HIGH)
#define BITS_LTR_RPBACC_ID_HIGH			(BIT_MASK_LTR_RPBACC_ID_HIGH << BIT_SHIFT_LTR_RPBACC_ID_HIGH)
#define BIT_CLEAR_LTR_RPBACC_ID_HIGH(x)		((x) & (~BITS_LTR_RPBACC_ID_HIGH))
#define BIT_GET_LTR_RPBACC_ID_HIGH(x)			(((x) >> BIT_SHIFT_LTR_RPBACC_ID_HIGH) & BIT_MASK_LTR_RPBACC_ID_HIGH)
#define BIT_SET_LTR_RPBACC_ID_HIGH(x, v)		(BIT_CLEAR_LTR_RPBACC_ID_HIGH(x) | BIT_LTR_RPBACC_ID_HIGH(v))

#define BIT_SHIFT_LTR_RPBACC_ID_MEDIA			22
#define BIT_MASK_LTR_RPBACC_ID_MEDIA			0x7
#define BIT_LTR_RPBACC_ID_MEDIA(x)			(((x) & BIT_MASK_LTR_RPBACC_ID_MEDIA) << BIT_SHIFT_LTR_RPBACC_ID_MEDIA)
#define BITS_LTR_RPBACC_ID_MEDIA			(BIT_MASK_LTR_RPBACC_ID_MEDIA << BIT_SHIFT_LTR_RPBACC_ID_MEDIA)
#define BIT_CLEAR_LTR_RPBACC_ID_MEDIA(x)		((x) & (~BITS_LTR_RPBACC_ID_MEDIA))
#define BIT_GET_LTR_RPBACC_ID_MEDIA(x)			(((x) >> BIT_SHIFT_LTR_RPBACC_ID_MEDIA) & BIT_MASK_LTR_RPBACC_ID_MEDIA)
#define BIT_SET_LTR_RPBACC_ID_MEDIA(x, v)		(BIT_CLEAR_LTR_RPBACC_ID_MEDIA(x) | BIT_LTR_RPBACC_ID_MEDIA(v))

#define BIT_SHIFT_LTR_RPBACC_ID_LOW			19
#define BIT_MASK_LTR_RPBACC_ID_LOW			0x7
#define BIT_LTR_RPBACC_ID_LOW(x)			(((x) & BIT_MASK_LTR_RPBACC_ID_LOW) << BIT_SHIFT_LTR_RPBACC_ID_LOW)
#define BITS_LTR_RPBACC_ID_LOW				(BIT_MASK_LTR_RPBACC_ID_LOW << BIT_SHIFT_LTR_RPBACC_ID_LOW)
#define BIT_CLEAR_LTR_RPBACC_ID_LOW(x)			((x) & (~BITS_LTR_RPBACC_ID_LOW))
#define BIT_GET_LTR_RPBACC_ID_LOW(x)			(((x) >> BIT_SHIFT_LTR_RPBACC_ID_LOW) & BIT_MASK_LTR_RPBACC_ID_LOW)
#define BIT_SET_LTR_RPBACC_ID_LOW(x, v)		(BIT_CLEAR_LTR_RPBACC_ID_LOW(x) | BIT_LTR_RPBACC_ID_LOW(v))

#define BIT_RPBACC_CLRBLOCK				BIT(18)
#define BIT_LTR_RPBACC_EN				BIT(17)

#define BIT_SHIFT_LTR_SPACE_ID				15
#define BIT_MASK_LTR_SPACE_ID				0x3
#define BIT_LTR_SPACE_ID(x)				(((x) & BIT_MASK_LTR_SPACE_ID) << BIT_SHIFT_LTR_SPACE_ID)
#define BITS_LTR_SPACE_ID				(BIT_MASK_LTR_SPACE_ID << BIT_SHIFT_LTR_SPACE_ID)
#define BIT_CLEAR_LTR_SPACE_ID(x)			((x) & (~BITS_LTR_SPACE_ID))
#define BIT_GET_LTR_SPACE_ID(x)			(((x) >> BIT_SHIFT_LTR_SPACE_ID) & BIT_MASK_LTR_SPACE_ID)
#define BIT_SET_LTR_SPACE_ID(x, v)			(BIT_CLEAR_LTR_SPACE_ID(x) | BIT_LTR_SPACE_ID(v))

#define BIT_SHIFT_LTR_IDLE_TIMER_ID			12
#define BIT_MASK_LTR_IDLE_TIMER_ID			0x7
#define BIT_LTR_IDLE_TIMER_ID(x)			(((x) & BIT_MASK_LTR_IDLE_TIMER_ID) << BIT_SHIFT_LTR_IDLE_TIMER_ID)
#define BITS_LTR_IDLE_TIMER_ID				(BIT_MASK_LTR_IDLE_TIMER_ID << BIT_SHIFT_LTR_IDLE_TIMER_ID)
#define BIT_CLEAR_LTR_IDLE_TIMER_ID(x)			((x) & (~BITS_LTR_IDLE_TIMER_ID))
#define BIT_GET_LTR_IDLE_TIMER_ID(x)			(((x) >> BIT_SHIFT_LTR_IDLE_TIMER_ID) & BIT_MASK_LTR_IDLE_TIMER_ID)
#define BIT_SET_LTR_IDLE_TIMER_ID(x, v)		(BIT_CLEAR_LTR_IDLE_TIMER_ID(x) | BIT_LTR_IDLE_TIMER_ID(v))

#define BIT_SHIFT_BLKHWBCN_TIMER_ID			9
#define BIT_MASK_BLKHWBCN_TIMER_ID			0x7
#define BIT_BLKHWBCN_TIMER_ID(x)			(((x) & BIT_MASK_BLKHWBCN_TIMER_ID) << BIT_SHIFT_BLKHWBCN_TIMER_ID)
#define BITS_BLKHWBCN_TIMER_ID				(BIT_MASK_BLKHWBCN_TIMER_ID << BIT_SHIFT_BLKHWBCN_TIMER_ID)
#define BIT_CLEAR_BLKHWBCN_TIMER_ID(x)			((x) & (~BITS_BLKHWBCN_TIMER_ID))
#define BIT_GET_BLKHWBCN_TIMER_ID(x)			(((x) >> BIT_SHIFT_BLKHWBCN_TIMER_ID) & BIT_MASK_BLKHWBCN_TIMER_ID)
#define BIT_SET_BLKHWBCN_TIMER_ID(x, v)		(BIT_CLEAR_BLKHWBCN_TIMER_ID(x) | BIT_BLKHWBCN_TIMER_ID(v))

#define BIT_OBFF_LTRIDLE_EN				BIT(8)
#define BIT_CFG_DELAY_LTR_ACT				BIT(7)
#define BIT_CFG_CTS_LTRACT				BIT(6)
#define BIT_LTRIDLE_NO_SNOOP				BIT(5)
#define BIT_LTRACT_EN_INCPUACT				BIT(4)
#define BIT_APP_REQ_LTRACT				BIT(3)
#define BIT_APP_REQ_LTRIDLE				BIT(2)
#define BIT_LTR_HW_EN					BIT(1)
#define BIT_LTR_EN					BIT(0)

/* 2 REG_LTR_CTRL2				(Offset 0x07A8) */

#define BIT_SHIFT_OBFF_TIMER_ID_HIGH			29
#define BIT_MASK_OBFF_TIMER_ID_HIGH			0x7
#define BIT_OBFF_TIMER_ID_HIGH(x)			(((x) & BIT_MASK_OBFF_TIMER_ID_HIGH) << BIT_SHIFT_OBFF_TIMER_ID_HIGH)
#define BITS_OBFF_TIMER_ID_HIGH			(BIT_MASK_OBFF_TIMER_ID_HIGH << BIT_SHIFT_OBFF_TIMER_ID_HIGH)
#define BIT_CLEAR_OBFF_TIMER_ID_HIGH(x)		((x) & (~BITS_OBFF_TIMER_ID_HIGH))
#define BIT_GET_OBFF_TIMER_ID_HIGH(x)			(((x) >> BIT_SHIFT_OBFF_TIMER_ID_HIGH) & BIT_MASK_OBFF_TIMER_ID_HIGH)
#define BIT_SET_OBFF_TIMER_ID_HIGH(x, v)		(BIT_CLEAR_OBFF_TIMER_ID_HIGH(x) | BIT_OBFF_TIMER_ID_HIGH(v))

#define BIT_SHIFT_HIGH_RATE_BDRY			16
#define BIT_MASK_HIGH_RATE_BDRY			0x7f
#define BIT_HIGH_RATE_BDRY(x)				(((x) & BIT_MASK_HIGH_RATE_BDRY) << BIT_SHIFT_HIGH_RATE_BDRY)
#define BITS_HIGH_RATE_BDRY				(BIT_MASK_HIGH_RATE_BDRY << BIT_SHIFT_HIGH_RATE_BDRY)
#define BIT_CLEAR_HIGH_RATE_BDRY(x)			((x) & (~BITS_HIGH_RATE_BDRY))
#define BIT_GET_HIGH_RATE_BDRY(x)			(((x) >> BIT_SHIFT_HIGH_RATE_BDRY) & BIT_MASK_HIGH_RATE_BDRY)
#define BIT_SET_HIGH_RATE_BDRY(x, v)			(BIT_CLEAR_HIGH_RATE_BDRY(x) | BIT_HIGH_RATE_BDRY(v))

#define BIT_SHIFT_LOW_RATE_BDRY			9
#define BIT_MASK_LOW_RATE_BDRY				0x7f
#define BIT_LOW_RATE_BDRY(x)				(((x) & BIT_MASK_LOW_RATE_BDRY) << BIT_SHIFT_LOW_RATE_BDRY)
#define BITS_LOW_RATE_BDRY				(BIT_MASK_LOW_RATE_BDRY << BIT_SHIFT_LOW_RATE_BDRY)
#define BIT_CLEAR_LOW_RATE_BDRY(x)			((x) & (~BITS_LOW_RATE_BDRY))
#define BIT_GET_LOW_RATE_BDRY(x)			(((x) >> BIT_SHIFT_LOW_RATE_BDRY) & BIT_MASK_LOW_RATE_BDRY)
#define BIT_SET_LOW_RATE_BDRY(x, v)			(BIT_CLEAR_LOW_RATE_BDRY(x) | BIT_LOW_RATE_BDRY(v))

#define BIT_SHIFT_HIGH_RATE_TRIGS			7
#define BIT_MASK_HIGH_RATE_TRIGS			0x3
#define BIT_HIGH_RATE_TRIGS(x)				(((x) & BIT_MASK_HIGH_RATE_TRIGS) << BIT_SHIFT_HIGH_RATE_TRIGS)
#define BITS_HIGH_RATE_TRIGS				(BIT_MASK_HIGH_RATE_TRIGS << BIT_SHIFT_HIGH_RATE_TRIGS)
#define BIT_CLEAR_HIGH_RATE_TRIGS(x)			((x) & (~BITS_HIGH_RATE_TRIGS))
#define BIT_GET_HIGH_RATE_TRIGS(x)			(((x) >> BIT_SHIFT_HIGH_RATE_TRIGS) & BIT_MASK_HIGH_RATE_TRIGS)
#define BIT_SET_HIGH_RATE_TRIGS(x, v)			(BIT_CLEAR_HIGH_RATE_TRIGS(x) | BIT_HIGH_RATE_TRIGS(v))

#define BIT_SHIFT_MEDIA_RATE_TRIGS			5
#define BIT_MASK_MEDIA_RATE_TRIGS			0x3
#define BIT_MEDIA_RATE_TRIGS(x)			(((x) & BIT_MASK_MEDIA_RATE_TRIGS) << BIT_SHIFT_MEDIA_RATE_TRIGS)
#define BITS_MEDIA_RATE_TRIGS				(BIT_MASK_MEDIA_RATE_TRIGS << BIT_SHIFT_MEDIA_RATE_TRIGS)
#define BIT_CLEAR_MEDIA_RATE_TRIGS(x)			((x) & (~BITS_MEDIA_RATE_TRIGS))
#define BIT_GET_MEDIA_RATE_TRIGS(x)			(((x) >> BIT_SHIFT_MEDIA_RATE_TRIGS) & BIT_MASK_MEDIA_RATE_TRIGS)
#define BIT_SET_MEDIA_RATE_TRIGS(x, v)			(BIT_CLEAR_MEDIA_RATE_TRIGS(x) | BIT_MEDIA_RATE_TRIGS(v))

#define BIT_SHIFT_LOW_RATE_TRIGS			3
#define BIT_MASK_LOW_RATE_TRIGS			0x3
#define BIT_LOW_RATE_TRIGS(x)				(((x) & BIT_MASK_LOW_RATE_TRIGS) << BIT_SHIFT_LOW_RATE_TRIGS)
#define BITS_LOW_RATE_TRIGS				(BIT_MASK_LOW_RATE_TRIGS << BIT_SHIFT_LOW_RATE_TRIGS)
#define BIT_CLEAR_LOW_RATE_TRIGS(x)			((x) & (~BITS_LOW_RATE_TRIGS))
#define BIT_GET_LOW_RATE_TRIGS(x)			(((x) >> BIT_SHIFT_LOW_RATE_TRIGS) & BIT_MASK_LOW_RATE_TRIGS)
#define BIT_SET_LOW_RATE_TRIGS(x, v)			(BIT_CLEAR_LOW_RATE_TRIGS(x) | BIT_LOW_RATE_TRIGS(v))

#define BIT_SHIFT_RX_EXHAUST_ID			0
#define BIT_MASK_RX_EXHAUST_ID				0x7
#define BIT_RX_EXHAUST_ID(x)				(((x) & BIT_MASK_RX_EXHAUST_ID) << BIT_SHIFT_RX_EXHAUST_ID)
#define BITS_RX_EXHAUST_ID				(BIT_MASK_RX_EXHAUST_ID << BIT_SHIFT_RX_EXHAUST_ID)
#define BIT_CLEAR_RX_EXHAUST_ID(x)			((x) & (~BITS_RX_EXHAUST_ID))
#define BIT_GET_RX_EXHAUST_ID(x)			(((x) >> BIT_SHIFT_RX_EXHAUST_ID) & BIT_MASK_RX_EXHAUST_ID)
#define BIT_SET_RX_EXHAUST_ID(x, v)			(BIT_CLEAR_RX_EXHAUST_ID(x) | BIT_RX_EXHAUST_ID(v))

/* 2 REG_ANTTRN_CTR_V1			(Offset 0x07B0) */

#define BIT_SHIFT_TRAIN_STA_ADDR_1			0
#define BIT_MASK_TRAIN_STA_ADDR_1			0xffffffffL
#define BIT_TRAIN_STA_ADDR_1(x)			(((x) & BIT_MASK_TRAIN_STA_ADDR_1) << BIT_SHIFT_TRAIN_STA_ADDR_1)
#define BITS_TRAIN_STA_ADDR_1				(BIT_MASK_TRAIN_STA_ADDR_1 << BIT_SHIFT_TRAIN_STA_ADDR_1)
#define BIT_CLEAR_TRAIN_STA_ADDR_1(x)			((x) & (~BITS_TRAIN_STA_ADDR_1))
#define BIT_GET_TRAIN_STA_ADDR_1(x)			(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1) & BIT_MASK_TRAIN_STA_ADDR_1)
#define BIT_SET_TRAIN_STA_ADDR_1(x, v)			(BIT_CLEAR_TRAIN_STA_ADDR_1(x) | BIT_TRAIN_STA_ADDR_1(v))

/* 2 REG_ANTTRN_CTR				(Offset 0x07B4) */

#define BIT_ANTTRN_SWITCH				BIT(19)
#define BIT_APPEND_MACID_IN_RESP_EN			BIT(18)
#define BIT_ADDR2_MATCH_EN				BIT(17)
#define BIT_ANTTRN_EN					BIT(16)

#define BIT_SHIFT_TRAIN_STA_ADDR_2			0
#define BIT_MASK_TRAIN_STA_ADDR_2			0xffff
#define BIT_TRAIN_STA_ADDR_2(x)			(((x) & BIT_MASK_TRAIN_STA_ADDR_2) << BIT_SHIFT_TRAIN_STA_ADDR_2)
#define BITS_TRAIN_STA_ADDR_2				(BIT_MASK_TRAIN_STA_ADDR_2 << BIT_SHIFT_TRAIN_STA_ADDR_2)
#define BIT_CLEAR_TRAIN_STA_ADDR_2(x)			((x) & (~BITS_TRAIN_STA_ADDR_2))
#define BIT_GET_TRAIN_STA_ADDR_2(x)			(((x) >> BIT_SHIFT_TRAIN_STA_ADDR_2) & BIT_MASK_TRAIN_STA_ADDR_2)
#define BIT_SET_TRAIN_STA_ADDR_2(x, v)			(BIT_CLEAR_TRAIN_STA_ADDR_2(x) | BIT_TRAIN_STA_ADDR_2(v))

/* 2 REG_WMAC_PKTCNT_RWD			(Offset 0x07B8) */

#define BIT_SHIFT_PKTCNT_BSSIDMAP			4
#define BIT_MASK_PKTCNT_BSSIDMAP			0xf
#define BIT_PKTCNT_BSSIDMAP(x)				(((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP)
#define BITS_PKTCNT_BSSIDMAP				(BIT_MASK_PKTCNT_BSSIDMAP << BIT_SHIFT_PKTCNT_BSSIDMAP)
#define BIT_CLEAR_PKTCNT_BSSIDMAP(x)			((x) & (~BITS_PKTCNT_BSSIDMAP))
#define BIT_GET_PKTCNT_BSSIDMAP(x)			(((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP)
#define BIT_SET_PKTCNT_BSSIDMAP(x, v)			(BIT_CLEAR_PKTCNT_BSSIDMAP(x) | BIT_PKTCNT_BSSIDMAP(v))

#define BIT_PKTCNT_CNTRST				BIT(1)
#define BIT_PKTCNT_CNTEN				BIT(0)

/* 2 REG_WMAC_PKTCNT_CTRL			(Offset 0x07BC) */

#define BIT_WMAC_PKTCNT_FEN				BIT(8)

#define BIT_SHIFT_WMAC_PKTCNT_CFGAD			0
#define BIT_MASK_WMAC_PKTCNT_CFGAD			0xff
#define BIT_WMAC_PKTCNT_CFGAD(x)			(((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD)
#define BITS_WMAC_PKTCNT_CFGAD				(BIT_MASK_WMAC_PKTCNT_CFGAD << BIT_SHIFT_WMAC_PKTCNT_CFGAD)
#define BIT_CLEAR_WMAC_PKTCNT_CFGAD(x)			((x) & (~BITS_WMAC_PKTCNT_CFGAD))
#define BIT_GET_WMAC_PKTCNT_CFGAD(x)			(((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD)
#define BIT_SET_WMAC_PKTCNT_CFGAD(x, v)		(BIT_CLEAR_WMAC_PKTCNT_CFGAD(x) | BIT_WMAC_PKTCNT_CFGAD(v))

/* 2 REG_IQ_DUMP				(Offset 0x07C0) */

#define BIT_SHIFT_DUMP_OK_ADDR				16
#define BIT_MASK_DUMP_OK_ADDR				0xffff
#define BIT_DUMP_OK_ADDR(x)				(((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR)
#define BITS_DUMP_OK_ADDR				(BIT_MASK_DUMP_OK_ADDR << BIT_SHIFT_DUMP_OK_ADDR)
#define BIT_CLEAR_DUMP_OK_ADDR(x)			((x) & (~BITS_DUMP_OK_ADDR))
#define BIT_GET_DUMP_OK_ADDR(x)			(((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR)
#define BIT_SET_DUMP_OK_ADDR(x, v)			(BIT_CLEAR_DUMP_OK_ADDR(x) | BIT_DUMP_OK_ADDR(v))

#define BIT_MACDBG_TRIG_IQDUMP				BIT(15)

#define BIT_SHIFT_R_TRIG_TIME_SEL			8
#define BIT_MASK_R_TRIG_TIME_SEL			0x7f
#define BIT_R_TRIG_TIME_SEL(x)				(((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL)
#define BITS_R_TRIG_TIME_SEL				(BIT_MASK_R_TRIG_TIME_SEL << BIT_SHIFT_R_TRIG_TIME_SEL)
#define BIT_CLEAR_R_TRIG_TIME_SEL(x)			((x) & (~BITS_R_TRIG_TIME_SEL))
#define BIT_GET_R_TRIG_TIME_SEL(x)			(((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL)
#define BIT_SET_R_TRIG_TIME_SEL(x, v)			(BIT_CLEAR_R_TRIG_TIME_SEL(x) | BIT_R_TRIG_TIME_SEL(v))

#define BIT_SHIFT_R_MAC_TRIG_SEL			6
#define BIT_MASK_R_MAC_TRIG_SEL			0x3
#define BIT_R_MAC_TRIG_SEL(x)				(((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL)
#define BITS_R_MAC_TRIG_SEL				(BIT_MASK_R_MAC_TRIG_SEL << BIT_SHIFT_R_MAC_TRIG_SEL)
#define BIT_CLEAR_R_MAC_TRIG_SEL(x)			((x) & (~BITS_R_MAC_TRIG_SEL))
#define BIT_GET_R_MAC_TRIG_SEL(x)			(((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL)
#define BIT_SET_R_MAC_TRIG_SEL(x, v)			(BIT_CLEAR_R_MAC_TRIG_SEL(x) | BIT_R_MAC_TRIG_SEL(v))

#define BIT_MAC_TRIG_REG				BIT(5)

#define BIT_SHIFT_R_LEVEL_PULSE_SEL			3
#define BIT_MASK_R_LEVEL_PULSE_SEL			0x3
#define BIT_R_LEVEL_PULSE_SEL(x)			(((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL)
#define BITS_R_LEVEL_PULSE_SEL				(BIT_MASK_R_LEVEL_PULSE_SEL << BIT_SHIFT_R_LEVEL_PULSE_SEL)
#define BIT_CLEAR_R_LEVEL_PULSE_SEL(x)			((x) & (~BITS_R_LEVEL_PULSE_SEL))
#define BIT_GET_R_LEVEL_PULSE_SEL(x)			(((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL)
#define BIT_SET_R_LEVEL_PULSE_SEL(x, v)		(BIT_CLEAR_R_LEVEL_PULSE_SEL(x) | BIT_R_LEVEL_PULSE_SEL(v))

#define BIT_EN_LA_MAC					BIT(2)
#define BIT_R_EN_IQDUMP				BIT(1)
#define BIT_R_IQDATA_DUMP				BIT(0)

/* 2 REG_MASK_LA_MAC				(Offset 0x07C4) */

#define BIT_SHIFT_MASK_LA_MAC				0
#define BIT_MASK_MASK_LA_MAC				0xffffffffL
#define BIT_MASK_LA_MAC(x)				(((x) & BIT_MASK_MASK_LA_MAC) << BIT_SHIFT_MASK_LA_MAC)
#define BITS_MASK_LA_MAC				(BIT_MASK_MASK_LA_MAC << BIT_SHIFT_MASK_LA_MAC)
#define BIT_CLEAR_MASK_LA_MAC(x)			((x) & (~BITS_MASK_LA_MAC))
#define BIT_GET_MASK_LA_MAC(x)				(((x) >> BIT_SHIFT_MASK_LA_MAC) & BIT_MASK_MASK_LA_MAC)
#define BIT_SET_MASK_LA_MAC(x, v)			(BIT_CLEAR_MASK_LA_MAC(x) | BIT_MASK_LA_MAC(v))

/* 2 REG_MATCH_REF_MAC			(Offset 0x07C8) */

#define BIT_SHIFT_MATCH_REF_MAC			0
#define BIT_MASK_MATCH_REF_MAC				0xffffffffL
#define BIT_MATCH_REF_MAC(x)				(((x) & BIT_MASK_MATCH_REF_MAC) << BIT_SHIFT_MATCH_REF_MAC)
#define BITS_MATCH_REF_MAC				(BIT_MASK_MATCH_REF_MAC << BIT_SHIFT_MATCH_REF_MAC)
#define BIT_CLEAR_MATCH_REF_MAC(x)			((x) & (~BITS_MATCH_REF_MAC))
#define BIT_GET_MATCH_REF_MAC(x)			(((x) >> BIT_SHIFT_MATCH_REF_MAC) & BIT_MASK_MATCH_REF_MAC)
#define BIT_SET_MATCH_REF_MAC(x, v)			(BIT_CLEAR_MATCH_REF_MAC(x) | BIT_MATCH_REF_MAC(v))

/* 2 REG_WMAC_FTM_CTL			(Offset 0x07CC) */

#define BIT_RXFTM_TXACK_SC				BIT(6)
#define BIT_RXFTM_TXACK_BW				BIT(5)
#define BIT_RXFTM_EN					BIT(3)
#define BIT_RXFTMREQ_BYDRV				BIT(2)
#define BIT_RXFTMREQ_EN				BIT(1)
#define BIT_FTM_EN					BIT(0)

/* 2 REG_WMAC_LA_DUMP_FUNC_EXT		(Offset 0x07CE) */

#define BIT_EN_TIMEOUT					BIT(13)
#define BIT_EN_RE_START				BIT(12)

#define BIT_SHIFT_LA_MAC_TIMEOUT_UNIT_SEL		10
#define BIT_MASK_LA_MAC_TIMEOUT_UNIT_SEL		0x3
#define BIT_LA_MAC_TIMEOUT_UNIT_SEL(x)			(((x) & BIT_MASK_LA_MAC_TIMEOUT_UNIT_SEL) << BIT_SHIFT_LA_MAC_TIMEOUT_UNIT_SEL)
#define BITS_LA_MAC_TIMEOUT_UNIT_SEL			(BIT_MASK_LA_MAC_TIMEOUT_UNIT_SEL << BIT_SHIFT_LA_MAC_TIMEOUT_UNIT_SEL)
#define BIT_CLEAR_LA_MAC_TIMEOUT_UNIT_SEL(x)		((x) & (~BITS_LA_MAC_TIMEOUT_UNIT_SEL))
#define BIT_GET_LA_MAC_TIMEOUT_UNIT_SEL(x)		(((x) >> BIT_SHIFT_LA_MAC_TIMEOUT_UNIT_SEL) & BIT_MASK_LA_MAC_TIMEOUT_UNIT_SEL)
#define BIT_SET_LA_MAC_TIMEOUT_UNIT_SEL(x, v)		(BIT_CLEAR_LA_MAC_TIMEOUT_UNIT_SEL(x) | BIT_LA_MAC_TIMEOUT_UNIT_SEL(v))

#define BIT_SHIFT_LA_MAC_TIMEOUT_VALUE			4
#define BIT_MASK_LA_MAC_TIMEOUT_VALUE			0x3f
#define BIT_LA_MAC_TIMEOUT_VALUE(x)			(((x) & BIT_MASK_LA_MAC_TIMEOUT_VALUE) << BIT_SHIFT_LA_MAC_TIMEOUT_VALUE)
#define BITS_LA_MAC_TIMEOUT_VALUE			(BIT_MASK_LA_MAC_TIMEOUT_VALUE << BIT_SHIFT_LA_MAC_TIMEOUT_VALUE)
#define BIT_CLEAR_LA_MAC_TIMEOUT_VALUE(x)		((x) & (~BITS_LA_MAC_TIMEOUT_VALUE))
#define BIT_GET_LA_MAC_TIMEOUT_VALUE(x)		(((x) >> BIT_SHIFT_LA_MAC_TIMEOUT_VALUE) & BIT_MASK_LA_MAC_TIMEOUT_VALUE)
#define BIT_SET_LA_MAC_TIMEOUT_VALUE(x, v)		(BIT_CLEAR_LA_MAC_TIMEOUT_VALUE(x) | BIT_LA_MAC_TIMEOUT_VALUE(v))

#define BIT_LEVEL_PULSE_SEL_EXT			BIT(3)

#define BIT_SHIFT_TRIG_TIME_UNIT_SEL			0
#define BIT_MASK_TRIG_TIME_UNIT_SEL			0x7
#define BIT_TRIG_TIME_UNIT_SEL(x)			(((x) & BIT_MASK_TRIG_TIME_UNIT_SEL) << BIT_SHIFT_TRIG_TIME_UNIT_SEL)
#define BITS_TRIG_TIME_UNIT_SEL			(BIT_MASK_TRIG_TIME_UNIT_SEL << BIT_SHIFT_TRIG_TIME_UNIT_SEL)
#define BIT_CLEAR_TRIG_TIME_UNIT_SEL(x)		((x) & (~BITS_TRIG_TIME_UNIT_SEL))
#define BIT_GET_TRIG_TIME_UNIT_SEL(x)			(((x) >> BIT_SHIFT_TRIG_TIME_UNIT_SEL) & BIT_MASK_TRIG_TIME_UNIT_SEL)
#define BIT_SET_TRIG_TIME_UNIT_SEL(x, v)		(BIT_CLEAR_TRIG_TIME_UNIT_SEL(x) | BIT_TRIG_TIME_UNIT_SEL(v))

/* 2 REG_OFDM_CCK_LEN_MASK			(Offset 0x07D0) */

#define BIT_SHIFT_OFDM_LEN_TH				16
#define BIT_MASK_OFDM_LEN_TH				0xffff
#define BIT_OFDM_LEN_TH(x)				(((x) & BIT_MASK_OFDM_LEN_TH) << BIT_SHIFT_OFDM_LEN_TH)
#define BITS_OFDM_LEN_TH				(BIT_MASK_OFDM_LEN_TH << BIT_SHIFT_OFDM_LEN_TH)
#define BIT_CLEAR_OFDM_LEN_TH(x)			((x) & (~BITS_OFDM_LEN_TH))
#define BIT_GET_OFDM_LEN_TH(x)				(((x) >> BIT_SHIFT_OFDM_LEN_TH) & BIT_MASK_OFDM_LEN_TH)
#define BIT_SET_OFDM_LEN_TH(x, v)			(BIT_CLEAR_OFDM_LEN_TH(x) | BIT_OFDM_LEN_TH(v))

#define BIT_SHIFT_CCK_LEN_TH				0
#define BIT_MASK_CCK_LEN_TH				0xffff
#define BIT_CCK_LEN_TH(x)				(((x) & BIT_MASK_CCK_LEN_TH) << BIT_SHIFT_CCK_LEN_TH)
#define BITS_CCK_LEN_TH				(BIT_MASK_CCK_LEN_TH << BIT_SHIFT_CCK_LEN_TH)
#define BIT_CLEAR_CCK_LEN_TH(x)			((x) & (~BITS_CCK_LEN_TH))
#define BIT_GET_CCK_LEN_TH(x)				(((x) >> BIT_SHIFT_CCK_LEN_TH) & BIT_MASK_CCK_LEN_TH)
#define BIT_SET_CCK_LEN_TH(x, v)			(BIT_CLEAR_CCK_LEN_TH(x) | BIT_CCK_LEN_TH(v))

/* 2 REG_WMAC_OPTION_FUNCTION_1		(Offset 0x07D4) */

#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1		24
#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1		0xff
#define BIT_R_WMAC_RXFIFO_FULL_TH_1(x)			(((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1)
#define BITS_R_WMAC_RXFIFO_FULL_TH_1			(BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1)
#define BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x)		((x) & (~BITS_R_WMAC_RXFIFO_FULL_TH_1))
#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1(x)		(((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1)
#define BIT_SET_R_WMAC_RXFIFO_FULL_TH_1(x, v)		(BIT_CLEAR_R_WMAC_RXFIFO_FULL_TH_1(x) | BIT_R_WMAC_RXFIFO_FULL_TH_1(v))

#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1			BIT(23)
#define BIT_R_WMAC_RXRST_DLY_1				BIT(22)
#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1		BIT(21)
#define BIT_R_WMAC_SRCH_TXRPT_UA1_1			BIT(20)
#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1			BIT(19)
#define BIT_R_WMAC_NDP_RST_1				BIT(18)
#define BIT_R_WMAC_POWINT_EN_1				BIT(17)
#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1			BIT(16)
#define BIT_R_WMAC_SRCH_TXRPT_MID_1			BIT(15)
#define BIT_R_WMAC_PFIN_TOEN_1				BIT(14)
#define BIT_R_WMAC_FIL_SECERR_1			BIT(13)
#define BIT_R_WMAC_FIL_CTLPKTLEN_1			BIT(12)
#define BIT_R_WMAC_FIL_FCTYPE_1			BIT(11)
#define BIT_R_WMAC_FIL_FCPROVER_1			BIT(10)
#define BIT_R_WMAC_PHYSTS_SNIF_1			BIT(9)
#define BIT_R_WMAC_PHYSTS_PLCP_1			BIT(8)
#define BIT_R_MAC_TCR_VBONF_RD_1			BIT(7)
#define BIT_R_WMAC_TCR_MPAR_NDP_1			BIT(6)
#define BIT_R_WMAC_NDP_FILTER_1			BIT(5)
#define BIT_R_WMAC_RXLEN_SEL_1				BIT(4)
#define BIT_R_WMAC_RXLEN_SEL1_1			BIT(3)
#define BIT_R_OFDM_FILTER_1				BIT(2)
#define BIT_R_WMAC_CHK_OFDM_LEN_1			BIT(1)
#define BIT_R_WMAC_CHK_CCK_LEN_1			BIT(0)

/* 2 REG_WMAC_OPTION_FUNCTION_2		(Offset 0x07D8) */

#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2			0
#define BIT_MASK_R_WMAC_RX_FIL_LEN_2			0xffff
#define BIT_R_WMAC_RX_FIL_LEN_2(x)			(((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2)
#define BITS_R_WMAC_RX_FIL_LEN_2			(BIT_MASK_R_WMAC_RX_FIL_LEN_2 << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2)
#define BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x)		((x) & (~BITS_R_WMAC_RX_FIL_LEN_2))
#define BIT_GET_R_WMAC_RX_FIL_LEN_2(x)			(((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2) & BIT_MASK_R_WMAC_RX_FIL_LEN_2)
#define BIT_SET_R_WMAC_RX_FIL_LEN_2(x, v)		(BIT_CLEAR_R_WMAC_RX_FIL_LEN_2(x) | BIT_R_WMAC_RX_FIL_LEN_2(v))

/* 2 REG_RX_FILTER_FUNCTION			(Offset 0x07DA) */

#define BIT_RXHANG_EN					BIT(15)
#define BIT_R_WMAC_MHRDDY_LATCH			BIT(14)
#define BIT_R_WMAC_MHRDDY_CLR				BIT(13)
#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1		BIT(12)
#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU			BIT(11)
#define BIT_R_CHK_DELIMIT_LEN				BIT(10)
#define BIT_R_REAPTER_ADDR_MATCH			BIT(9)
#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY		BIT(8)
#define BIT_R_LATCH_MACHRDY				BIT(7)
#define BIT_R_WMAC_RXFIL_REND				BIT(6)
#define BIT_R_WMAC_MPDURDY_CLR				BIT(5)
#define BIT_R_WMAC_CLRRXSEC				BIT(4)
#define BIT_R_WMAC_RXFIL_RDEL				BIT(3)
#define BIT_R_WMAC_RXFIL_FCSE				BIT(2)
#define BIT_R_WMAC_RXFIL_MESH_DEL			BIT(1)
#define BIT_R_WMAC_RXFIL_MASKM				BIT(0)

/* 2 REG_RX_BEACON_LENGTH			(Offset 0x07DC) */

#define BIT_SHIFT_RX_BCN_LEN				0
#define BIT_MASK_RX_BCN_LEN				0xffff
#define BIT_RX_BCN_LEN(x)				(((x) & BIT_MASK_RX_BCN_LEN) << BIT_SHIFT_RX_BCN_LEN)
#define BITS_RX_BCN_LEN				(BIT_MASK_RX_BCN_LEN << BIT_SHIFT_RX_BCN_LEN)
#define BIT_CLEAR_RX_BCN_LEN(x)			((x) & (~BITS_RX_BCN_LEN))
#define BIT_GET_RX_BCN_LEN(x)				(((x) >> BIT_SHIFT_RX_BCN_LEN) & BIT_MASK_RX_BCN_LEN)
#define BIT_SET_RX_BCN_LEN(x, v)			(BIT_CLEAR_RX_BCN_LEN(x) | BIT_RX_BCN_LEN(v))

/* 2 REG_NDP_SIG				(Offset 0x07E0) */

#define BIT_SHIFT_R_WMAC_TXNDP_SIGB			0
#define BIT_MASK_R_WMAC_TXNDP_SIGB			0x1fffff
#define BIT_R_WMAC_TXNDP_SIGB(x)			(((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB)
#define BITS_R_WMAC_TXNDP_SIGB				(BIT_MASK_R_WMAC_TXNDP_SIGB << BIT_SHIFT_R_WMAC_TXNDP_SIGB)
#define BIT_CLEAR_R_WMAC_TXNDP_SIGB(x)			((x) & (~BITS_R_WMAC_TXNDP_SIGB))
#define BIT_GET_R_WMAC_TXNDP_SIGB(x)			(((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB)
#define BIT_SET_R_WMAC_TXNDP_SIGB(x, v)		(BIT_CLEAR_R_WMAC_TXNDP_SIGB(x) | BIT_R_WMAC_TXNDP_SIGB(v))

/* 2 REG_WSEC_OPTION				(Offset 0x07EC) */

#define BIT_RXDEC_BM_MGNT				BIT(22)
#define BIT_TXENC_BM_MGNT				BIT(21)
#define BIT_RXDEC_UNI_MGNT				BIT(20)
#define BIT_TXENC_UNI_MGNT				BIT(19)
#define BIT_WMAC_SEC_MASKIV				BIT(18)

#define BIT_SHIFT_WMAC_SEC_PN_SEL			16
#define BIT_MASK_WMAC_SEC_PN_SEL			0x3
#define BIT_WMAC_SEC_PN_SEL(x)				(((x) & BIT_MASK_WMAC_SEC_PN_SEL) << BIT_SHIFT_WMAC_SEC_PN_SEL)
#define BITS_WMAC_SEC_PN_SEL				(BIT_MASK_WMAC_SEC_PN_SEL << BIT_SHIFT_WMAC_SEC_PN_SEL)
#define BIT_CLEAR_WMAC_SEC_PN_SEL(x)			((x) & (~BITS_WMAC_SEC_PN_SEL))
#define BIT_GET_WMAC_SEC_PN_SEL(x)			(((x) >> BIT_SHIFT_WMAC_SEC_PN_SEL) & BIT_MASK_WMAC_SEC_PN_SEL)
#define BIT_SET_WMAC_SEC_PN_SEL(x, v)			(BIT_CLEAR_WMAC_SEC_PN_SEL(x) | BIT_WMAC_SEC_PN_SEL(v))

#define BIT_SHIFT_BT_TIME_CNT				0
#define BIT_MASK_BT_TIME_CNT				0xff
#define BIT_BT_TIME_CNT(x)				(((x) & BIT_MASK_BT_TIME_CNT) << BIT_SHIFT_BT_TIME_CNT)
#define BITS_BT_TIME_CNT				(BIT_MASK_BT_TIME_CNT << BIT_SHIFT_BT_TIME_CNT)
#define BIT_CLEAR_BT_TIME_CNT(x)			((x) & (~BITS_BT_TIME_CNT))
#define BIT_GET_BT_TIME_CNT(x)				(((x) >> BIT_SHIFT_BT_TIME_CNT) & BIT_MASK_BT_TIME_CNT)
#define BIT_SET_BT_TIME_CNT(x, v)			(BIT_CLEAR_BT_TIME_CNT(x) | BIT_BT_TIME_CNT(v))

/* 2 REG_RTS_ADDRESS_0			(Offset 0x07F0) */

#define BIT_SHIFT_R_WMAC_RTS_ADDR0			0
#define BIT_MASK_R_WMAC_RTS_ADDR0			0xffffffffL
#define BIT_R_WMAC_RTS_ADDR0(x)			(((x) & BIT_MASK_R_WMAC_RTS_ADDR0) << BIT_SHIFT_R_WMAC_RTS_ADDR0)
#define BITS_R_WMAC_RTS_ADDR0				(BIT_MASK_R_WMAC_RTS_ADDR0 << BIT_SHIFT_R_WMAC_RTS_ADDR0)
#define BIT_CLEAR_R_WMAC_RTS_ADDR0(x)			((x) & (~BITS_R_WMAC_RTS_ADDR0))
#define BIT_GET_R_WMAC_RTS_ADDR0(x)			(((x) >> BIT_SHIFT_R_WMAC_RTS_ADDR0) & BIT_MASK_R_WMAC_RTS_ADDR0)
#define BIT_SET_R_WMAC_RTS_ADDR0(x, v)			(BIT_CLEAR_R_WMAC_RTS_ADDR0(x) | BIT_R_WMAC_RTS_ADDR0(v))

/* 2 REG_RTS_ADDRESS_0_1			(Offset 0x07F4) */

#define BIT_SHIFT_R_WMAC_RTS_ADDR0_1			0
#define BIT_MASK_R_WMAC_RTS_ADDR0_1			0xffff
#define BIT_R_WMAC_RTS_ADDR0_1(x)			(((x) & BIT_MASK_R_WMAC_RTS_ADDR0_1) << BIT_SHIFT_R_WMAC_RTS_ADDR0_1)
#define BITS_R_WMAC_RTS_ADDR0_1			(BIT_MASK_R_WMAC_RTS_ADDR0_1 << BIT_SHIFT_R_WMAC_RTS_ADDR0_1)
#define BIT_CLEAR_R_WMAC_RTS_ADDR0_1(x)		((x) & (~BITS_R_WMAC_RTS_ADDR0_1))
#define BIT_GET_R_WMAC_RTS_ADDR0_1(x)			(((x) >> BIT_SHIFT_R_WMAC_RTS_ADDR0_1) & BIT_MASK_R_WMAC_RTS_ADDR0_1)
#define BIT_SET_R_WMAC_RTS_ADDR0_1(x, v)		(BIT_CLEAR_R_WMAC_RTS_ADDR0_1(x) | BIT_R_WMAC_RTS_ADDR0_1(v))

/* 2 REG_RTS_ADDRESS_1			(Offset 0x07F8) */

#define BIT_SHIFT_R_WMAC_RTS_ADDR1			0
#define BIT_MASK_R_WMAC_RTS_ADDR1			0xffffffffL
#define BIT_R_WMAC_RTS_ADDR1(x)			(((x) & BIT_MASK_R_WMAC_RTS_ADDR1) << BIT_SHIFT_R_WMAC_RTS_ADDR1)
#define BITS_R_WMAC_RTS_ADDR1				(BIT_MASK_R_WMAC_RTS_ADDR1 << BIT_SHIFT_R_WMAC_RTS_ADDR1)
#define BIT_CLEAR_R_WMAC_RTS_ADDR1(x)			((x) & (~BITS_R_WMAC_RTS_ADDR1))
#define BIT_GET_R_WMAC_RTS_ADDR1(x)			(((x) >> BIT_SHIFT_R_WMAC_RTS_ADDR1) & BIT_MASK_R_WMAC_RTS_ADDR1)
#define BIT_SET_R_WMAC_RTS_ADDR1(x, v)			(BIT_CLEAR_R_WMAC_RTS_ADDR1(x) | BIT_R_WMAC_RTS_ADDR1(v))

/* 2 REG_RTS_ADDRESS_1_1			(Offset 0x07FC) */

#define BIT_SHIFT_R_WMAC_RTS_ADDR1_1			0
#define BIT_MASK_R_WMAC_RTS_ADDR1_1			0xffff
#define BIT_R_WMAC_RTS_ADDR1_1(x)			(((x) & BIT_MASK_R_WMAC_RTS_ADDR1_1) << BIT_SHIFT_R_WMAC_RTS_ADDR1_1)
#define BITS_R_WMAC_RTS_ADDR1_1			(BIT_MASK_R_WMAC_RTS_ADDR1_1 << BIT_SHIFT_R_WMAC_RTS_ADDR1_1)
#define BIT_CLEAR_R_WMAC_RTS_ADDR1_1(x)		((x) & (~BITS_R_WMAC_RTS_ADDR1_1))
#define BIT_GET_R_WMAC_RTS_ADDR1_1(x)			(((x) >> BIT_SHIFT_R_WMAC_RTS_ADDR1_1) & BIT_MASK_R_WMAC_RTS_ADDR1_1)
#define BIT_SET_R_WMAC_RTS_ADDR1_1(x, v)		(BIT_CLEAR_R_WMAC_RTS_ADDR1_1(x) | BIT_R_WMAC_RTS_ADDR1_1(v))

/* 2 REG_EXT_SYS_FUNC_EN			(Offset 0x1000) */

#define BIT_WLCPU_INT_MASK				BIT(20)
#define BIT_OPT_WDT_RST_IOWRP				BIT(19)
#define BIT_IPSEC_FUNC_EN				BIT(18)
#define BIT_DDMA_FUNC_EN				BIT(17)
#define BIT_PLFM_FUNC_EN				BIT(16)
#define BIT_PWC_WL_IRAM3				BIT(13)
#define BIT_PWC_WL_IRAM2				BIT(12)
#define BIT_PWC_SPDIO_OFF2				BIT(11)
#define BIT_PWC_SPDIO_OFF1				BIT(10)
#define BIT_PWC_SPDIO_ON				BIT(9)
#define BIT_ISO_WL_IRAM3_2PP				BIT(7)
#define BIT_ISO_WL_IRAM2_2PP				BIT(6)
#define BIT_ISO_WLDA2PP				BIT(5)
#define BIT_ISO_WLAD2PP				BIT(4)
#define BIT_ISO_SDOFF2_2PP				BIT(3)
#define BIT_ISO_SDOFF1_2PP				BIT(2)
#define BIT_ISO_SDON2PP				BIT(1)

/* 2 REG_EXT_SYS_PW_CTRL			(Offset 0x1004) */

#define BIT_USB_SUS_LDO_VOLT				BIT(5)
#define BIT_SYM_DOP_ALDM				BIT(4)
#define BIT_WLSOP_ALDM					BIT(3)
#define BIT_WLSOP_LDOM					BIT(2)
#define BIT_WLSOP_ESLD					BIT(1)
#define BIT_WLSOP_ELLD					BIT(0)

/* 2 REG_EXT_SYS_CLK_CTRL			(Offset 0x1008) */

#define BIT_SHIFT_SEC_CHECK1				8
#define BIT_MASK_SEC_CHECK1				0xff
#define BIT_SEC_CHECK1(x)				(((x) & BIT_MASK_SEC_CHECK1) << BIT_SHIFT_SEC_CHECK1)
#define BITS_SEC_CHECK1				(BIT_MASK_SEC_CHECK1 << BIT_SHIFT_SEC_CHECK1)
#define BIT_CLEAR_SEC_CHECK1(x)			((x) & (~BITS_SEC_CHECK1))
#define BIT_GET_SEC_CHECK1(x)				(((x) >> BIT_SHIFT_SEC_CHECK1) & BIT_MASK_SEC_CHECK1)
#define BIT_SET_SEC_CHECK1(x, v)			(BIT_CLEAR_SEC_CHECK1(x) | BIT_SEC_CHECK1(v))

#define BIT_R_SYM_ANA_CLK_SEL				BIT(6)
#define BIT_WL_IPSEC_CKEN				BIT(5)
#define BIT_WLSLP_CLK_32K				BIT(4)

#define BIT_SHIFT_SEC_CLK_SEL				2
#define BIT_MASK_SEC_CLK_SEL				0x3
#define BIT_SEC_CLK_SEL(x)				(((x) & BIT_MASK_SEC_CLK_SEL) << BIT_SHIFT_SEC_CLK_SEL)
#define BITS_SEC_CLK_SEL				(BIT_MASK_SEC_CLK_SEL << BIT_SHIFT_SEC_CLK_SEL)
#define BIT_CLEAR_SEC_CLK_SEL(x)			((x) & (~BITS_SEC_CLK_SEL))
#define BIT_GET_SEC_CLK_SEL(x)				(((x) >> BIT_SHIFT_SEC_CLK_SEL) & BIT_MASK_SEC_CLK_SEL)
#define BIT_SET_SEC_CLK_SEL(x, v)			(BIT_CLEAR_SEC_CLK_SEL(x) | BIT_SEC_CLK_SEL(v))

#define BIT_WL_PLFM_CKEN				BIT(1)
#define BIT_WL_32L_LP_XTAL				BIT(0)

#define BIT_SHIFT_SEC_CHECK0				0
#define BIT_MASK_SEC_CHECK0				0xff
#define BIT_SEC_CHECK0(x)				(((x) & BIT_MASK_SEC_CHECK0) << BIT_SHIFT_SEC_CHECK0)
#define BITS_SEC_CHECK0				(BIT_MASK_SEC_CHECK0 << BIT_SHIFT_SEC_CHECK0)
#define BIT_CLEAR_SEC_CHECK0(x)			((x) & (~BITS_SEC_CHECK0))
#define BIT_GET_SEC_CHECK0(x)				(((x) >> BIT_SHIFT_SEC_CHECK0) & BIT_MASK_SEC_CHECK0)
#define BIT_SET_SEC_CHECK0(x, v)			(BIT_CLEAR_SEC_CHECK0(x) | BIT_SEC_CHECK0(v))

/* 2 REG_ANAPARSW_MAC_ON_0			(Offset 0x1010) */

#define BIT_PFMCMP_IQ					BIT(31)
#define BIT_REG_EXTERNAL_CLK_SEL_L			BIT(30)
#define BIT_OFF_END_SEL				BIT(29)
#define BIT_POW_MINOFF_L				BIT(28)

#define BIT_SHIFT_COT_I_L				26
#define BIT_MASK_COT_I_L				0x3
#define BIT_COT_I_L(x)					(((x) & BIT_MASK_COT_I_L) << BIT_SHIFT_COT_I_L)
#define BITS_COT_I_L					(BIT_MASK_COT_I_L << BIT_SHIFT_COT_I_L)
#define BIT_CLEAR_COT_I_L(x)				((x) & (~BITS_COT_I_L))
#define BIT_GET_COT_I_L(x)				(((x) >> BIT_SHIFT_COT_I_L) & BIT_MASK_COT_I_L)
#define BIT_SET_COT_I_L(x, v)				(BIT_CLEAR_COT_I_L(x) | BIT_COT_I_L(v))

#define BIT_SHIFT_VREFPFM_L				22
#define BIT_MASK_VREFPFM_L				0xf
#define BIT_VREFPFM_L(x)				(((x) & BIT_MASK_VREFPFM_L) << BIT_SHIFT_VREFPFM_L)
#define BITS_VREFPFM_L					(BIT_MASK_VREFPFM_L << BIT_SHIFT_VREFPFM_L)
#define BIT_CLEAR_VREFPFM_L(x)				((x) & (~BITS_VREFPFM_L))
#define BIT_GET_VREFPFM_L(x)				(((x) >> BIT_SHIFT_VREFPFM_L) & BIT_MASK_VREFPFM_L)
#define BIT_SET_VREFPFM_L(x, v)			(BIT_CLEAR_VREFPFM_L(x) | BIT_VREFPFM_L(v))

#define BIT_FORCE_ZCD_BIAS				BIT(21)

#define BIT_SHIFT_ZCD_SDZ_L				19
#define BIT_MASK_ZCD_SDZ_L				0x3
#define BIT_ZCD_SDZ_L(x)				(((x) & BIT_MASK_ZCD_SDZ_L) << BIT_SHIFT_ZCD_SDZ_L)
#define BITS_ZCD_SDZ_L					(BIT_MASK_ZCD_SDZ_L << BIT_SHIFT_ZCD_SDZ_L)
#define BIT_CLEAR_ZCD_SDZ_L(x)				((x) & (~BITS_ZCD_SDZ_L))
#define BIT_GET_ZCD_SDZ_L(x)				(((x) >> BIT_SHIFT_ZCD_SDZ_L) & BIT_MASK_ZCD_SDZ_L)
#define BIT_SET_ZCD_SDZ_L(x, v)			(BIT_CLEAR_ZCD_SDZ_L(x) | BIT_ZCD_SDZ_L(v))

#define BIT_SHIFT_REG_ZCDC_H				17
#define BIT_MASK_REG_ZCDC_H				0x3
#define BIT_REG_ZCDC_H(x)				(((x) & BIT_MASK_REG_ZCDC_H) << BIT_SHIFT_REG_ZCDC_H)
#define BITS_REG_ZCDC_H				(BIT_MASK_REG_ZCDC_H << BIT_SHIFT_REG_ZCDC_H)
#define BIT_CLEAR_REG_ZCDC_H(x)			((x) & (~BITS_REG_ZCDC_H))
#define BIT_GET_REG_ZCDC_H(x)				(((x) >> BIT_SHIFT_REG_ZCDC_H) & BIT_MASK_REG_ZCDC_H)
#define BIT_SET_REG_ZCDC_H(x, v)			(BIT_CLEAR_REG_ZCDC_H(x) | BIT_REG_ZCDC_H(v))

#define BIT_POW_ZCD_L					BIT(16)

#define BIT_SHIFT_OCP_L1				13
#define BIT_MASK_OCP_L1				0x7
#define BIT_OCP_L1(x)					(((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1)
#define BITS_OCP_L1					(BIT_MASK_OCP_L1 << BIT_SHIFT_OCP_L1)
#define BIT_CLEAR_OCP_L1(x)				((x) & (~BITS_OCP_L1))
#define BIT_GET_OCP_L1(x)				(((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1)
#define BIT_SET_OCP_L1(x, v)				(BIT_CLEAR_OCP_L1(x) | BIT_OCP_L1(v))

#define BIT_POWOCP_L1					BIT(12)

#define BIT_SHIFT_SAW_FREQ_L				8
#define BIT_MASK_SAW_FREQ_L				0xf
#define BIT_SAW_FREQ_L(x)				(((x) & BIT_MASK_SAW_FREQ_L) << BIT_SHIFT_SAW_FREQ_L)
#define BITS_SAW_FREQ_L				(BIT_MASK_SAW_FREQ_L << BIT_SHIFT_SAW_FREQ_L)
#define BIT_CLEAR_SAW_FREQ_L(x)			((x) & (~BITS_SAW_FREQ_L))
#define BIT_GET_SAW_FREQ_L(x)				(((x) >> BIT_SHIFT_SAW_FREQ_L) & BIT_MASK_SAW_FREQ_L)
#define BIT_SET_SAW_FREQ_L(x, v)			(BIT_CLEAR_SAW_FREQ_L(x) | BIT_SAW_FREQ_L(v))

#define BIT_REG_BYPASS_L				BIT(7)
#define BIT_FPWM_L1					BIT(6)

#define BIT_SHIFT_STD_L1				4
#define BIT_MASK_STD_L1				0x3
#define BIT_STD_L1(x)					(((x) & BIT_MASK_STD_L1) << BIT_SHIFT_STD_L1)
#define BITS_STD_L1					(BIT_MASK_STD_L1 << BIT_SHIFT_STD_L1)
#define BIT_CLEAR_STD_L1(x)				((x) & (~BITS_STD_L1))
#define BIT_GET_STD_L1(x)				(((x) >> BIT_SHIFT_STD_L1) & BIT_MASK_STD_L1)
#define BIT_SET_STD_L1(x, v)				(BIT_CLEAR_STD_L1(x) | BIT_STD_L1(v))

#define BIT_SHIFT_VOL_L1				0
#define BIT_MASK_VOL_L1				0xf
#define BIT_VOL_L1(x)					(((x) & BIT_MASK_VOL_L1) << BIT_SHIFT_VOL_L1)
#define BITS_VOL_L1					(BIT_MASK_VOL_L1 << BIT_SHIFT_VOL_L1)
#define BIT_CLEAR_VOL_L1(x)				((x) & (~BITS_VOL_L1))
#define BIT_GET_VOL_L1(x)				(((x) >> BIT_SHIFT_VOL_L1) & BIT_MASK_VOL_L1)
#define BIT_SET_VOL_L1(x, v)				(BIT_CLEAR_VOL_L1(x) | BIT_VOL_L1(v))

/* 2 REG_ANAPARSW_MAC_ON_1			(Offset 0x1014) */

#define BIT_SHIFT_SN_N_L				28
#define BIT_MASK_SN_N_L				0xf
#define BIT_SN_N_L(x)					(((x) & BIT_MASK_SN_N_L) << BIT_SHIFT_SN_N_L)
#define BITS_SN_N_L					(BIT_MASK_SN_N_L << BIT_SHIFT_SN_N_L)
#define BIT_CLEAR_SN_N_L(x)				((x) & (~BITS_SN_N_L))
#define BIT_GET_SN_N_L(x)				(((x) >> BIT_SHIFT_SN_N_L) & BIT_MASK_SN_N_L)
#define BIT_SET_SN_N_L(x, v)				(BIT_CLEAR_SN_N_L(x) | BIT_SN_N_L(v))

#define BIT_SHIFT_SP_N_L				24
#define BIT_MASK_SP_N_L				0xf
#define BIT_SP_N_L(x)					(((x) & BIT_MASK_SP_N_L) << BIT_SHIFT_SP_N_L)
#define BITS_SP_N_L					(BIT_MASK_SP_N_L << BIT_SHIFT_SP_N_L)
#define BIT_CLEAR_SP_N_L(x)				((x) & (~BITS_SP_N_L))
#define BIT_GET_SP_N_L(x)				(((x) >> BIT_SHIFT_SP_N_L) & BIT_MASK_SP_N_L)
#define BIT_SET_SP_N_L(x, v)				(BIT_CLEAR_SP_N_L(x) | BIT_SP_N_L(v))

#define BIT_SHIFT_SN_P_L				20
#define BIT_MASK_SN_P_L				0xf
#define BIT_SN_P_L(x)					(((x) & BIT_MASK_SN_P_L) << BIT_SHIFT_SN_P_L)
#define BITS_SN_P_L					(BIT_MASK_SN_P_L << BIT_SHIFT_SN_P_L)
#define BIT_CLEAR_SN_P_L(x)				((x) & (~BITS_SN_P_L))
#define BIT_GET_SN_P_L(x)				(((x) >> BIT_SHIFT_SN_P_L) & BIT_MASK_SN_P_L)
#define BIT_SET_SN_P_L(x, v)				(BIT_CLEAR_SN_P_L(x) | BIT_SN_P_L(v))

#define BIT_SHIFT_SP_P_L				16
#define BIT_MASK_SP_P_L				0xf
#define BIT_SP_P_L(x)					(((x) & BIT_MASK_SP_P_L) << BIT_SHIFT_SP_P_L)
#define BITS_SP_P_L					(BIT_MASK_SP_P_L << BIT_SHIFT_SP_P_L)
#define BIT_CLEAR_SP_P_L(x)				((x) & (~BITS_SP_P_L))
#define BIT_GET_SP_P_L(x)				(((x) >> BIT_SHIFT_SP_P_L) & BIT_MASK_SP_P_L)
#define BIT_SET_SP_P_L(x, v)				(BIT_CLEAR_SP_P_L(x) | BIT_SP_P_L(v))

#define BIT_VO_DISCHG_PWM_H				BIT(15)
#define BIT_REG_MODE_PREDRIVER				BIT(14)

#define BIT_SHIFT_REG_ADJSLDO_L			10
#define BIT_MASK_REG_ADJSLDO_L				0xf
#define BIT_REG_ADJSLDO_L(x)				(((x) & BIT_MASK_REG_ADJSLDO_L) << BIT_SHIFT_REG_ADJSLDO_L)
#define BITS_REG_ADJSLDO_L				(BIT_MASK_REG_ADJSLDO_L << BIT_SHIFT_REG_ADJSLDO_L)
#define BIT_CLEAR_REG_ADJSLDO_L(x)			((x) & (~BITS_REG_ADJSLDO_L))
#define BIT_GET_REG_ADJSLDO_L(x)			(((x) >> BIT_SHIFT_REG_ADJSLDO_L) & BIT_MASK_REG_ADJSLDO_L)
#define BIT_SET_REG_ADJSLDO_L(x, v)			(BIT_CLEAR_REG_ADJSLDO_L(x) | BIT_REG_ADJSLDO_L(v))

#define BIT_REG_LDOR_L					BIT(9)
#define BIT_PWM_FORCE					BIT(8)
#define BIT_PFM_PD_RST					BIT(7)
#define BIT_VC_PFM_RSTB				BIT(6)
#define BIT_PFM_IN_SEL					BIT(5)
#define BIT_VC_RSTB					BIT(4)
#define BIT_FPWMDELAY					BIT(3)
#define BIT_ENFPWMDELAY_H				BIT(2)
#define BIT_REG_MOS_HALF_L				BIT(1)
#define BIT_CURRENT_SENSE_MOS				BIT(0)

/* 2 REG_ANAPARSW_MAC_1			(Offset 0x101C) */

#define BIT_AGPIO_GPO					BIT(31)
#define BIT_AGPIO_GPE					BIT(30)

#define BIT_SHIFT_AGPIO_DRV				28
#define BIT_MASK_AGPIO_DRV				0x3
#define BIT_AGPIO_DRV(x)				(((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV)
#define BITS_AGPIO_DRV					(BIT_MASK_AGPIO_DRV << BIT_SHIFT_AGPIO_DRV)
#define BIT_CLEAR_AGPIO_DRV(x)				((x) & (~BITS_AGPIO_DRV))
#define BIT_GET_AGPIO_DRV(x)				(((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV)
#define BIT_SET_AGPIO_DRV(x, v)			(BIT_CLEAR_AGPIO_DRV(x) | BIT_AGPIO_DRV(v))

#define BIT_SYN_AGPIO					BIT(27)
#define BIT_VPULSE_LDO_BUF				BIT(24)
#define BIT_VPULSE_LDO_PLL				BIT(23)

#define BIT_SHIFT_LDO_OUT_BUF				21
#define BIT_MASK_LDO_OUT_BUF				0x3
#define BIT_LDO_OUT_BUF(x)				(((x) & BIT_MASK_LDO_OUT_BUF) << BIT_SHIFT_LDO_OUT_BUF)
#define BITS_LDO_OUT_BUF				(BIT_MASK_LDO_OUT_BUF << BIT_SHIFT_LDO_OUT_BUF)
#define BIT_CLEAR_LDO_OUT_BUF(x)			((x) & (~BITS_LDO_OUT_BUF))
#define BIT_GET_LDO_OUT_BUF(x)				(((x) >> BIT_SHIFT_LDO_OUT_BUF) & BIT_MASK_LDO_OUT_BUF)
#define BIT_SET_LDO_OUT_BUF(x, v)			(BIT_CLEAR_LDO_OUT_BUF(x) | BIT_LDO_OUT_BUF(v))

#define BIT_SHIFT_LDO_OUT_PLL				19
#define BIT_MASK_LDO_OUT_PLL				0x3
#define BIT_LDO_OUT_PLL(x)				(((x) & BIT_MASK_LDO_OUT_PLL) << BIT_SHIFT_LDO_OUT_PLL)
#define BITS_LDO_OUT_PLL				(BIT_MASK_LDO_OUT_PLL << BIT_SHIFT_LDO_OUT_PLL)
#define BIT_CLEAR_LDO_OUT_PLL(x)			((x) & (~BITS_LDO_OUT_PLL))
#define BIT_GET_LDO_OUT_PLL(x)				(((x) >> BIT_SHIFT_LDO_OUT_PLL) & BIT_MASK_LDO_OUT_PLL)
#define BIT_SET_LDO_OUT_PLL(x, v)			(BIT_CLEAR_LDO_OUT_PLL(x) | BIT_LDO_OUT_PLL(v))

#define BIT_LDO2PWRCUT_BUF				BIT(18)
#define BIT_LDO2PWRCUT_PLL				BIT(17)
#define BIT_POW_LDO_BUF				BIT(16)
#define BIT_POW_LDO_PLL				BIT(15)

#define BIT_SHIFT_XTAL_GM_REP				13
#define BIT_MASK_XTAL_GM_REP				0x3
#define BIT_XTAL_GM_REP(x)				(((x) & BIT_MASK_XTAL_GM_REP) << BIT_SHIFT_XTAL_GM_REP)
#define BITS_XTAL_GM_REP				(BIT_MASK_XTAL_GM_REP << BIT_SHIFT_XTAL_GM_REP)
#define BIT_CLEAR_XTAL_GM_REP(x)			((x) & (~BITS_XTAL_GM_REP))
#define BIT_GET_XTAL_GM_REP(x)				(((x) >> BIT_SHIFT_XTAL_GM_REP) & BIT_MASK_XTAL_GM_REP)
#define BIT_SET_XTAL_GM_REP(x, v)			(BIT_CLEAR_XTAL_GM_REP(x) | BIT_XTAL_GM_REP(v))

#define BIT_XTAL_DRV_RF_LATCH_NC			BIT(12)
#define BIT_XTAL_LP					BIT(11)
#define BIT_XTAL_GM_SEP_NC				BIT(10)

#define BIT_SHIFT_XTAL_SEL_TOK_NC			7
#define BIT_MASK_XTAL_SEL_TOK_NC			0x7
#define BIT_XTAL_SEL_TOK_NC(x)				(((x) & BIT_MASK_XTAL_SEL_TOK_NC) << BIT_SHIFT_XTAL_SEL_TOK_NC)
#define BITS_XTAL_SEL_TOK_NC				(BIT_MASK_XTAL_SEL_TOK_NC << BIT_SHIFT_XTAL_SEL_TOK_NC)
#define BIT_CLEAR_XTAL_SEL_TOK_NC(x)			((x) & (~BITS_XTAL_SEL_TOK_NC))
#define BIT_GET_XTAL_SEL_TOK_NC(x)			(((x) >> BIT_SHIFT_XTAL_SEL_TOK_NC) & BIT_MASK_XTAL_SEL_TOK_NC)
#define BIT_SET_XTAL_SEL_TOK_NC(x, v)			(BIT_CLEAR_XTAL_SEL_TOK_NC(x) | BIT_XTAL_SEL_TOK_NC(v))

#define BIT_SHIFT_XTAL_CAP_XO				1
#define BIT_MASK_XTAL_CAP_XO				0x3f
#define BIT_XTAL_CAP_XO(x)				(((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO)
#define BITS_XTAL_CAP_XO				(BIT_MASK_XTAL_CAP_XO << BIT_SHIFT_XTAL_CAP_XO)
#define BIT_CLEAR_XTAL_CAP_XO(x)			((x) & (~BITS_XTAL_CAP_XO))
#define BIT_GET_XTAL_CAP_XO(x)				(((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO)
#define BIT_SET_XTAL_CAP_XO(x, v)			(BIT_CLEAR_XTAL_CAP_XO(x) | BIT_XTAL_CAP_XO(v))

#define BIT_XTAL_CAP_XI				BIT(0)

/* 2 REG_ANAPARSW_MAC_2			(Offset 0x1020) */

#define BIT_SHIFT_DIVN_SDM				26
#define BIT_MASK_DIVN_SDM				0x3f
#define BIT_DIVN_SDM(x)				(((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM)
#define BITS_DIVN_SDM					(BIT_MASK_DIVN_SDM << BIT_SHIFT_DIVN_SDM)
#define BIT_CLEAR_DIVN_SDM(x)				((x) & (~BITS_DIVN_SDM))
#define BIT_GET_DIVN_SDM(x)				(((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM)
#define BIT_SET_DIVN_SDM(x, v)				(BIT_CLEAR_DIVN_SDM(x) | BIT_DIVN_SDM(v))

#define BIT_SHIFT_DITHER_SDM				23
#define BIT_MASK_DITHER_SDM				0xf
#define BIT_DITHER_SDM(x)				(((x) & BIT_MASK_DITHER_SDM) << BIT_SHIFT_DITHER_SDM)
#define BITS_DITHER_SDM				(BIT_MASK_DITHER_SDM << BIT_SHIFT_DITHER_SDM)
#define BIT_CLEAR_DITHER_SDM(x)			((x) & (~BITS_DITHER_SDM))
#define BIT_GET_DITHER_SDM(x)				(((x) >> BIT_SHIFT_DITHER_SDM) & BIT_MASK_DITHER_SDM)
#define BIT_SET_DITHER_SDM(x, v)			(BIT_CLEAR_DITHER_SDM(x) | BIT_DITHER_SDM(v))

#define BIT_SHIFT_BB_REF_SEL_AFE_SDM			22
#define BIT_MASK_BB_REF_SEL_AFE_SDM			0xf
#define BIT_BB_REF_SEL_AFE_SDM(x)			(((x) & BIT_MASK_BB_REF_SEL_AFE_SDM) << BIT_SHIFT_BB_REF_SEL_AFE_SDM)
#define BITS_BB_REF_SEL_AFE_SDM			(BIT_MASK_BB_REF_SEL_AFE_SDM << BIT_SHIFT_BB_REF_SEL_AFE_SDM)
#define BIT_CLEAR_BB_REF_SEL_AFE_SDM(x)		((x) & (~BITS_BB_REF_SEL_AFE_SDM))
#define BIT_GET_BB_REF_SEL_AFE_SDM(x)			(((x) >> BIT_SHIFT_BB_REF_SEL_AFE_SDM) & BIT_MASK_BB_REF_SEL_AFE_SDM)
#define BIT_SET_BB_REF_SEL_AFE_SDM(x, v)		(BIT_CLEAR_BB_REF_SEL_AFE_SDM(x) | BIT_BB_REF_SEL_AFE_SDM(v))

#define BIT_ORDER_SDM					BIT(22)
#define BIT_REG_FREF_SEL				BIT(21)
#define BIT_REG_PSEN					BIT(20)

#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM			18
#define BIT_MASK_BB_DBG_SEL_AFE_SDM			0xf
#define BIT_BB_DBG_SEL_AFE_SDM(x)			(((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM)
#define BITS_BB_DBG_SEL_AFE_SDM			(BIT_MASK_BB_DBG_SEL_AFE_SDM << BIT_SHIFT_BB_DBG_SEL_AFE_SDM)
#define BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x)		((x) & (~BITS_BB_DBG_SEL_AFE_SDM))
#define BIT_GET_BB_DBG_SEL_AFE_SDM(x)			(((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM) & BIT_MASK_BB_DBG_SEL_AFE_SDM)
#define BIT_SET_BB_DBG_SEL_AFE_SDM(x, v)		(BIT_CLEAR_BB_DBG_SEL_AFE_SDM(x) | BIT_BB_DBG_SEL_AFE_SDM(v))

#define BIT_REF_SEL_SDM				BIT(17)

#define BIT_SHIFT_REG_PS				17
#define BIT_MASK_REG_PS				0x7
#define BIT_REG_PS(x)					(((x) & BIT_MASK_REG_PS) << BIT_SHIFT_REG_PS)
#define BITS_REG_PS					(BIT_MASK_REG_PS << BIT_SHIFT_REG_PS)
#define BIT_CLEAR_REG_PS(x)				((x) & (~BITS_REG_PS))
#define BIT_GET_REG_PS(x)				(((x) >> BIT_SHIFT_REG_PS) & BIT_MASK_REG_PS)
#define BIT_SET_REG_PS(x, v)				(BIT_CLEAR_REG_PS(x) | BIT_REG_PS(v))

#define BIT_REG_FREF_EDGE				BIT(16)
#define BIT_REG_CK_BT_WIFI_EN				BIT(16)

#define BIT_SHIFT_REG_RS_SEL				13
#define BIT_MASK_REG_RS_SEL				0x7
#define BIT_REG_RS_SEL(x)				(((x) & BIT_MASK_REG_RS_SEL) << BIT_SHIFT_REG_RS_SEL)
#define BITS_REG_RS_SEL				(BIT_MASK_REG_RS_SEL << BIT_SHIFT_REG_RS_SEL)
#define BIT_CLEAR_REG_RS_SEL(x)			((x) & (~BITS_REG_RS_SEL))
#define BIT_GET_REG_RS_SEL(x)				(((x) >> BIT_SHIFT_REG_RS_SEL) & BIT_MASK_REG_RS_SEL)
#define BIT_SET_REG_RS_SEL(x, v)			(BIT_CLEAR_REG_RS_SEL(x) | BIT_REG_RS_SEL(v))

#define BIT_SHIFT_F0N_SDM				13
#define BIT_MASK_F0N_SDM				0x7
#define BIT_F0N_SDM(x)					(((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM)
#define BITS_F0N_SDM					(BIT_MASK_F0N_SDM << BIT_SHIFT_F0N_SDM)
#define BIT_CLEAR_F0N_SDM(x)				((x) & (~BITS_F0N_SDM))
#define BIT_GET_F0N_SDM(x)				(((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM)
#define BIT_SET_F0N_SDM(x, v)				(BIT_CLEAR_F0N_SDM(x) | BIT_F0N_SDM(v))

#define BIT_REG_DOGENB					BIT(12)
#define BIT_VPULSE_LDO_DAC				BIT(9)

#define BIT_SHIFT_REG_CP_BIAS				8
#define BIT_MASK_REG_CP_BIAS				0x7
#define BIT_REG_CP_BIAS(x)				(((x) & BIT_MASK_REG_CP_BIAS) << BIT_SHIFT_REG_CP_BIAS)
#define BITS_REG_CP_BIAS				(BIT_MASK_REG_CP_BIAS << BIT_SHIFT_REG_CP_BIAS)
#define BIT_CLEAR_REG_CP_BIAS(x)			((x) & (~BITS_REG_CP_BIAS))
#define BIT_GET_REG_CP_BIAS(x)				(((x) >> BIT_SHIFT_REG_CP_BIAS) & BIT_MASK_REG_CP_BIAS)
#define BIT_SET_REG_CP_BIAS(x, v)			(BIT_CLEAR_REG_CP_BIAS(x) | BIT_REG_CP_BIAS(v))

#define BIT_VPULSE_LDO_ADC				BIT(8)
#define BIT_REG_ADCK_DACK_SYN_EN			BIT(6)

#define BIT_SHIFT_LDO_OUT_DAC				6
#define BIT_MASK_LDO_OUT_DAC				0x3
#define BIT_LDO_OUT_DAC(x)				(((x) & BIT_MASK_LDO_OUT_DAC) << BIT_SHIFT_LDO_OUT_DAC)
#define BITS_LDO_OUT_DAC				(BIT_MASK_LDO_OUT_DAC << BIT_SHIFT_LDO_OUT_DAC)
#define BIT_CLEAR_LDO_OUT_DAC(x)			((x) & (~BITS_LDO_OUT_DAC))
#define BIT_GET_LDO_OUT_DAC(x)				(((x) >> BIT_SHIFT_LDO_OUT_DAC) & BIT_MASK_LDO_OUT_DAC)
#define BIT_SET_LDO_OUT_DAC(x, v)			(BIT_CLEAR_LDO_OUT_DAC(x) | BIT_LDO_OUT_DAC(v))

#define BIT_SHIFT_LDO_OUT_ADC				4
#define BIT_MASK_LDO_OUT_ADC				0x3
#define BIT_LDO_OUT_ADC(x)				(((x) & BIT_MASK_LDO_OUT_ADC) << BIT_SHIFT_LDO_OUT_ADC)
#define BITS_LDO_OUT_ADC				(BIT_MASK_LDO_OUT_ADC << BIT_SHIFT_LDO_OUT_ADC)
#define BIT_CLEAR_LDO_OUT_ADC(x)			((x) & (~BITS_LDO_OUT_ADC))
#define BIT_GET_LDO_OUT_ADC(x)				(((x) >> BIT_SHIFT_LDO_OUT_ADC) & BIT_MASK_LDO_OUT_ADC)
#define BIT_SET_LDO_OUT_ADC(x, v)			(BIT_CLEAR_LDO_OUT_ADC(x) | BIT_LDO_OUT_ADC(v))

#define BIT_LDO2PWRCUT_DAC				BIT(3)
#define BIT_LDO2PWRCUT_ADC				BIT(2)

#define BIT_SHIFT_REG_SEL_V				1
#define BIT_MASK_REG_SEL_V				0x3
#define BIT_REG_SEL_V(x)				(((x) & BIT_MASK_REG_SEL_V) << BIT_SHIFT_REG_SEL_V)
#define BITS_REG_SEL_V					(BIT_MASK_REG_SEL_V << BIT_SHIFT_REG_SEL_V)
#define BIT_CLEAR_REG_SEL_V(x)				((x) & (~BITS_REG_SEL_V))
#define BIT_GET_REG_SEL_V(x)				(((x) >> BIT_SHIFT_REG_SEL_V) & BIT_MASK_REG_SEL_V)
#define BIT_SET_REG_SEL_V(x, v)			(BIT_CLEAR_REG_SEL_V(x) | BIT_REG_SEL_V(v))

#define BIT_POW_LDO_DAC				BIT(1)
#define BIT_REG_SEL_LDO_PC				BIT(0)

#define BIT_SHIFT_F0F_SDM				0
#define BIT_MASK_F0F_SDM				0x1fff
#define BIT_F0F_SDM(x)					(((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM)
#define BITS_F0F_SDM					(BIT_MASK_F0F_SDM << BIT_SHIFT_F0F_SDM)
#define BIT_CLEAR_F0F_SDM(x)				((x) & (~BITS_F0F_SDM))
#define BIT_GET_F0F_SDM(x)				(((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM)
#define BIT_SET_F0F_SDM(x, v)				(BIT_CLEAR_F0F_SDM(x) | BIT_F0F_SDM(v))

#define BIT_POW_LDO_ADC				BIT(0)

/* 2 REG_ANAPARSW_MAC_7			(Offset 0x1034) */

#define BIT_NEED_CHECK_CKO_IQK				BIT(31)
#define BIT_NEED_CHECK_AFE				BIT(30)

/* 2 REG_ANAPARSW_MAC_8			(Offset 0x1038) */

#define BIT_REG_CK_MON_SEL				BIT(5)
#define BIT_REG_CKMON_EN				BIT(4)
#define BIT_REG_CK320MB_EN				BIT(3)
#define BIT_REG_CK320M_EN				BIT(2)
#define BIT_REG_CK_5M_EN				BIT(1)
#define BIT_REG_TESTEN					BIT(0)

/* 2 REG_WL_ANAPAR_XTAL_ON_0			(Offset 0x103C) */

#define BIT_XTAL_SC_LPS_L				BIT(31)

#define BIT_SHIFT_XTAL_SC_INIT				24
#define BIT_MASK_XTAL_SC_INIT				0x7f
#define BIT_XTAL_SC_INIT(x)				(((x) & BIT_MASK_XTAL_SC_INIT) << BIT_SHIFT_XTAL_SC_INIT)
#define BITS_XTAL_SC_INIT				(BIT_MASK_XTAL_SC_INIT << BIT_SHIFT_XTAL_SC_INIT)
#define BIT_CLEAR_XTAL_SC_INIT(x)			((x) & (~BITS_XTAL_SC_INIT))
#define BIT_GET_XTAL_SC_INIT(x)			(((x) >> BIT_SHIFT_XTAL_SC_INIT) & BIT_MASK_XTAL_SC_INIT)
#define BIT_SET_XTAL_SC_INIT(x, v)			(BIT_CLEAR_XTAL_SC_INIT(x) | BIT_XTAL_SC_INIT(v))

#define BIT_SHIFT_XTAL_SC_XO				17
#define BIT_MASK_XTAL_SC_XO				0x7f
#define BIT_XTAL_SC_XO(x)				(((x) & BIT_MASK_XTAL_SC_XO) << BIT_SHIFT_XTAL_SC_XO)
#define BITS_XTAL_SC_XO				(BIT_MASK_XTAL_SC_XO << BIT_SHIFT_XTAL_SC_XO)
#define BIT_CLEAR_XTAL_SC_XO(x)			((x) & (~BITS_XTAL_SC_XO))
#define BIT_GET_XTAL_SC_XO(x)				(((x) >> BIT_SHIFT_XTAL_SC_XO) & BIT_MASK_XTAL_SC_XO)
#define BIT_SET_XTAL_SC_XO(x, v)			(BIT_CLEAR_XTAL_SC_XO(x) | BIT_XTAL_SC_XO(v))

#define BIT_SHIFT_XTAL_SC_XI				10
#define BIT_MASK_XTAL_SC_XI				0x7f
#define BIT_XTAL_SC_XI(x)				(((x) & BIT_MASK_XTAL_SC_XI) << BIT_SHIFT_XTAL_SC_XI)
#define BITS_XTAL_SC_XI				(BIT_MASK_XTAL_SC_XI << BIT_SHIFT_XTAL_SC_XI)
#define BIT_CLEAR_XTAL_SC_XI(x)			((x) & (~BITS_XTAL_SC_XI))
#define BIT_GET_XTAL_SC_XI(x)				(((x) >> BIT_SHIFT_XTAL_SC_XI) & BIT_MASK_XTAL_SC_XI)
#define BIT_SET_XTAL_SC_XI(x, v)			(BIT_CLEAR_XTAL_SC_XI(x) | BIT_XTAL_SC_XI(v))

#define BIT_SHIFT_XTAL_GMN				5
#define BIT_MASK_XTAL_GMN				0x1f
#define BIT_XTAL_GMN(x)				(((x) & BIT_MASK_XTAL_GMN) << BIT_SHIFT_XTAL_GMN)
#define BITS_XTAL_GMN					(BIT_MASK_XTAL_GMN << BIT_SHIFT_XTAL_GMN)
#define BIT_CLEAR_XTAL_GMN(x)				((x) & (~BITS_XTAL_GMN))
#define BIT_GET_XTAL_GMN(x)				(((x) >> BIT_SHIFT_XTAL_GMN) & BIT_MASK_XTAL_GMN)
#define BIT_SET_XTAL_GMN(x, v)				(BIT_CLEAR_XTAL_GMN(x) | BIT_XTAL_GMN(v))

#define BIT_SHIFT_XTAL_GMP				0
#define BIT_MASK_XTAL_GMP				0x1f
#define BIT_XTAL_GMP(x)				(((x) & BIT_MASK_XTAL_GMP) << BIT_SHIFT_XTAL_GMP)
#define BITS_XTAL_GMP					(BIT_MASK_XTAL_GMP << BIT_SHIFT_XTAL_GMP)
#define BIT_CLEAR_XTAL_GMP(x)				((x) & (~BITS_XTAL_GMP))
#define BIT_GET_XTAL_GMP(x)				(((x) >> BIT_SHIFT_XTAL_GMP) & BIT_MASK_XTAL_GMP)
#define BIT_SET_XTAL_GMP(x, v)				(BIT_CLEAR_XTAL_GMP(x) | BIT_XTAL_GMP(v))

/* 2 REG_WL_ANAPAR_XTAL_ON_1			(Offset 0x1040) */

#define BIT_AAC_MODE_0					BIT(31)

#define BIT_SHIFT_XTAL_CFIX				29
#define BIT_MASK_XTAL_CFIX				0x3
#define BIT_XTAL_CFIX(x)				(((x) & BIT_MASK_XTAL_CFIX) << BIT_SHIFT_XTAL_CFIX)
#define BITS_XTAL_CFIX					(BIT_MASK_XTAL_CFIX << BIT_SHIFT_XTAL_CFIX)
#define BIT_CLEAR_XTAL_CFIX(x)				((x) & (~BITS_XTAL_CFIX))
#define BIT_GET_XTAL_CFIX(x)				(((x) >> BIT_SHIFT_XTAL_CFIX) & BIT_MASK_XTAL_CFIX)
#define BIT_SET_XTAL_CFIX(x, v)			(BIT_CLEAR_XTAL_CFIX(x) | BIT_XTAL_CFIX(v))

#define BIT_SHIFT_XTAL_AAC_OPCUR			27
#define BIT_MASK_XTAL_AAC_OPCUR			0x3
#define BIT_XTAL_AAC_OPCUR(x)				(((x) & BIT_MASK_XTAL_AAC_OPCUR) << BIT_SHIFT_XTAL_AAC_OPCUR)
#define BITS_XTAL_AAC_OPCUR				(BIT_MASK_XTAL_AAC_OPCUR << BIT_SHIFT_XTAL_AAC_OPCUR)
#define BIT_CLEAR_XTAL_AAC_OPCUR(x)			((x) & (~BITS_XTAL_AAC_OPCUR))
#define BIT_GET_XTAL_AAC_OPCUR(x)			(((x) >> BIT_SHIFT_XTAL_AAC_OPCUR) & BIT_MASK_XTAL_AAC_OPCUR)
#define BIT_SET_XTAL_AAC_OPCUR(x, v)			(BIT_CLEAR_XTAL_AAC_OPCUR(x) | BIT_XTAL_AAC_OPCUR(v))

#define BIT_SHIFT_XTAL_VREF_SEL			22
#define BIT_MASK_XTAL_VREF_SEL				0x1f
#define BIT_XTAL_VREF_SEL(x)				(((x) & BIT_MASK_XTAL_VREF_SEL) << BIT_SHIFT_XTAL_VREF_SEL)
#define BITS_XTAL_VREF_SEL				(BIT_MASK_XTAL_VREF_SEL << BIT_SHIFT_XTAL_VREF_SEL)
#define BIT_CLEAR_XTAL_VREF_SEL(x)			((x) & (~BITS_XTAL_VREF_SEL))
#define BIT_GET_XTAL_VREF_SEL(x)			(((x) >> BIT_SHIFT_XTAL_VREF_SEL) & BIT_MASK_XTAL_VREF_SEL)
#define BIT_SET_XTAL_VREF_SEL(x, v)			(BIT_CLEAR_XTAL_VREF_SEL(x) | BIT_XTAL_VREF_SEL(v))

#define BIT_XTAL_LPS_DIVISOR				BIT(21)
#define BIT_XTAL_CKDIGI_SEL				BIT(20)
#define BIT_EN_XTAL_LPS_CLK				BIT(19)
#define BIT_EN_XTAL_SCHMITT				BIT(18)

#define BIT_SHIFT_XTAL_LDO_VREF			15
#define BIT_MASK_XTAL_LDO_VREF				0x7
#define BIT_XTAL_LDO_VREF(x)				(((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF)
#define BITS_XTAL_LDO_VREF				(BIT_MASK_XTAL_LDO_VREF << BIT_SHIFT_XTAL_LDO_VREF)
#define BIT_CLEAR_XTAL_LDO_VREF(x)			((x) & (~BITS_XTAL_LDO_VREF))
#define BIT_GET_XTAL_LDO_VREF(x)			(((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF)
#define BIT_SET_XTAL_LDO_VREF(x, v)			(BIT_CLEAR_XTAL_LDO_VREF(x) | BIT_XTAL_LDO_VREF(v))

#define BIT_SHIFT_XTAL_SEL_TOK				12
#define BIT_MASK_XTAL_SEL_TOK				0x7
#define BIT_XTAL_SEL_TOK(x)				(((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK)
#define BITS_XTAL_SEL_TOK				(BIT_MASK_XTAL_SEL_TOK << BIT_SHIFT_XTAL_SEL_TOK)
#define BIT_CLEAR_XTAL_SEL_TOK(x)			((x) & (~BITS_XTAL_SEL_TOK))
#define BIT_GET_XTAL_SEL_TOK(x)			(((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK)
#define BIT_SET_XTAL_SEL_TOK(x, v)			(BIT_CLEAR_XTAL_SEL_TOK(x) | BIT_XTAL_SEL_TOK(v))

#define BIT_EN_XTAL_DRV_LPS				BIT(11)
#define BIT_EN_XTAL_DRV_DIGI				BIT(10)
#define BIT_EN_XTAL_DRV_USB				BIT(9)
#define BIT_EN_XTAL_DRV_AFE				BIT(8)
#define BIT_EN_XTAL_DRV_RF2				BIT(7)
#define BIT_EN_XTAL_DRV_RF1				BIT(6)

#define BIT_SHIFT_XTAL_SC_LPS_H			0
#define BIT_MASK_XTAL_SC_LPS_H				0x3f
#define BIT_XTAL_SC_LPS_H(x)				(((x) & BIT_MASK_XTAL_SC_LPS_H) << BIT_SHIFT_XTAL_SC_LPS_H)
#define BITS_XTAL_SC_LPS_H				(BIT_MASK_XTAL_SC_LPS_H << BIT_SHIFT_XTAL_SC_LPS_H)
#define BIT_CLEAR_XTAL_SC_LPS_H(x)			((x) & (~BITS_XTAL_SC_LPS_H))
#define BIT_GET_XTAL_SC_LPS_H(x)			(((x) >> BIT_SHIFT_XTAL_SC_LPS_H) & BIT_MASK_XTAL_SC_LPS_H)
#define BIT_SET_XTAL_SC_LPS_H(x, v)			(BIT_CLEAR_XTAL_SC_LPS_H(x) | BIT_XTAL_SC_LPS_H(v))

/* 2 REG_WL_ANAPAR_XTAL_ON_2			(Offset 0x1044) */

#define BIT_EN_XTAL_DRV_IQK_BCN			BIT(1)
#define BIT_AAC_MODE_1					BIT(0)

/* 2 REG_ANAPAR_LDO_0			(Offset 0x1048) */

#define BIT_SHIFT_REG_RES_BT_PON_L			30
#define BIT_MASK_REG_RES_BT_PON_L			0x3
#define BIT_REG_RES_BT_PON_L(x)			(((x) & BIT_MASK_REG_RES_BT_PON_L) << BIT_SHIFT_REG_RES_BT_PON_L)
#define BITS_REG_RES_BT_PON_L				(BIT_MASK_REG_RES_BT_PON_L << BIT_SHIFT_REG_RES_BT_PON_L)
#define BIT_CLEAR_REG_RES_BT_PON_L(x)			((x) & (~BITS_REG_RES_BT_PON_L))
#define BIT_GET_REG_RES_BT_PON_L(x)			(((x) >> BIT_SHIFT_REG_RES_BT_PON_L) & BIT_MASK_REG_RES_BT_PON_L)
#define BIT_SET_REG_RES_BT_PON_L(x, v)			(BIT_CLEAR_REG_RES_BT_PON_L(x) | BIT_REG_RES_BT_PON_L(v))

#define BIT_SHIFT_REG_BIAS_BT_PON_L			28
#define BIT_MASK_REG_BIAS_BT_PON_L			0x3
#define BIT_REG_BIAS_BT_PON_L(x)			(((x) & BIT_MASK_REG_BIAS_BT_PON_L) << BIT_SHIFT_REG_BIAS_BT_PON_L)
#define BITS_REG_BIAS_BT_PON_L				(BIT_MASK_REG_BIAS_BT_PON_L << BIT_SHIFT_REG_BIAS_BT_PON_L)
#define BIT_CLEAR_REG_BIAS_BT_PON_L(x)			((x) & (~BITS_REG_BIAS_BT_PON_L))
#define BIT_GET_REG_BIAS_BT_PON_L(x)			(((x) >> BIT_SHIFT_REG_BIAS_BT_PON_L) & BIT_MASK_REG_BIAS_BT_PON_L)
#define BIT_SET_REG_BIAS_BT_PON_L(x, v)		(BIT_CLEAR_REG_BIAS_BT_PON_L(x) | BIT_REG_BIAS_BT_PON_L(v))

#define BIT_SHIFT_LDOD_V12ADJ_BT_PON_L			24
#define BIT_MASK_LDOD_V12ADJ_BT_PON_L			0xf
#define BIT_LDOD_V12ADJ_BT_PON_L(x)			(((x) & BIT_MASK_LDOD_V12ADJ_BT_PON_L) << BIT_SHIFT_LDOD_V12ADJ_BT_PON_L)
#define BITS_LDOD_V12ADJ_BT_PON_L			(BIT_MASK_LDOD_V12ADJ_BT_PON_L << BIT_SHIFT_LDOD_V12ADJ_BT_PON_L)
#define BIT_CLEAR_LDOD_V12ADJ_BT_PON_L(x)		((x) & (~BITS_LDOD_V12ADJ_BT_PON_L))
#define BIT_GET_LDOD_V12ADJ_BT_PON_L(x)		(((x) >> BIT_SHIFT_LDOD_V12ADJ_BT_PON_L) & BIT_MASK_LDOD_V12ADJ_BT_PON_L)
#define BIT_SET_LDOD_V12ADJ_BT_PON_L(x, v)		(BIT_CLEAR_LDOD_V12ADJ_BT_PON_L(x) | BIT_LDOD_V12ADJ_BT_PON_L(v))

#define BIT_SHIFT_REG_CC_BT_PON_L			22
#define BIT_MASK_REG_CC_BT_PON_L			0x3
#define BIT_REG_CC_BT_PON_L(x)				(((x) & BIT_MASK_REG_CC_BT_PON_L) << BIT_SHIFT_REG_CC_BT_PON_L)
#define BITS_REG_CC_BT_PON_L				(BIT_MASK_REG_CC_BT_PON_L << BIT_SHIFT_REG_CC_BT_PON_L)
#define BIT_CLEAR_REG_CC_BT_PON_L(x)			((x) & (~BITS_REG_CC_BT_PON_L))
#define BIT_GET_REG_CC_BT_PON_L(x)			(((x) >> BIT_SHIFT_REG_CC_BT_PON_L) & BIT_MASK_REG_CC_BT_PON_L)
#define BIT_SET_REG_CC_BT_PON_L(x, v)			(BIT_CLEAR_REG_CC_BT_PON_L(x) | BIT_REG_CC_BT_PON_L(v))

#define BIT_REG_STANDBY_BT_PON_L			BIT(21)
#define BIT_POW_LDO_BT_PON				BIT(20)

#define BIT_SHIFT_REG_RES_BT_L				18
#define BIT_MASK_REG_RES_BT_L				0x3
#define BIT_REG_RES_BT_L(x)				(((x) & BIT_MASK_REG_RES_BT_L) << BIT_SHIFT_REG_RES_BT_L)
#define BITS_REG_RES_BT_L				(BIT_MASK_REG_RES_BT_L << BIT_SHIFT_REG_RES_BT_L)
#define BIT_CLEAR_REG_RES_BT_L(x)			((x) & (~BITS_REG_RES_BT_L))
#define BIT_GET_REG_RES_BT_L(x)			(((x) >> BIT_SHIFT_REG_RES_BT_L) & BIT_MASK_REG_RES_BT_L)
#define BIT_SET_REG_RES_BT_L(x, v)			(BIT_CLEAR_REG_RES_BT_L(x) | BIT_REG_RES_BT_L(v))

#define BIT_SHIFT_REG_BIAS_BT_L			16
#define BIT_MASK_REG_BIAS_BT_L				0x3
#define BIT_REG_BIAS_BT_L(x)				(((x) & BIT_MASK_REG_BIAS_BT_L) << BIT_SHIFT_REG_BIAS_BT_L)
#define BITS_REG_BIAS_BT_L				(BIT_MASK_REG_BIAS_BT_L << BIT_SHIFT_REG_BIAS_BT_L)
#define BIT_CLEAR_REG_BIAS_BT_L(x)			((x) & (~BITS_REG_BIAS_BT_L))
#define BIT_GET_REG_BIAS_BT_L(x)			(((x) >> BIT_SHIFT_REG_BIAS_BT_L) & BIT_MASK_REG_BIAS_BT_L)
#define BIT_SET_REG_BIAS_BT_L(x, v)			(BIT_CLEAR_REG_BIAS_BT_L(x) | BIT_REG_BIAS_BT_L(v))

#define BIT_SHIFT_LDOD_V12ADJ_BT_L			12
#define BIT_MASK_LDOD_V12ADJ_BT_L			0xf
#define BIT_LDOD_V12ADJ_BT_L(x)			(((x) & BIT_MASK_LDOD_V12ADJ_BT_L) << BIT_SHIFT_LDOD_V12ADJ_BT_L)
#define BITS_LDOD_V12ADJ_BT_L				(BIT_MASK_LDOD_V12ADJ_BT_L << BIT_SHIFT_LDOD_V12ADJ_BT_L)
#define BIT_CLEAR_LDOD_V12ADJ_BT_L(x)			((x) & (~BITS_LDOD_V12ADJ_BT_L))
#define BIT_GET_LDOD_V12ADJ_BT_L(x)			(((x) >> BIT_SHIFT_LDOD_V12ADJ_BT_L) & BIT_MASK_LDOD_V12ADJ_BT_L)
#define BIT_SET_LDOD_V12ADJ_BT_L(x, v)			(BIT_CLEAR_LDOD_V12ADJ_BT_L(x) | BIT_LDOD_V12ADJ_BT_L(v))

#define BIT_SHIFT_REG_CC_BT_L				10
#define BIT_MASK_REG_CC_BT_L				0x3
#define BIT_REG_CC_BT_L(x)				(((x) & BIT_MASK_REG_CC_BT_L) << BIT_SHIFT_REG_CC_BT_L)
#define BITS_REG_CC_BT_L				(BIT_MASK_REG_CC_BT_L << BIT_SHIFT_REG_CC_BT_L)
#define BIT_CLEAR_REG_CC_BT_L(x)			((x) & (~BITS_REG_CC_BT_L))
#define BIT_GET_REG_CC_BT_L(x)				(((x) >> BIT_SHIFT_REG_CC_BT_L) & BIT_MASK_REG_CC_BT_L)
#define BIT_SET_REG_CC_BT_L(x, v)			(BIT_CLEAR_REG_CC_BT_L(x) | BIT_REG_CC_BT_L(v))

#define BIT_REG_STANDBY_BT_L				BIT(9)
#define BIT_POW_LDO_BT					BIT(8)

#define BIT_SHIFT_REG_RES_WL_PON_L			6
#define BIT_MASK_REG_RES_WL_PON_L			0x3
#define BIT_REG_RES_WL_PON_L(x)			(((x) & BIT_MASK_REG_RES_WL_PON_L) << BIT_SHIFT_REG_RES_WL_PON_L)
#define BITS_REG_RES_WL_PON_L				(BIT_MASK_REG_RES_WL_PON_L << BIT_SHIFT_REG_RES_WL_PON_L)
#define BIT_CLEAR_REG_RES_WL_PON_L(x)			((x) & (~BITS_REG_RES_WL_PON_L))
#define BIT_GET_REG_RES_WL_PON_L(x)			(((x) >> BIT_SHIFT_REG_RES_WL_PON_L) & BIT_MASK_REG_RES_WL_PON_L)
#define BIT_SET_REG_RES_WL_PON_L(x, v)			(BIT_CLEAR_REG_RES_WL_PON_L(x) | BIT_REG_RES_WL_PON_L(v))

#define BIT_SHIFT_REG_BIAS_WL_PON_L			4
#define BIT_MASK_REG_BIAS_WL_PON_L			0x3
#define BIT_REG_BIAS_WL_PON_L(x)			(((x) & BIT_MASK_REG_BIAS_WL_PON_L) << BIT_SHIFT_REG_BIAS_WL_PON_L)
#define BITS_REG_BIAS_WL_PON_L				(BIT_MASK_REG_BIAS_WL_PON_L << BIT_SHIFT_REG_BIAS_WL_PON_L)
#define BIT_CLEAR_REG_BIAS_WL_PON_L(x)			((x) & (~BITS_REG_BIAS_WL_PON_L))
#define BIT_GET_REG_BIAS_WL_PON_L(x)			(((x) >> BIT_SHIFT_REG_BIAS_WL_PON_L) & BIT_MASK_REG_BIAS_WL_PON_L)
#define BIT_SET_REG_BIAS_WL_PON_L(x, v)		(BIT_CLEAR_REG_BIAS_WL_PON_L(x) | BIT_REG_BIAS_WL_PON_L(v))

#define BIT_SHIFT_LDOD_V12ADJ_WL_PON_L			0
#define BIT_MASK_LDOD_V12ADJ_WL_PON_L			0xf
#define BIT_LDOD_V12ADJ_WL_PON_L(x)			(((x) & BIT_MASK_LDOD_V12ADJ_WL_PON_L) << BIT_SHIFT_LDOD_V12ADJ_WL_PON_L)
#define BITS_LDOD_V12ADJ_WL_PON_L			(BIT_MASK_LDOD_V12ADJ_WL_PON_L << BIT_SHIFT_LDOD_V12ADJ_WL_PON_L)
#define BIT_CLEAR_LDOD_V12ADJ_WL_PON_L(x)		((x) & (~BITS_LDOD_V12ADJ_WL_PON_L))
#define BIT_GET_LDOD_V12ADJ_WL_PON_L(x)		(((x) >> BIT_SHIFT_LDOD_V12ADJ_WL_PON_L) & BIT_MASK_LDOD_V12ADJ_WL_PON_L)
#define BIT_SET_LDOD_V12ADJ_WL_PON_L(x, v)		(BIT_CLEAR_LDOD_V12ADJ_WL_PON_L(x) | BIT_LDOD_V12ADJ_WL_PON_L(v))

/* 2 REG_ANAPAR_LDO_1			(Offset 0x104C) */

#define BIT_SW_GPIO_RIGHT_SHD				BIT(18)
#define BIT_SW_GPIO_LEFT_SHD				BIT(17)
#define BIT_SW_GPIO_PAD_IE_V18				BIT(16)
#define BIT_EN_PC					BIT(12)

#define BIT_SHIFT_REG_RES_PHY_DIG_L			10
#define BIT_MASK_REG_RES_PHY_DIG_L			0x3
#define BIT_REG_RES_PHY_DIG_L(x)			(((x) & BIT_MASK_REG_RES_PHY_DIG_L) << BIT_SHIFT_REG_RES_PHY_DIG_L)
#define BITS_REG_RES_PHY_DIG_L				(BIT_MASK_REG_RES_PHY_DIG_L << BIT_SHIFT_REG_RES_PHY_DIG_L)
#define BIT_CLEAR_REG_RES_PHY_DIG_L(x)			((x) & (~BITS_REG_RES_PHY_DIG_L))
#define BIT_GET_REG_RES_PHY_DIG_L(x)			(((x) >> BIT_SHIFT_REG_RES_PHY_DIG_L) & BIT_MASK_REG_RES_PHY_DIG_L)
#define BIT_SET_REG_RES_PHY_DIG_L(x, v)		(BIT_CLEAR_REG_RES_PHY_DIG_L(x) | BIT_REG_RES_PHY_DIG_L(v))

#define BIT_SHIFT_REG_BIAS_PHY_DIG_L			8
#define BIT_MASK_REG_BIAS_PHY_DIG_L			0x3
#define BIT_REG_BIAS_PHY_DIG_L(x)			(((x) & BIT_MASK_REG_BIAS_PHY_DIG_L) << BIT_SHIFT_REG_BIAS_PHY_DIG_L)
#define BITS_REG_BIAS_PHY_DIG_L			(BIT_MASK_REG_BIAS_PHY_DIG_L << BIT_SHIFT_REG_BIAS_PHY_DIG_L)
#define BIT_CLEAR_REG_BIAS_PHY_DIG_L(x)		((x) & (~BITS_REG_BIAS_PHY_DIG_L))
#define BIT_GET_REG_BIAS_PHY_DIG_L(x)			(((x) >> BIT_SHIFT_REG_BIAS_PHY_DIG_L) & BIT_MASK_REG_BIAS_PHY_DIG_L)
#define BIT_SET_REG_BIAS_PHY_DIG_L(x, v)		(BIT_CLEAR_REG_BIAS_PHY_DIG_L(x) | BIT_REG_BIAS_PHY_DIG_L(v))

#define BIT_SHIFT_LDOD_V12ADJ_PHY_DIG_L		4
#define BIT_MASK_LDOD_V12ADJ_PHY_DIG_L			0xf
#define BIT_LDOD_V12ADJ_PHY_DIG_L(x)			(((x) & BIT_MASK_LDOD_V12ADJ_PHY_DIG_L) << BIT_SHIFT_LDOD_V12ADJ_PHY_DIG_L)
#define BITS_LDOD_V12ADJ_PHY_DIG_L			(BIT_MASK_LDOD_V12ADJ_PHY_DIG_L << BIT_SHIFT_LDOD_V12ADJ_PHY_DIG_L)
#define BIT_CLEAR_LDOD_V12ADJ_PHY_DIG_L(x)		((x) & (~BITS_LDOD_V12ADJ_PHY_DIG_L))
#define BIT_GET_LDOD_V12ADJ_PHY_DIG_L(x)		(((x) >> BIT_SHIFT_LDOD_V12ADJ_PHY_DIG_L) & BIT_MASK_LDOD_V12ADJ_PHY_DIG_L)
#define BIT_SET_LDOD_V12ADJ_PHY_DIG_L(x, v)		(BIT_CLEAR_LDOD_V12ADJ_PHY_DIG_L(x) | BIT_LDOD_V12ADJ_PHY_DIG_L(v))

#define BIT_SHIFT_REG_CC_PHY_DIG_L			2
#define BIT_MASK_REG_CC_PHY_DIG_L			0x3
#define BIT_REG_CC_PHY_DIG_L(x)			(((x) & BIT_MASK_REG_CC_PHY_DIG_L) << BIT_SHIFT_REG_CC_PHY_DIG_L)
#define BITS_REG_CC_PHY_DIG_L				(BIT_MASK_REG_CC_PHY_DIG_L << BIT_SHIFT_REG_CC_PHY_DIG_L)
#define BIT_CLEAR_REG_CC_PHY_DIG_L(x)			((x) & (~BITS_REG_CC_PHY_DIG_L))
#define BIT_GET_REG_CC_PHY_DIG_L(x)			(((x) >> BIT_SHIFT_REG_CC_PHY_DIG_L) & BIT_MASK_REG_CC_PHY_DIG_L)
#define BIT_SET_REG_CC_PHY_DIG_L(x, v)			(BIT_CLEAR_REG_CC_PHY_DIG_L(x) | BIT_REG_CC_PHY_DIG_L(v))

#define BIT_REG_STANDBY_PHY_DIG_L			BIT(1)
#define BIT_POW_LDO_PHY_DIG				BIT(0)

#define BIT_SHIFT_SW_GPIO_A_E2				0
#define BIT_MASK_SW_GPIO_A_E2				0xffff
#define BIT_SW_GPIO_A_E2(x)				(((x) & BIT_MASK_SW_GPIO_A_E2) << BIT_SHIFT_SW_GPIO_A_E2)
#define BITS_SW_GPIO_A_E2				(BIT_MASK_SW_GPIO_A_E2 << BIT_SHIFT_SW_GPIO_A_E2)
#define BIT_CLEAR_SW_GPIO_A_E2(x)			((x) & (~BITS_SW_GPIO_A_E2))
#define BIT_GET_SW_GPIO_A_E2(x)			(((x) >> BIT_SHIFT_SW_GPIO_A_E2) & BIT_MASK_SW_GPIO_A_E2)
#define BIT_SET_SW_GPIO_A_E2(x, v)			(BIT_CLEAR_SW_GPIO_A_E2(x) | BIT_SW_GPIO_A_E2(v))

#define BIT_SHIFT_SW_SMT				0
#define BIT_MASK_SW_SMT				0xffff
#define BIT_SW_SMT(x)					(((x) & BIT_MASK_SW_SMT) << BIT_SHIFT_SW_SMT)
#define BITS_SW_SMT					(BIT_MASK_SW_SMT << BIT_SHIFT_SW_SMT)
#define BIT_CLEAR_SW_SMT(x)				((x) & (~BITS_SW_SMT))
#define BIT_GET_SW_SMT(x)				(((x) >> BIT_SHIFT_SW_SMT) & BIT_MASK_SW_SMT)
#define BIT_SET_SW_SMT(x, v)				(BIT_CLEAR_SW_SMT(x) | BIT_SW_SMT(v))

/* 2 REG_ANAPAR_MODE_DEC_ON			(Offset 0x1064) */

#define BIT_SHIFT_XTAL_LDO_LPS				21
#define BIT_MASK_XTAL_LDO_LPS				0x7
#define BIT_XTAL_LDO_LPS(x)				(((x) & BIT_MASK_XTAL_LDO_LPS) << BIT_SHIFT_XTAL_LDO_LPS)
#define BITS_XTAL_LDO_LPS				(BIT_MASK_XTAL_LDO_LPS << BIT_SHIFT_XTAL_LDO_LPS)
#define BIT_CLEAR_XTAL_LDO_LPS(x)			((x) & (~BITS_XTAL_LDO_LPS))
#define BIT_GET_XTAL_LDO_LPS(x)			(((x) >> BIT_SHIFT_XTAL_LDO_LPS) & BIT_MASK_XTAL_LDO_LPS)
#define BIT_SET_XTAL_LDO_LPS(x, v)			(BIT_CLEAR_XTAL_LDO_LPS(x) | BIT_XTAL_LDO_LPS(v))

#define BIT_SHIFT_XTAL_WAIT_CYC			15
#define BIT_MASK_XTAL_WAIT_CYC				0x3f
#define BIT_XTAL_WAIT_CYC(x)				(((x) & BIT_MASK_XTAL_WAIT_CYC) << BIT_SHIFT_XTAL_WAIT_CYC)
#define BITS_XTAL_WAIT_CYC				(BIT_MASK_XTAL_WAIT_CYC << BIT_SHIFT_XTAL_WAIT_CYC)
#define BIT_CLEAR_XTAL_WAIT_CYC(x)			((x) & (~BITS_XTAL_WAIT_CYC))
#define BIT_GET_XTAL_WAIT_CYC(x)			(((x) >> BIT_SHIFT_XTAL_WAIT_CYC) & BIT_MASK_XTAL_WAIT_CYC)
#define BIT_SET_XTAL_WAIT_CYC(x, v)			(BIT_CLEAR_XTAL_WAIT_CYC(x) | BIT_XTAL_WAIT_CYC(v))

#define BIT_SHIFT_XTAL_LDO_OK				12
#define BIT_MASK_XTAL_LDO_OK				0x7
#define BIT_XTAL_LDO_OK(x)				(((x) & BIT_MASK_XTAL_LDO_OK) << BIT_SHIFT_XTAL_LDO_OK)
#define BITS_XTAL_LDO_OK				(BIT_MASK_XTAL_LDO_OK << BIT_SHIFT_XTAL_LDO_OK)
#define BIT_CLEAR_XTAL_LDO_OK(x)			((x) & (~BITS_XTAL_LDO_OK))
#define BIT_GET_XTAL_LDO_OK(x)				(((x) >> BIT_SHIFT_XTAL_LDO_OK) & BIT_MASK_XTAL_LDO_OK)
#define BIT_SET_XTAL_LDO_OK(x, v)			(BIT_CLEAR_XTAL_LDO_OK(x) | BIT_XTAL_LDO_OK(v))

#define BIT_XTAL_MD_LPOW				BIT(11)

#define BIT_SHIFT_XTAL_OV_RATIO			9
#define BIT_MASK_XTAL_OV_RATIO				0x3
#define BIT_XTAL_OV_RATIO(x)				(((x) & BIT_MASK_XTAL_OV_RATIO) << BIT_SHIFT_XTAL_OV_RATIO)
#define BITS_XTAL_OV_RATIO				(BIT_MASK_XTAL_OV_RATIO << BIT_SHIFT_XTAL_OV_RATIO)
#define BIT_CLEAR_XTAL_OV_RATIO(x)			((x) & (~BITS_XTAL_OV_RATIO))
#define BIT_GET_XTAL_OV_RATIO(x)			(((x) >> BIT_SHIFT_XTAL_OV_RATIO) & BIT_MASK_XTAL_OV_RATIO)
#define BIT_SET_XTAL_OV_RATIO(x, v)			(BIT_CLEAR_XTAL_OV_RATIO(x) | BIT_XTAL_OV_RATIO(v))

#define BIT_SHIFT_XTAL_OV_UNIT				6
#define BIT_MASK_XTAL_OV_UNIT				0x7
#define BIT_XTAL_OV_UNIT(x)				(((x) & BIT_MASK_XTAL_OV_UNIT) << BIT_SHIFT_XTAL_OV_UNIT)
#define BITS_XTAL_OV_UNIT				(BIT_MASK_XTAL_OV_UNIT << BIT_SHIFT_XTAL_OV_UNIT)
#define BIT_CLEAR_XTAL_OV_UNIT(x)			((x) & (~BITS_XTAL_OV_UNIT))
#define BIT_GET_XTAL_OV_UNIT(x)			(((x) >> BIT_SHIFT_XTAL_OV_UNIT) & BIT_MASK_XTAL_OV_UNIT)
#define BIT_SET_XTAL_OV_UNIT(x, v)			(BIT_CLEAR_XTAL_OV_UNIT(x) | BIT_XTAL_OV_UNIT(v))

#define BIT_SHIFT_XTAL_MODE_MANUAL			4
#define BIT_MASK_XTAL_MODE_MANUAL			0x3
#define BIT_XTAL_MODE_MANUAL(x)			(((x) & BIT_MASK_XTAL_MODE_MANUAL) << BIT_SHIFT_XTAL_MODE_MANUAL)
#define BITS_XTAL_MODE_MANUAL				(BIT_MASK_XTAL_MODE_MANUAL << BIT_SHIFT_XTAL_MODE_MANUAL)
#define BIT_CLEAR_XTAL_MODE_MANUAL(x)			((x) & (~BITS_XTAL_MODE_MANUAL))
#define BIT_GET_XTAL_MODE_MANUAL(x)			(((x) >> BIT_SHIFT_XTAL_MODE_MANUAL) & BIT_MASK_XTAL_MODE_MANUAL)
#define BIT_SET_XTAL_MODE_MANUAL(x, v)			(BIT_CLEAR_XTAL_MODE_MANUAL(x) | BIT_XTAL_MODE_MANUAL(v))

#define BIT_XTAL_MANU_SEL				BIT(3)
#define BIT_POW_XTAL_LPS				BIT(2)
#define BIT_XTAL_MODE					BIT(1)
#define BIT_RESET_N					BIT(0)

/* 2 REG_RO_XTAL_MODE_DEC			(Offset 0x1068) */

#define BIT_SHIFT_RO_XTAL_MODE_DEC			0
#define BIT_MASK_RO_XTAL_MODE_DEC			0xffffffffL
#define BIT_RO_XTAL_MODE_DEC(x)			(((x) & BIT_MASK_RO_XTAL_MODE_DEC) << BIT_SHIFT_RO_XTAL_MODE_DEC)
#define BITS_RO_XTAL_MODE_DEC				(BIT_MASK_RO_XTAL_MODE_DEC << BIT_SHIFT_RO_XTAL_MODE_DEC)
#define BIT_CLEAR_RO_XTAL_MODE_DEC(x)			((x) & (~BITS_RO_XTAL_MODE_DEC))
#define BIT_GET_RO_XTAL_MODE_DEC(x)			(((x) >> BIT_SHIFT_RO_XTAL_MODE_DEC) & BIT_MASK_RO_XTAL_MODE_DEC)
#define BIT_SET_RO_XTAL_MODE_DEC(x, v)			(BIT_CLEAR_RO_XTAL_MODE_DEC(x) | BIT_RO_XTAL_MODE_DEC(v))

/* 2 REG_WL_ANAPAR_XTAL_OFF0			(Offset 0x106C) */

#define BIT_XTAL_PDCK_MANU				BIT(31)
#define BIT_XTAL_PDCK_OK_MANU				BIT(30)
#define BIT_EN_XTAL_PDCK_VREF				BIT(29)
#define BIT_XTAL_SEL_PWR				BIT(28)
#define BIT_XTAL_PK_SEL_OFFSET				BIT(27)

#define BIT_SHIFT_XTAL_MANU_PK_SEL			25
#define BIT_MASK_XTAL_MANU_PK_SEL			0x3
#define BIT_XTAL_MANU_PK_SEL(x)			(((x) & BIT_MASK_XTAL_MANU_PK_SEL) << BIT_SHIFT_XTAL_MANU_PK_SEL)
#define BITS_XTAL_MANU_PK_SEL				(BIT_MASK_XTAL_MANU_PK_SEL << BIT_SHIFT_XTAL_MANU_PK_SEL)
#define BIT_CLEAR_XTAL_MANU_PK_SEL(x)			((x) & (~BITS_XTAL_MANU_PK_SEL))
#define BIT_GET_XTAL_MANU_PK_SEL(x)			(((x) >> BIT_SHIFT_XTAL_MANU_PK_SEL) & BIT_MASK_XTAL_MANU_PK_SEL)
#define BIT_SET_XTAL_MANU_PK_SEL(x, v)			(BIT_CLEAR_XTAL_MANU_PK_SEL(x) | BIT_XTAL_MANU_PK_SEL(v))

#define BIT_XTAL_AACK_PK_MANU				BIT(24)
#define BIT_EN_XTAL_AAC_PKDET				BIT(23)
#define BIT_EN_XTAL_AAC_GM				BIT(22)
#define BIT_XTAL_LDO_OPVB_SEL				BIT(21)
#define BIT_XTAL_LDO_NC				BIT(20)
#define BIT_XTAL_LPMODE				BIT(19)
#define BIT_XTAL_DELAY_DIGI				BIT(18)
#define BIT_XTAL_DELAY_USB				BIT(17)
#define BIT_XTAL_DELAY_AFE				BIT(16)

#define BIT_SHIFT_XTAL_DRV_DIGI			14
#define BIT_MASK_XTAL_DRV_DIGI				0x3
#define BIT_XTAL_DRV_DIGI(x)				(((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI)
#define BITS_XTAL_DRV_DIGI				(BIT_MASK_XTAL_DRV_DIGI << BIT_SHIFT_XTAL_DRV_DIGI)
#define BIT_CLEAR_XTAL_DRV_DIGI(x)			((x) & (~BITS_XTAL_DRV_DIGI))
#define BIT_GET_XTAL_DRV_DIGI(x)			(((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI)
#define BIT_SET_XTAL_DRV_DIGI(x, v)			(BIT_CLEAR_XTAL_DRV_DIGI(x) | BIT_XTAL_DRV_DIGI(v))

#define BIT_SHIFT_XTAL_DRV_USB				12
#define BIT_MASK_XTAL_DRV_USB				0x3
#define BIT_XTAL_DRV_USB(x)				(((x) & BIT_MASK_XTAL_DRV_USB) << BIT_SHIFT_XTAL_DRV_USB)
#define BITS_XTAL_DRV_USB				(BIT_MASK_XTAL_DRV_USB << BIT_SHIFT_XTAL_DRV_USB)
#define BIT_CLEAR_XTAL_DRV_USB(x)			((x) & (~BITS_XTAL_DRV_USB))
#define BIT_GET_XTAL_DRV_USB(x)			(((x) >> BIT_SHIFT_XTAL_DRV_USB) & BIT_MASK_XTAL_DRV_USB)
#define BIT_SET_XTAL_DRV_USB(x, v)			(BIT_CLEAR_XTAL_DRV_USB(x) | BIT_XTAL_DRV_USB(v))

#define BIT_SHIFT_XTAL_DRV_AFE				10
#define BIT_MASK_XTAL_DRV_AFE				0x3
#define BIT_XTAL_DRV_AFE(x)				(((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE)
#define BITS_XTAL_DRV_AFE				(BIT_MASK_XTAL_DRV_AFE << BIT_SHIFT_XTAL_DRV_AFE)
#define BIT_CLEAR_XTAL_DRV_AFE(x)			((x) & (~BITS_XTAL_DRV_AFE))
#define BIT_GET_XTAL_DRV_AFE(x)			(((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE)
#define BIT_SET_XTAL_DRV_AFE(x, v)			(BIT_CLEAR_XTAL_DRV_AFE(x) | BIT_XTAL_DRV_AFE(v))

#define BIT_SHIFT_XTAL_DRV_RF2				8
#define BIT_MASK_XTAL_DRV_RF2				0x3
#define BIT_XTAL_DRV_RF2(x)				(((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2)
#define BITS_XTAL_DRV_RF2				(BIT_MASK_XTAL_DRV_RF2 << BIT_SHIFT_XTAL_DRV_RF2)
#define BIT_CLEAR_XTAL_DRV_RF2(x)			((x) & (~BITS_XTAL_DRV_RF2))
#define BIT_GET_XTAL_DRV_RF2(x)			(((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2)
#define BIT_SET_XTAL_DRV_RF2(x, v)			(BIT_CLEAR_XTAL_DRV_RF2(x) | BIT_XTAL_DRV_RF2(v))

#define BIT_SHIFT_XTAL_DRV_RF1				6
#define BIT_MASK_XTAL_DRV_RF1				0x3
#define BIT_XTAL_DRV_RF1(x)				(((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1)
#define BITS_XTAL_DRV_RF1				(BIT_MASK_XTAL_DRV_RF1 << BIT_SHIFT_XTAL_DRV_RF1)
#define BIT_CLEAR_XTAL_DRV_RF1(x)			((x) & (~BITS_XTAL_DRV_RF1))
#define BIT_GET_XTAL_DRV_RF1(x)			(((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1)
#define BIT_SET_XTAL_DRV_RF1(x, v)			(BIT_CLEAR_XTAL_DRV_RF1(x) | BIT_XTAL_DRV_RF1(v))

#define BIT_XTAL_DRV_RF_LATCH				BIT(5)
#define BIT_XTAL_GM_SEP				BIT(4)
#define BIT_XQSEL_RF_AWAKE				BIT(3)
#define BIT_XQSEL_RF_INITIAL				BIT(2)
#define BIT_XQSEL					BIT(1)
#define BIT_GATED_XTAL_OK0				BIT(0)

/* 2 REG_WL_ANAPAR_XTAL_OFF1			(Offset 0x1070) */

#define BIT_SHIFT_XTAL_SRC_IQK_BCN			20
#define BIT_MASK_XTAL_SRC_IQK_BCN			0x7
#define BIT_XTAL_SRC_IQK_BCN(x)			(((x) & BIT_MASK_XTAL_SRC_IQK_BCN) << BIT_SHIFT_XTAL_SRC_IQK_BCN)
#define BITS_XTAL_SRC_IQK_BCN				(BIT_MASK_XTAL_SRC_IQK_BCN << BIT_SHIFT_XTAL_SRC_IQK_BCN)
#define BIT_CLEAR_XTAL_SRC_IQK_BCN(x)			((x) & (~BITS_XTAL_SRC_IQK_BCN))
#define BIT_GET_XTAL_SRC_IQK_BCN(x)			(((x) >> BIT_SHIFT_XTAL_SRC_IQK_BCN) & BIT_MASK_XTAL_SRC_IQK_BCN)
#define BIT_SET_XTAL_SRC_IQK_BCN(x, v)			(BIT_CLEAR_XTAL_SRC_IQK_BCN(x) | BIT_XTAL_SRC_IQK_BCN(v))

#define BIT_SHIFT_XTAL_SRC_BT				17
#define BIT_MASK_XTAL_SRC_BT				0x7
#define BIT_XTAL_SRC_BT(x)				(((x) & BIT_MASK_XTAL_SRC_BT) << BIT_SHIFT_XTAL_SRC_BT)
#define BITS_XTAL_SRC_BT				(BIT_MASK_XTAL_SRC_BT << BIT_SHIFT_XTAL_SRC_BT)
#define BIT_CLEAR_XTAL_SRC_BT(x)			((x) & (~BITS_XTAL_SRC_BT))
#define BIT_GET_XTAL_SRC_BT(x)				(((x) >> BIT_SHIFT_XTAL_SRC_BT) & BIT_MASK_XTAL_SRC_BT)
#define BIT_SET_XTAL_SRC_BT(x, v)			(BIT_CLEAR_XTAL_SRC_BT(x) | BIT_XTAL_SRC_BT(v))

#define BIT_SHIFT_XTAL_SRC_RF				14
#define BIT_MASK_XTAL_SRC_RF				0x7
#define BIT_XTAL_SRC_RF(x)				(((x) & BIT_MASK_XTAL_SRC_RF) << BIT_SHIFT_XTAL_SRC_RF)
#define BITS_XTAL_SRC_RF				(BIT_MASK_XTAL_SRC_RF << BIT_SHIFT_XTAL_SRC_RF)
#define BIT_CLEAR_XTAL_SRC_RF(x)			((x) & (~BITS_XTAL_SRC_RF))
#define BIT_GET_XTAL_SRC_RF(x)				(((x) >> BIT_SHIFT_XTAL_SRC_RF) & BIT_MASK_XTAL_SRC_RF)
#define BIT_SET_XTAL_SRC_RF(x, v)			(BIT_CLEAR_XTAL_SRC_RF(x) | BIT_XTAL_SRC_RF(v))

#define BIT_SHIFT_XTAL_DUMMY				10
#define BIT_MASK_XTAL_DUMMY				0xf
#define BIT_XTAL_DUMMY(x)				(((x) & BIT_MASK_XTAL_DUMMY) << BIT_SHIFT_XTAL_DUMMY)
#define BITS_XTAL_DUMMY				(BIT_MASK_XTAL_DUMMY << BIT_SHIFT_XTAL_DUMMY)
#define BIT_CLEAR_XTAL_DUMMY(x)			((x) & (~BITS_XTAL_DUMMY))
#define BIT_GET_XTAL_DUMMY(x)				(((x) >> BIT_SHIFT_XTAL_DUMMY) & BIT_MASK_XTAL_DUMMY)
#define BIT_SET_XTAL_DUMMY(x, v)			(BIT_CLEAR_XTAL_DUMMY(x) | BIT_XTAL_DUMMY(v))

#define BIT_XTAL_EN_LNBUF				BIT(9)
#define BIT_XTAL__AAC_TIE_MID				BIT(8)

#define BIT_SHIFT_XTAL_AAC_IOFFSET			6
#define BIT_MASK_XTAL_AAC_IOFFSET			0x3
#define BIT_XTAL_AAC_IOFFSET(x)			(((x) & BIT_MASK_XTAL_AAC_IOFFSET) << BIT_SHIFT_XTAL_AAC_IOFFSET)
#define BITS_XTAL_AAC_IOFFSET				(BIT_MASK_XTAL_AAC_IOFFSET << BIT_SHIFT_XTAL_AAC_IOFFSET)
#define BIT_CLEAR_XTAL_AAC_IOFFSET(x)			((x) & (~BITS_XTAL_AAC_IOFFSET))
#define BIT_GET_XTAL_AAC_IOFFSET(x)			(((x) >> BIT_SHIFT_XTAL_AAC_IOFFSET) & BIT_MASK_XTAL_AAC_IOFFSET)
#define BIT_SET_XTAL_AAC_IOFFSET(x, v)			(BIT_CLEAR_XTAL_AAC_IOFFSET(x) | BIT_XTAL_AAC_IOFFSET(v))

#define BIT_SHIFT_XTAL_AAC_CAP				4
#define BIT_MASK_XTAL_AAC_CAP				0x3
#define BIT_XTAL_AAC_CAP(x)				(((x) & BIT_MASK_XTAL_AAC_CAP) << BIT_SHIFT_XTAL_AAC_CAP)
#define BITS_XTAL_AAC_CAP				(BIT_MASK_XTAL_AAC_CAP << BIT_SHIFT_XTAL_AAC_CAP)
#define BIT_CLEAR_XTAL_AAC_CAP(x)			((x) & (~BITS_XTAL_AAC_CAP))
#define BIT_GET_XTAL_AAC_CAP(x)			(((x) >> BIT_SHIFT_XTAL_AAC_CAP) & BIT_MASK_XTAL_AAC_CAP)
#define BIT_SET_XTAL_AAC_CAP(x, v)			(BIT_CLEAR_XTAL_AAC_CAP(x) | BIT_XTAL_AAC_CAP(v))

#define BIT_SHIFT_XTAL_PDSW				2
#define BIT_MASK_XTAL_PDSW				0x3
#define BIT_XTAL_PDSW(x)				(((x) & BIT_MASK_XTAL_PDSW) << BIT_SHIFT_XTAL_PDSW)
#define BITS_XTAL_PDSW					(BIT_MASK_XTAL_PDSW << BIT_SHIFT_XTAL_PDSW)
#define BIT_CLEAR_XTAL_PDSW(x)				((x) & (~BITS_XTAL_PDSW))
#define BIT_GET_XTAL_PDSW(x)				(((x) >> BIT_SHIFT_XTAL_PDSW) & BIT_MASK_XTAL_PDSW)
#define BIT_SET_XTAL_PDSW(x, v)			(BIT_CLEAR_XTAL_PDSW(x) | BIT_XTAL_PDSW(v))

#define BIT_SHIFT_XTAL_LPS_BUF_VB			0
#define BIT_MASK_XTAL_LPS_BUF_VB			0x3
#define BIT_XTAL_LPS_BUF_VB(x)				(((x) & BIT_MASK_XTAL_LPS_BUF_VB) << BIT_SHIFT_XTAL_LPS_BUF_VB)
#define BITS_XTAL_LPS_BUF_VB				(BIT_MASK_XTAL_LPS_BUF_VB << BIT_SHIFT_XTAL_LPS_BUF_VB)
#define BIT_CLEAR_XTAL_LPS_BUF_VB(x)			((x) & (~BITS_XTAL_LPS_BUF_VB))
#define BIT_GET_XTAL_LPS_BUF_VB(x)			(((x) >> BIT_SHIFT_XTAL_LPS_BUF_VB) & BIT_MASK_XTAL_LPS_BUF_VB)
#define BIT_SET_XTAL_LPS_BUF_VB(x, v)			(BIT_CLEAR_XTAL_LPS_BUF_VB(x) | BIT_XTAL_LPS_BUF_VB(v))

/* 2 REG_ANAPAR_XTAL_AAC_OFF0		(Offset 0x1074) */

#define BIT_XAAC_LPOW					BIT(31)

#define BIT_SHIFT_AAC_MODE				29
#define BIT_MASK_AAC_MODE				0x3
#define BIT_AAC_MODE(x)				(((x) & BIT_MASK_AAC_MODE) << BIT_SHIFT_AAC_MODE)
#define BITS_AAC_MODE					(BIT_MASK_AAC_MODE << BIT_SHIFT_AAC_MODE)
#define BIT_CLEAR_AAC_MODE(x)				((x) & (~BITS_AAC_MODE))
#define BIT_GET_AAC_MODE(x)				(((x) >> BIT_SHIFT_AAC_MODE) & BIT_MASK_AAC_MODE)
#define BIT_SET_AAC_MODE(x, v)				(BIT_CLEAR_AAC_MODE(x) | BIT_AAC_MODE(v))

#define BIT_EN_XTAL_AAC_TRIG				BIT(28)
#define BIT_EN_XTAL_AAC_V1				BIT(27)
#define BIT_EN_XTAL_AAC_DIGI				BIT(26)

#define BIT_SHIFT_GM_MANUAL				21
#define BIT_MASK_GM_MANUAL				0x1f
#define BIT_GM_MANUAL(x)				(((x) & BIT_MASK_GM_MANUAL) << BIT_SHIFT_GM_MANUAL)
#define BITS_GM_MANUAL					(BIT_MASK_GM_MANUAL << BIT_SHIFT_GM_MANUAL)
#define BIT_CLEAR_GM_MANUAL(x)				((x) & (~BITS_GM_MANUAL))
#define BIT_GET_GM_MANUAL(x)				(((x) >> BIT_SHIFT_GM_MANUAL) & BIT_MASK_GM_MANUAL)
#define BIT_SET_GM_MANUAL(x, v)			(BIT_CLEAR_GM_MANUAL(x) | BIT_GM_MANUAL(v))

#define BIT_SHIFT_GM_STUP				16
#define BIT_MASK_GM_STUP				0x1f
#define BIT_GM_STUP(x)					(((x) & BIT_MASK_GM_STUP) << BIT_SHIFT_GM_STUP)
#define BITS_GM_STUP					(BIT_MASK_GM_STUP << BIT_SHIFT_GM_STUP)
#define BIT_CLEAR_GM_STUP(x)				((x) & (~BITS_GM_STUP))
#define BIT_GET_GM_STUP(x)				(((x) >> BIT_SHIFT_GM_STUP) & BIT_MASK_GM_STUP)
#define BIT_SET_GM_STUP(x, v)				(BIT_CLEAR_GM_STUP(x) | BIT_GM_STUP(v))

#define BIT_SHIFT_XTAL_CK_SET				13
#define BIT_MASK_XTAL_CK_SET				0x7
#define BIT_XTAL_CK_SET(x)				(((x) & BIT_MASK_XTAL_CK_SET) << BIT_SHIFT_XTAL_CK_SET)
#define BITS_XTAL_CK_SET				(BIT_MASK_XTAL_CK_SET << BIT_SHIFT_XTAL_CK_SET)
#define BIT_CLEAR_XTAL_CK_SET(x)			((x) & (~BITS_XTAL_CK_SET))
#define BIT_GET_XTAL_CK_SET(x)				(((x) >> BIT_SHIFT_XTAL_CK_SET) & BIT_MASK_XTAL_CK_SET)
#define BIT_SET_XTAL_CK_SET(x, v)			(BIT_CLEAR_XTAL_CK_SET(x) | BIT_XTAL_CK_SET(v))

#define BIT_SHIFT_GM_INIT				8
#define BIT_MASK_GM_INIT				0x1f
#define BIT_GM_INIT(x)					(((x) & BIT_MASK_GM_INIT) << BIT_SHIFT_GM_INIT)
#define BITS_GM_INIT					(BIT_MASK_GM_INIT << BIT_SHIFT_GM_INIT)
#define BIT_CLEAR_GM_INIT(x)				((x) & (~BITS_GM_INIT))
#define BIT_GET_GM_INIT(x)				(((x) >> BIT_SHIFT_GM_INIT) & BIT_MASK_GM_INIT)
#define BIT_SET_GM_INIT(x, v)				(BIT_CLEAR_GM_INIT(x) | BIT_GM_INIT(v))

#define BIT_GM_STEP					BIT(7)

#define BIT_SHIFT_XAAC_GM_OFFSET			2
#define BIT_MASK_XAAC_GM_OFFSET			0x1f
#define BIT_XAAC_GM_OFFSET(x)				(((x) & BIT_MASK_XAAC_GM_OFFSET) << BIT_SHIFT_XAAC_GM_OFFSET)
#define BITS_XAAC_GM_OFFSET				(BIT_MASK_XAAC_GM_OFFSET << BIT_SHIFT_XAAC_GM_OFFSET)
#define BIT_CLEAR_XAAC_GM_OFFSET(x)			((x) & (~BITS_XAAC_GM_OFFSET))
#define BIT_GET_XAAC_GM_OFFSET(x)			(((x) >> BIT_SHIFT_XAAC_GM_OFFSET) & BIT_MASK_XAAC_GM_OFFSET)
#define BIT_SET_XAAC_GM_OFFSET(x, v)			(BIT_CLEAR_XAAC_GM_OFFSET(x) | BIT_XAAC_GM_OFFSET(v))

#define BIT_OFFSET_PLUS				BIT(1)

/* 2 REG_ANAPAR_XTAL_AAC_OFF1		(Offset 0x1078) */

#define BIT_SHIFT_PK_END_AR				3
#define BIT_MASK_PK_END_AR				0x3
#define BIT_PK_END_AR(x)				(((x) & BIT_MASK_PK_END_AR) << BIT_SHIFT_PK_END_AR)
#define BITS_PK_END_AR					(BIT_MASK_PK_END_AR << BIT_SHIFT_PK_END_AR)
#define BIT_CLEAR_PK_END_AR(x)				((x) & (~BITS_PK_END_AR))
#define BIT_GET_PK_END_AR(x)				(((x) >> BIT_SHIFT_PK_END_AR) & BIT_MASK_PK_END_AR)
#define BIT_SET_PK_END_AR(x, v)			(BIT_CLEAR_PK_END_AR(x) | BIT_PK_END_AR(v))

#define BIT_SHIFT_PK_START_AR				1
#define BIT_MASK_PK_START_AR				0x3
#define BIT_PK_START_AR(x)				(((x) & BIT_MASK_PK_START_AR) << BIT_SHIFT_PK_START_AR)
#define BITS_PK_START_AR				(BIT_MASK_PK_START_AR << BIT_SHIFT_PK_START_AR)
#define BIT_CLEAR_PK_START_AR(x)			((x) & (~BITS_PK_START_AR))
#define BIT_GET_PK_START_AR(x)				(((x) >> BIT_SHIFT_PK_START_AR) & BIT_MASK_PK_START_AR)
#define BIT_SET_PK_START_AR(x, v)			(BIT_CLEAR_PK_START_AR(x) | BIT_PK_START_AR(v))

#define BIT_XAAC_LUT_MANUAL_EN				BIT(0)

/* 2 REG_XAAC_READ_ONLY_DATA			(Offset 0x107C) */

#define BIT_SHIFT_AAC_MODE_R1				17
#define BIT_MASK_AAC_MODE_R1				0x3
#define BIT_AAC_MODE_R1(x)				(((x) & BIT_MASK_AAC_MODE_R1) << BIT_SHIFT_AAC_MODE_R1)
#define BITS_AAC_MODE_R1				(BIT_MASK_AAC_MODE_R1 << BIT_SHIFT_AAC_MODE_R1)
#define BIT_CLEAR_AAC_MODE_R1(x)			((x) & (~BITS_AAC_MODE_R1))
#define BIT_GET_AAC_MODE_R1(x)				(((x) >> BIT_SHIFT_AAC_MODE_R1) & BIT_MASK_AAC_MODE_R1)
#define BIT_SET_AAC_MODE_R1(x, v)			(BIT_CLEAR_AAC_MODE_R1(x) | BIT_AAC_MODE_R1(v))

#define BIT_SHIFT_XAACK_DBG				14
#define BIT_MASK_XAACK_DBG				0x7
#define BIT_XAACK_DBG(x)				(((x) & BIT_MASK_XAACK_DBG) << BIT_SHIFT_XAACK_DBG)
#define BITS_XAACK_DBG					(BIT_MASK_XAACK_DBG << BIT_SHIFT_XAACK_DBG)
#define BIT_CLEAR_XAACK_DBG(x)				((x) & (~BITS_XAACK_DBG))
#define BIT_GET_XAACK_DBG(x)				(((x) >> BIT_SHIFT_XAACK_DBG) & BIT_MASK_XAACK_DBG)
#define BIT_SET_XAACK_DBG(x, v)			(BIT_CLEAR_XAACK_DBG(x) | BIT_XAACK_DBG(v))

#define BIT_SHIFT_XAACK_STATE				10
#define BIT_MASK_XAACK_STATE				0xf
#define BIT_XAACK_STATE(x)				(((x) & BIT_MASK_XAACK_STATE) << BIT_SHIFT_XAACK_STATE)
#define BITS_XAACK_STATE				(BIT_MASK_XAACK_STATE << BIT_SHIFT_XAACK_STATE)
#define BIT_CLEAR_XAACK_STATE(x)			((x) & (~BITS_XAACK_STATE))
#define BIT_GET_XAACK_STATE(x)				(((x) >> BIT_SHIFT_XAACK_STATE) & BIT_MASK_XAACK_STATE)
#define BIT_SET_XAACK_STATE(x, v)			(BIT_CLEAR_XAACK_STATE(x) | BIT_XAACK_STATE(v))

#define BIT_XTAL_PEAKDET_OUT				BIT(9)
#define BIT_XAAC_BUSY					BIT(8)
#define BIT_XAAC_READY					BIT(7)

#define BIT_SHIFT_XAAC_PK_SEL				5
#define BIT_MASK_XAAC_PK_SEL				0x3
#define BIT_XAAC_PK_SEL(x)				(((x) & BIT_MASK_XAAC_PK_SEL) << BIT_SHIFT_XAAC_PK_SEL)
#define BITS_XAAC_PK_SEL				(BIT_MASK_XAAC_PK_SEL << BIT_SHIFT_XAAC_PK_SEL)
#define BIT_CLEAR_XAAC_PK_SEL(x)			((x) & (~BITS_XAAC_PK_SEL))
#define BIT_GET_XAAC_PK_SEL(x)				(((x) >> BIT_SHIFT_XAAC_PK_SEL) & BIT_MASK_XAAC_PK_SEL)
#define BIT_SET_XAAC_PK_SEL(x, v)			(BIT_CLEAR_XAAC_PK_SEL(x) | BIT_XAAC_PK_SEL(v))

#define BIT_SHIFT_XTAL_GM_OUT				0
#define BIT_MASK_XTAL_GM_OUT				0x1f
#define BIT_XTAL_GM_OUT(x)				(((x) & BIT_MASK_XTAL_GM_OUT) << BIT_SHIFT_XTAL_GM_OUT)
#define BITS_XTAL_GM_OUT				(BIT_MASK_XTAL_GM_OUT << BIT_SHIFT_XTAL_GM_OUT)
#define BIT_CLEAR_XTAL_GM_OUT(x)			((x) & (~BITS_XTAL_GM_OUT))
#define BIT_GET_XTAL_GM_OUT(x)				(((x) >> BIT_SHIFT_XTAL_GM_OUT) & BIT_MASK_XTAL_GM_OUT)
#define BIT_SET_XTAL_GM_OUT(x, v)			(BIT_CLEAR_XTAL_GM_OUT(x) | BIT_XTAL_GM_OUT(v))

/* 2 REG_ANAPAR_PDCK_OFF			(Offset 0x1080) */

#define BIT_PDCK_LPOW					BIT(22)

#define BIT_SHIFT_XPDCK_VREF_SEL			17
#define BIT_MASK_XPDCK_VREF_SEL			0x1f
#define BIT_XPDCK_VREF_SEL(x)				(((x) & BIT_MASK_XPDCK_VREF_SEL) << BIT_SHIFT_XPDCK_VREF_SEL)
#define BITS_XPDCK_VREF_SEL				(BIT_MASK_XPDCK_VREF_SEL << BIT_SHIFT_XPDCK_VREF_SEL)
#define BIT_CLEAR_XPDCK_VREF_SEL(x)			((x) & (~BITS_XPDCK_VREF_SEL))
#define BIT_GET_XPDCK_VREF_SEL(x)			(((x) >> BIT_SHIFT_XPDCK_VREF_SEL) & BIT_MASK_XPDCK_VREF_SEL)
#define BIT_SET_XPDCK_VREF_SEL(x, v)			(BIT_CLEAR_XPDCK_VREF_SEL(x) | BIT_XPDCK_VREF_SEL(v))

#define BIT_SHIFT_XTAL_PDCK_UNIT			15
#define BIT_MASK_XTAL_PDCK_UNIT			0x3
#define BIT_XTAL_PDCK_UNIT(x)				(((x) & BIT_MASK_XTAL_PDCK_UNIT) << BIT_SHIFT_XTAL_PDCK_UNIT)
#define BITS_XTAL_PDCK_UNIT				(BIT_MASK_XTAL_PDCK_UNIT << BIT_SHIFT_XTAL_PDCK_UNIT)
#define BIT_CLEAR_XTAL_PDCK_UNIT(x)			((x) & (~BITS_XTAL_PDCK_UNIT))
#define BIT_GET_XTAL_PDCK_UNIT(x)			(((x) >> BIT_SHIFT_XTAL_PDCK_UNIT) & BIT_MASK_XTAL_PDCK_UNIT)
#define BIT_SET_XTAL_PDCK_UNIT(x, v)			(BIT_CLEAR_XTAL_PDCK_UNIT(x) | BIT_XTAL_PDCK_UNIT(v))

#define BIT_SHIFT_VREF_INIT				10
#define BIT_MASK_VREF_INIT				0x1f
#define BIT_VREF_INIT(x)				(((x) & BIT_MASK_VREF_INIT) << BIT_SHIFT_VREF_INIT)
#define BITS_VREF_INIT					(BIT_MASK_VREF_INIT << BIT_SHIFT_VREF_INIT)
#define BIT_CLEAR_VREF_INIT(x)				((x) & (~BITS_VREF_INIT))
#define BIT_GET_VREF_INIT(x)				(((x) >> BIT_SHIFT_VREF_INIT) & BIT_MASK_VREF_INIT)
#define BIT_SET_VREF_INIT(x, v)			(BIT_CLEAR_VREF_INIT(x) | BIT_VREF_INIT(v))

#define BIT_SHIFT_VREF_MANUAL				5
#define BIT_MASK_VREF_MANUAL				0x1f
#define BIT_VREF_MANUAL(x)				(((x) & BIT_MASK_VREF_MANUAL) << BIT_SHIFT_VREF_MANUAL)
#define BITS_VREF_MANUAL				(BIT_MASK_VREF_MANUAL << BIT_SHIFT_VREF_MANUAL)
#define BIT_CLEAR_VREF_MANUAL(x)			((x) & (~BITS_VREF_MANUAL))
#define BIT_GET_VREF_MANUAL(x)				(((x) >> BIT_SHIFT_VREF_MANUAL) & BIT_MASK_VREF_MANUAL)
#define BIT_SET_VREF_MANUAL(x, v)			(BIT_CLEAR_VREF_MANUAL(x) | BIT_VREF_MANUAL(v))

#define BIT_SHIFT_PDCK_WAIT_CYC			3
#define BIT_MASK_PDCK_WAIT_CYC				0x3
#define BIT_PDCK_WAIT_CYC(x)				(((x) & BIT_MASK_PDCK_WAIT_CYC) << BIT_SHIFT_PDCK_WAIT_CYC)
#define BITS_PDCK_WAIT_CYC				(BIT_MASK_PDCK_WAIT_CYC << BIT_SHIFT_PDCK_WAIT_CYC)
#define BIT_CLEAR_PDCK_WAIT_CYC(x)			((x) & (~BITS_PDCK_WAIT_CYC))
#define BIT_GET_PDCK_WAIT_CYC(x)			(((x) >> BIT_SHIFT_PDCK_WAIT_CYC) & BIT_MASK_PDCK_WAIT_CYC)
#define BIT_SET_PDCK_WAIT_CYC(x, v)			(BIT_CLEAR_PDCK_WAIT_CYC(x) | BIT_PDCK_WAIT_CYC(v))

#define BIT_PDCK_SEARCH_MODE				BIT(2)
#define BIT_EN_XTAL_PDCK_DIGI				BIT(1)

/* 2 REG__PDCK_READ_ONLY_DATA		(Offset 0x1084) */

#define BIT_SHIFT_PDCK_STATE				19
#define BIT_MASK_PDCK_STATE				0xf
#define BIT_PDCK_STATE(x)				(((x) & BIT_MASK_PDCK_STATE) << BIT_SHIFT_PDCK_STATE)
#define BITS_PDCK_STATE				(BIT_MASK_PDCK_STATE << BIT_SHIFT_PDCK_STATE)
#define BIT_CLEAR_PDCK_STATE(x)			((x) & (~BITS_PDCK_STATE))
#define BIT_GET_PDCK_STATE(x)				(((x) >> BIT_SHIFT_PDCK_STATE) & BIT_MASK_PDCK_STATE)
#define BIT_SET_PDCK_STATE(x, v)			(BIT_CLEAR_PDCK_STATE(x) | BIT_PDCK_STATE(v))

#define BIT_XPDCK_BUSY					BIT(18)
#define BIT_XPDCK_READY				BIT(17)

#define BIT_SHIFT_XPDCK_VREF_OUT			12
#define BIT_MASK_XPDCK_VREF_OUT			0x1f
#define BIT_XPDCK_VREF_OUT(x)				(((x) & BIT_MASK_XPDCK_VREF_OUT) << BIT_SHIFT_XPDCK_VREF_OUT)
#define BITS_XPDCK_VREF_OUT				(BIT_MASK_XPDCK_VREF_OUT << BIT_SHIFT_XPDCK_VREF_OUT)
#define BIT_CLEAR_XPDCK_VREF_OUT(x)			((x) & (~BITS_XPDCK_VREF_OUT))
#define BIT_GET_XPDCK_VREF_OUT(x)			(((x) >> BIT_SHIFT_XPDCK_VREF_OUT) & BIT_MASK_XPDCK_VREF_OUT)
#define BIT_SET_XPDCK_VREF_OUT(x, v)			(BIT_CLEAR_XPDCK_VREF_OUT(x) | BIT_XPDCK_VREF_OUT(v))

#define BIT_BT_XPDCK_GNT				BIT(11)
#define BIT_WL_XPDCK_GNT				BIT(10)
#define BIT_BT_XPDCK_REQ				BIT(9)
#define BIT_WL_XPDCK_REQ				BIT(8)
#define BIT_XPDCK_BUSY_WL				BIT(6)
#define BIT_XPDCK_READY_WL				BIT(5)

#define BIT_SHIFT_XPDCK_VREF_OUT_WL			0
#define BIT_MASK_XPDCK_VREF_OUT_WL			0x1f
#define BIT_XPDCK_VREF_OUT_WL(x)			(((x) & BIT_MASK_XPDCK_VREF_OUT_WL) << BIT_SHIFT_XPDCK_VREF_OUT_WL)
#define BITS_XPDCK_VREF_OUT_WL				(BIT_MASK_XPDCK_VREF_OUT_WL << BIT_SHIFT_XPDCK_VREF_OUT_WL)
#define BIT_CLEAR_XPDCK_VREF_OUT_WL(x)			((x) & (~BITS_XPDCK_VREF_OUT_WL))
#define BIT_GET_XPDCK_VREF_OUT_WL(x)			(((x) >> BIT_SHIFT_XPDCK_VREF_OUT_WL) & BIT_MASK_XPDCK_VREF_OUT_WL)
#define BIT_SET_XPDCK_VREF_OUT_WL(x, v)		(BIT_CLEAR_XPDCK_VREF_OUT_WL(x) | BIT_XPDCK_VREF_OUT_WL(v))

/* 2 REG_ANAPARSW_MAC_OFF0			(Offset 0x1088) */

#define BIT_SHIFT_SDZN_L				30
#define BIT_MASK_SDZN_L				0x3
#define BIT_SDZN_L(x)					(((x) & BIT_MASK_SDZN_L) << BIT_SHIFT_SDZN_L)
#define BITS_SDZN_L					(BIT_MASK_SDZN_L << BIT_SHIFT_SDZN_L)
#define BIT_CLEAR_SDZN_L(x)				((x) & (~BITS_SDZN_L))
#define BIT_GET_SDZN_L(x)				(((x) >> BIT_SHIFT_SDZN_L) & BIT_MASK_SDZN_L)
#define BIT_SET_SDZN_L(x, v)				(BIT_CLEAR_SDZN_L(x) | BIT_SDZN_L(v))

#define BIT_REG_AUTOZCD_L				BIT(29)
#define BIT_REG_VOFB_SEL				BIT(28)

#define BIT_SHIFT_TBOX_L1				26
#define BIT_MASK_TBOX_L1				0x3
#define BIT_TBOX_L1(x)					(((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1)
#define BITS_TBOX_L1					(BIT_MASK_TBOX_L1 << BIT_SHIFT_TBOX_L1)
#define BIT_CLEAR_TBOX_L1(x)				((x) & (~BITS_TBOX_L1))
#define BIT_GET_TBOX_L1(x)				(((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1)
#define BIT_SET_TBOX_L1(x, v)				(BIT_CLEAR_TBOX_L1(x) | BIT_TBOX_L1(v))

#define BIT_ENOCPMUX_L					BIT(25)
#define BIT_FORCE_LDOS					BIT(24)
#define BIT_VO_DISCHG					BIT(23)
#define BIT_LDO_OC_CLAMP				BIT(22)
#define BIT_MINOFF_LIQ					BIT(21)
#define BIT_MINON_LIQ					BIT(20)
#define BIT_POW_AUTO_L					BIT(19)
#define BIT_ARENB_H					BIT(18)
#define BIT_NO_OFFTIME_L				BIT(17)
#define BIT_EN_ON_END_L				BIT(16)
#define BIT_ENCOT_L					BIT(15)

#define BIT_SHIFT_REG_CLK_SEL				13
#define BIT_MASK_REG_CLK_SEL				0x3
#define BIT_REG_CLK_SEL(x)				(((x) & BIT_MASK_REG_CLK_SEL) << BIT_SHIFT_REG_CLK_SEL)
#define BITS_REG_CLK_SEL				(BIT_MASK_REG_CLK_SEL << BIT_SHIFT_REG_CLK_SEL)
#define BIT_CLEAR_REG_CLK_SEL(x)			((x) & (~BITS_REG_CLK_SEL))
#define BIT_GET_REG_CLK_SEL(x)				(((x) >> BIT_SHIFT_REG_CLK_SEL) & BIT_MASK_REG_CLK_SEL)
#define BIT_SET_REG_CLK_SEL(x, v)			(BIT_CLEAR_REG_CLK_SEL(x) | BIT_REG_CLK_SEL(v))

#define BIT_REG_TYPE_L					BIT(12)

#define BIT_SHIFT_R3_L1				10
#define BIT_MASK_R3_L1					0x3
#define BIT_R3_L1(x)					(((x) & BIT_MASK_R3_L1) << BIT_SHIFT_R3_L1)
#define BITS_R3_L1					(BIT_MASK_R3_L1 << BIT_SHIFT_R3_L1)
#define BIT_CLEAR_R3_L1(x)				((x) & (~BITS_R3_L1))
#define BIT_GET_R3_L1(x)				(((x) >> BIT_SHIFT_R3_L1) & BIT_MASK_R3_L1)
#define BIT_SET_R3_L1(x, v)				(BIT_CLEAR_R3_L1(x) | BIT_R3_L1(v))

#define BIT_SHIFT_R2_L1				8
#define BIT_MASK_R2_L1					0x3
#define BIT_R2_L1(x)					(((x) & BIT_MASK_R2_L1) << BIT_SHIFT_R2_L1)
#define BITS_R2_L1					(BIT_MASK_R2_L1 << BIT_SHIFT_R2_L1)
#define BIT_CLEAR_R2_L1(x)				((x) & (~BITS_R2_L1))
#define BIT_GET_R2_L1(x)				(((x) >> BIT_SHIFT_R2_L1) & BIT_MASK_R2_L1)
#define BIT_SET_R2_L1(x, v)				(BIT_CLEAR_R2_L1(x) | BIT_R2_L1(v))

#define BIT_SHIFT_R1_L1				6
#define BIT_MASK_R1_L1					0x3
#define BIT_R1_L1(x)					(((x) & BIT_MASK_R1_L1) << BIT_SHIFT_R1_L1)
#define BITS_R1_L1					(BIT_MASK_R1_L1 << BIT_SHIFT_R1_L1)
#define BIT_CLEAR_R1_L1(x)				((x) & (~BITS_R1_L1))
#define BIT_GET_R1_L1(x)				(((x) >> BIT_SHIFT_R1_L1) & BIT_MASK_R1_L1)
#define BIT_SET_R1_L1(x, v)				(BIT_CLEAR_R1_L1(x) | BIT_R1_L1(v))

#define BIT_SHIFT_C3_L1				4
#define BIT_MASK_C3_L1					0x3
#define BIT_C3_L1(x)					(((x) & BIT_MASK_C3_L1) << BIT_SHIFT_C3_L1)
#define BITS_C3_L1					(BIT_MASK_C3_L1 << BIT_SHIFT_C3_L1)
#define BIT_CLEAR_C3_L1(x)				((x) & (~BITS_C3_L1))
#define BIT_GET_C3_L1(x)				(((x) >> BIT_SHIFT_C3_L1) & BIT_MASK_C3_L1)
#define BIT_SET_C3_L1(x, v)				(BIT_CLEAR_C3_L1(x) | BIT_C3_L1(v))

#define BIT_SHIFT_C2_L1				2
#define BIT_MASK_C2_L1					0x3
#define BIT_C2_L1(x)					(((x) & BIT_MASK_C2_L1) << BIT_SHIFT_C2_L1)
#define BITS_C2_L1					(BIT_MASK_C2_L1 << BIT_SHIFT_C2_L1)
#define BIT_CLEAR_C2_L1(x)				((x) & (~BITS_C2_L1))
#define BIT_GET_C2_L1(x)				(((x) >> BIT_SHIFT_C2_L1) & BIT_MASK_C2_L1)
#define BIT_SET_C2_L1(x, v)				(BIT_CLEAR_C2_L1(x) | BIT_C2_L1(v))

#define BIT_SHIFT_C1_L1				0
#define BIT_MASK_C1_L1					0x3
#define BIT_C1_L1(x)					(((x) & BIT_MASK_C1_L1) << BIT_SHIFT_C1_L1)
#define BITS_C1_L1					(BIT_MASK_C1_L1 << BIT_SHIFT_C1_L1)
#define BIT_CLEAR_C1_L1(x)				((x) & (~BITS_C1_L1))
#define BIT_GET_C1_L1(x)				(((x) >> BIT_SHIFT_C1_L1) & BIT_MASK_C1_L1)
#define BIT_SET_C1_L1(x, v)				(BIT_CLEAR_C1_L1(x) | BIT_C1_L1(v))

/* 2 REG_ANAPARSW_MAC_OFF1			(Offset 0x108C) */

#define BIT_REG_NMOS_OFF_L				BIT(5)
#define BIT_REG_MUX_PI_L				BIT(4)
#define BIT_REG_PWM_CTRL_L				BIT(3)
#define BIT_ENSR_L					BIT(2)

#define BIT_SHIFT_SDZP_L				0
#define BIT_MASK_SDZP_L				0x3
#define BIT_SDZP_L(x)					(((x) & BIT_MASK_SDZP_L) << BIT_SHIFT_SDZP_L)
#define BITS_SDZP_L					(BIT_MASK_SDZP_L << BIT_SHIFT_SDZP_L)
#define BIT_CLEAR_SDZP_L(x)				((x) & (~BITS_SDZP_L))
#define BIT_GET_SDZP_L(x)				(((x) >> BIT_SHIFT_SDZP_L) & BIT_MASK_SDZP_L)
#define BIT_SET_SDZP_L(x, v)				(BIT_CLEAR_SDZP_L(x) | BIT_SDZP_L(v))

/* 2 REG_FW_DBG0				(Offset 0x1090) */

#define BIT_SHIFT_FW_DBG0				0
#define BIT_MASK_FW_DBG0				0xffffffffL
#define BIT_FW_DBG0(x)					(((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0)
#define BITS_FW_DBG0					(BIT_MASK_FW_DBG0 << BIT_SHIFT_FW_DBG0)
#define BIT_CLEAR_FW_DBG0(x)				((x) & (~BITS_FW_DBG0))
#define BIT_GET_FW_DBG0(x)				(((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0)
#define BIT_SET_FW_DBG0(x, v)				(BIT_CLEAR_FW_DBG0(x) | BIT_FW_DBG0(v))

/* 2 REG_FW_DBG1				(Offset 0x1094) */

#define BIT_SHIFT_FW_DBG1				0
#define BIT_MASK_FW_DBG1				0xffffffffL
#define BIT_FW_DBG1(x)					(((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1)
#define BITS_FW_DBG1					(BIT_MASK_FW_DBG1 << BIT_SHIFT_FW_DBG1)
#define BIT_CLEAR_FW_DBG1(x)				((x) & (~BITS_FW_DBG1))
#define BIT_GET_FW_DBG1(x)				(((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1)
#define BIT_SET_FW_DBG1(x, v)				(BIT_CLEAR_FW_DBG1(x) | BIT_FW_DBG1(v))

/* 2 REG_FW_DBG2				(Offset 0x1098) */

#define BIT_SHIFT_FW_DBG2				0
#define BIT_MASK_FW_DBG2				0xffffffffL
#define BIT_FW_DBG2(x)					(((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2)
#define BITS_FW_DBG2					(BIT_MASK_FW_DBG2 << BIT_SHIFT_FW_DBG2)
#define BIT_CLEAR_FW_DBG2(x)				((x) & (~BITS_FW_DBG2))
#define BIT_GET_FW_DBG2(x)				(((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2)
#define BIT_SET_FW_DBG2(x, v)				(BIT_CLEAR_FW_DBG2(x) | BIT_FW_DBG2(v))

/* 2 REG_FW_DBG3				(Offset 0x109C) */

#define BIT_SHIFT_FW_DBG3				0
#define BIT_MASK_FW_DBG3				0xffffffffL
#define BIT_FW_DBG3(x)					(((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3)
#define BITS_FW_DBG3					(BIT_MASK_FW_DBG3 << BIT_SHIFT_FW_DBG3)
#define BIT_CLEAR_FW_DBG3(x)				((x) & (~BITS_FW_DBG3))
#define BIT_GET_FW_DBG3(x)				(((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3)
#define BIT_SET_FW_DBG3(x, v)				(BIT_CLEAR_FW_DBG3(x) | BIT_FW_DBG3(v))

/* 2 REG_FW_DBG4				(Offset 0x10A0) */

#define BIT_SHIFT_FW_DBG4				0
#define BIT_MASK_FW_DBG4				0xffffffffL
#define BIT_FW_DBG4(x)					(((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4)
#define BITS_FW_DBG4					(BIT_MASK_FW_DBG4 << BIT_SHIFT_FW_DBG4)
#define BIT_CLEAR_FW_DBG4(x)				((x) & (~BITS_FW_DBG4))
#define BIT_GET_FW_DBG4(x)				(((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4)
#define BIT_SET_FW_DBG4(x, v)				(BIT_CLEAR_FW_DBG4(x) | BIT_FW_DBG4(v))

/* 2 REG_FW_DBG5				(Offset 0x10A4) */

#define BIT_SHIFT_FW_DBG5				0
#define BIT_MASK_FW_DBG5				0xffffffffL
#define BIT_FW_DBG5(x)					(((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5)
#define BITS_FW_DBG5					(BIT_MASK_FW_DBG5 << BIT_SHIFT_FW_DBG5)
#define BIT_CLEAR_FW_DBG5(x)				((x) & (~BITS_FW_DBG5))
#define BIT_GET_FW_DBG5(x)				(((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5)
#define BIT_SET_FW_DBG5(x, v)				(BIT_CLEAR_FW_DBG5(x) | BIT_FW_DBG5(v))

/* 2 REG_FW_DBG6				(Offset 0x10A8) */

#define BIT_SHIFT_FW_DBG6				0
#define BIT_MASK_FW_DBG6				0xffffffffL
#define BIT_FW_DBG6(x)					(((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6)
#define BITS_FW_DBG6					(BIT_MASK_FW_DBG6 << BIT_SHIFT_FW_DBG6)
#define BIT_CLEAR_FW_DBG6(x)				((x) & (~BITS_FW_DBG6))
#define BIT_GET_FW_DBG6(x)				(((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6)
#define BIT_SET_FW_DBG6(x, v)				(BIT_CLEAR_FW_DBG6(x) | BIT_FW_DBG6(v))

/* 2 REG_FW_DBG7				(Offset 0x10AC) */

#define BIT_SHIFT_RFSI_SEL				30
#define BIT_MASK_RFSI_SEL				0x3
#define BIT_RFSI_SEL(x)				(((x) & BIT_MASK_RFSI_SEL) << BIT_SHIFT_RFSI_SEL)
#define BITS_RFSI_SEL					(BIT_MASK_RFSI_SEL << BIT_SHIFT_RFSI_SEL)
#define BIT_CLEAR_RFSI_SEL(x)				((x) & (~BITS_RFSI_SEL))
#define BIT_GET_RFSI_SEL(x)				(((x) >> BIT_SHIFT_RFSI_SEL) & BIT_MASK_RFSI_SEL)
#define BIT_SET_RFSI_SEL(x, v)				(BIT_CLEAR_RFSI_SEL(x) | BIT_RFSI_SEL(v))

#define BIT_VPROB_EN0					BIT(28)

#define BIT_SHIFT_GPIO_DMUX_SEL3			24
#define BIT_MASK_GPIO_DMUX_SEL3			0x1f
#define BIT_GPIO_DMUX_SEL3(x)				(((x) & BIT_MASK_GPIO_DMUX_SEL3) << BIT_SHIFT_GPIO_DMUX_SEL3)
#define BITS_GPIO_DMUX_SEL3				(BIT_MASK_GPIO_DMUX_SEL3 << BIT_SHIFT_GPIO_DMUX_SEL3)
#define BIT_CLEAR_GPIO_DMUX_SEL3(x)			((x) & (~BITS_GPIO_DMUX_SEL3))
#define BIT_GET_GPIO_DMUX_SEL3(x)			(((x) >> BIT_SHIFT_GPIO_DMUX_SEL3) & BIT_MASK_GPIO_DMUX_SEL3)
#define BIT_SET_GPIO_DMUX_SEL3(x, v)			(BIT_CLEAR_GPIO_DMUX_SEL3(x) | BIT_GPIO_DMUX_SEL3(v))

#define BIT_SHIFT_GPIO_DMUX_SEL7			24
#define BIT_MASK_GPIO_DMUX_SEL7			0x1f
#define BIT_GPIO_DMUX_SEL7(x)				(((x) & BIT_MASK_GPIO_DMUX_SEL7) << BIT_SHIFT_GPIO_DMUX_SEL7)
#define BITS_GPIO_DMUX_SEL7				(BIT_MASK_GPIO_DMUX_SEL7 << BIT_SHIFT_GPIO_DMUX_SEL7)
#define BIT_CLEAR_GPIO_DMUX_SEL7(x)			((x) & (~BITS_GPIO_DMUX_SEL7))
#define BIT_GET_GPIO_DMUX_SEL7(x)			(((x) >> BIT_SHIFT_GPIO_DMUX_SEL7) & BIT_MASK_GPIO_DMUX_SEL7)
#define BIT_SET_GPIO_DMUX_SEL7(x, v)			(BIT_CLEAR_GPIO_DMUX_SEL7(x) | BIT_GPIO_DMUX_SEL7(v))

#define BIT_SHIFT_GPIO_DMUX_SEL2			16
#define BIT_MASK_GPIO_DMUX_SEL2			0x1f
#define BIT_GPIO_DMUX_SEL2(x)				(((x) & BIT_MASK_GPIO_DMUX_SEL2) << BIT_SHIFT_GPIO_DMUX_SEL2)
#define BITS_GPIO_DMUX_SEL2				(BIT_MASK_GPIO_DMUX_SEL2 << BIT_SHIFT_GPIO_DMUX_SEL2)
#define BIT_CLEAR_GPIO_DMUX_SEL2(x)			((x) & (~BITS_GPIO_DMUX_SEL2))
#define BIT_GET_GPIO_DMUX_SEL2(x)			(((x) >> BIT_SHIFT_GPIO_DMUX_SEL2) & BIT_MASK_GPIO_DMUX_SEL2)
#define BIT_SET_GPIO_DMUX_SEL2(x, v)			(BIT_CLEAR_GPIO_DMUX_SEL2(x) | BIT_GPIO_DMUX_SEL2(v))

#define BIT_SHIFT_GPIO_DMUX_SEL6			16
#define BIT_MASK_GPIO_DMUX_SEL6			0x1f
#define BIT_GPIO_DMUX_SEL6(x)				(((x) & BIT_MASK_GPIO_DMUX_SEL6) << BIT_SHIFT_GPIO_DMUX_SEL6)
#define BITS_GPIO_DMUX_SEL6				(BIT_MASK_GPIO_DMUX_SEL6 << BIT_SHIFT_GPIO_DMUX_SEL6)
#define BIT_CLEAR_GPIO_DMUX_SEL6(x)			((x) & (~BITS_GPIO_DMUX_SEL6))
#define BIT_GET_GPIO_DMUX_SEL6(x)			(((x) >> BIT_SHIFT_GPIO_DMUX_SEL6) & BIT_MASK_GPIO_DMUX_SEL6)
#define BIT_SET_GPIO_DMUX_SEL6(x, v)			(BIT_CLEAR_GPIO_DMUX_SEL6(x) | BIT_GPIO_DMUX_SEL6(v))

#define BIT_VPROB_USB1_OE				BIT(11)
#define BIT_VPROB_USB0_OE				BIT(10)
#define BIT_VPROB_BT_OFF1_OE				BIT(9)
#define BIT_VPROB_BT_OFF0_OE				BIT(8)

#define BIT_SHIFT_GPIO_DMUX_SEL1			8
#define BIT_MASK_GPIO_DMUX_SEL1			0x1f
#define BIT_GPIO_DMUX_SEL1(x)				(((x) & BIT_MASK_GPIO_DMUX_SEL1) << BIT_SHIFT_GPIO_DMUX_SEL1)
#define BITS_GPIO_DMUX_SEL1				(BIT_MASK_GPIO_DMUX_SEL1 << BIT_SHIFT_GPIO_DMUX_SEL1)
#define BIT_CLEAR_GPIO_DMUX_SEL1(x)			((x) & (~BITS_GPIO_DMUX_SEL1))
#define BIT_GET_GPIO_DMUX_SEL1(x)			(((x) >> BIT_SHIFT_GPIO_DMUX_SEL1) & BIT_MASK_GPIO_DMUX_SEL1)
#define BIT_SET_GPIO_DMUX_SEL1(x, v)			(BIT_CLEAR_GPIO_DMUX_SEL1(x) | BIT_GPIO_DMUX_SEL1(v))

#define BIT_SHIFT_GPIO_DMUX_SEL5			8
#define BIT_MASK_GPIO_DMUX_SEL5			0x1f
#define BIT_GPIO_DMUX_SEL5(x)				(((x) & BIT_MASK_GPIO_DMUX_SEL5) << BIT_SHIFT_GPIO_DMUX_SEL5)
#define BITS_GPIO_DMUX_SEL5				(BIT_MASK_GPIO_DMUX_SEL5 << BIT_SHIFT_GPIO_DMUX_SEL5)
#define BIT_CLEAR_GPIO_DMUX_SEL5(x)			((x) & (~BITS_GPIO_DMUX_SEL5))
#define BIT_GET_GPIO_DMUX_SEL5(x)			(((x) >> BIT_SHIFT_GPIO_DMUX_SEL5) & BIT_MASK_GPIO_DMUX_SEL5)
#define BIT_SET_GPIO_DMUX_SEL5(x, v)			(BIT_CLEAR_GPIO_DMUX_SEL5(x) | BIT_GPIO_DMUX_SEL5(v))

#define BIT_VPROB_BT_PON1_OE				BIT(7)
#define BIT_UPHY_SLB_HS				BIT(7)
#define BIT_VPROB_BT_PON0_OE				BIT(6)
#define BIT_UPHY_FORCE_SLB				BIT(6)
#define BIT_VPROB_WL_OFF1_OE				BIT(5)
#define BIT_UPHY_SLB_FAIL				BIT(5)
#define BIT_VPROB_WL_OFF0_OE				BIT(4)
#define BIT_UPHY_SLB_DONE				BIT(4)
#define BIT_VPROB_WL_PON1_OE				BIT(3)
#define BIT_UPHY_SLB_CMD				BIT(3)
#define BIT_VPROB_WL_PON0_OE				BIT(2)
#define BIT_UPHY_SLB_HW_PRD				BIT(2)
#define BIT_VPROB_AON1_OE				BIT(1)
#define BIT_UPHY_HS_SLB_OK				BIT(1)

#define BIT_SHIFT_FW_DBG7				0
#define BIT_MASK_FW_DBG7				0xffffffffL
#define BIT_FW_DBG7(x)					(((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7)
#define BITS_FW_DBG7					(BIT_MASK_FW_DBG7 << BIT_SHIFT_FW_DBG7)
#define BIT_CLEAR_FW_DBG7(x)				((x) & (~BITS_FW_DBG7))
#define BIT_GET_FW_DBG7(x)				(((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7)
#define BIT_SET_FW_DBG7(x, v)				(BIT_CLEAR_FW_DBG7(x) | BIT_FW_DBG7(v))

#define BIT_VPROB_AON0_OE				BIT(0)

#define BIT_SHIFT_GPIO_DMUX_SEL0			0
#define BIT_MASK_GPIO_DMUX_SEL0			0x1f
#define BIT_GPIO_DMUX_SEL0(x)				(((x) & BIT_MASK_GPIO_DMUX_SEL0) << BIT_SHIFT_GPIO_DMUX_SEL0)
#define BITS_GPIO_DMUX_SEL0				(BIT_MASK_GPIO_DMUX_SEL0 << BIT_SHIFT_GPIO_DMUX_SEL0)
#define BIT_CLEAR_GPIO_DMUX_SEL0(x)			((x) & (~BITS_GPIO_DMUX_SEL0))
#define BIT_GET_GPIO_DMUX_SEL0(x)			(((x) >> BIT_SHIFT_GPIO_DMUX_SEL0) & BIT_MASK_GPIO_DMUX_SEL0)
#define BIT_SET_GPIO_DMUX_SEL0(x, v)			(BIT_CLEAR_GPIO_DMUX_SEL0(x) | BIT_GPIO_DMUX_SEL0(v))

#define BIT_SHIFT_GPIO_DMUX_SEL4			0
#define BIT_MASK_GPIO_DMUX_SEL4			0x1f
#define BIT_GPIO_DMUX_SEL4(x)				(((x) & BIT_MASK_GPIO_DMUX_SEL4) << BIT_SHIFT_GPIO_DMUX_SEL4)
#define BITS_GPIO_DMUX_SEL4				(BIT_MASK_GPIO_DMUX_SEL4 << BIT_SHIFT_GPIO_DMUX_SEL4)
#define BIT_CLEAR_GPIO_DMUX_SEL4(x)			((x) & (~BITS_GPIO_DMUX_SEL4))
#define BIT_GET_GPIO_DMUX_SEL4(x)			(((x) >> BIT_SHIFT_GPIO_DMUX_SEL4) & BIT_MASK_GPIO_DMUX_SEL4)
#define BIT_SET_GPIO_DMUX_SEL4(x, v)			(BIT_CLEAR_GPIO_DMUX_SEL4(x) | BIT_GPIO_DMUX_SEL4(v))

#define BIT_UPHY_FS_SLB_OK				BIT(0)

/* 2 REG_PAD_CTRL				(Offset 0x10C0) */

#define BIT_GPIO_GRP_SEL				BIT(14)
#define BIT_GPIO_GRP_SET				BIT(13)

#define BIT_SHIFT_GPIO_GRP_FID				8
#define BIT_MASK_GPIO_GRP_FID				0x1f
#define BIT_GPIO_GRP_FID(x)				(((x) & BIT_MASK_GPIO_GRP_FID) << BIT_SHIFT_GPIO_GRP_FID)
#define BITS_GPIO_GRP_FID				(BIT_MASK_GPIO_GRP_FID << BIT_SHIFT_GPIO_GRP_FID)
#define BIT_CLEAR_GPIO_GRP_FID(x)			((x) & (~BITS_GPIO_GRP_FID))
#define BIT_GET_GPIO_GRP_FID(x)			(((x) >> BIT_SHIFT_GPIO_GRP_FID) & BIT_MASK_GPIO_GRP_FID)
#define BIT_SET_GPIO_GRP_FID(x, v)			(BIT_CLEAR_GPIO_GRP_FID(x) | BIT_GPIO_GRP_FID(v))

#define BIT_SHIFT_GPIO_GRP_IDX				0
#define BIT_MASK_GPIO_GRP_IDX				0xff
#define BIT_GPIO_GRP_IDX(x)				(((x) & BIT_MASK_GPIO_GRP_IDX) << BIT_SHIFT_GPIO_GRP_IDX)
#define BITS_GPIO_GRP_IDX				(BIT_MASK_GPIO_GRP_IDX << BIT_SHIFT_GPIO_GRP_IDX)
#define BIT_CLEAR_GPIO_GRP_IDX(x)			((x) & (~BITS_GPIO_GRP_IDX))
#define BIT_GET_GPIO_GRP_IDX(x)			(((x) >> BIT_SHIFT_GPIO_GRP_IDX) & BIT_MASK_GPIO_GRP_IDX)
#define BIT_SET_GPIO_GRP_IDX(x, v)			(BIT_CLEAR_GPIO_GRP_IDX(x) | BIT_GPIO_GRP_IDX(v))

/* 2 REG_GPIO_0				(Offset 0x10D0) */

#define BIT_GPIOA3_PD					BIT(30)
#define BIT_GPIOA3_PU					BIT(29)

#define BIT_SHIFT_GPIOA3_FID				24
#define BIT_MASK_GPIOA3_FID				0x1f
#define BIT_GPIOA3_FID(x)				(((x) & BIT_MASK_GPIOA3_FID) << BIT_SHIFT_GPIOA3_FID)
#define BITS_GPIOA3_FID				(BIT_MASK_GPIOA3_FID << BIT_SHIFT_GPIOA3_FID)
#define BIT_CLEAR_GPIOA3_FID(x)			((x) & (~BITS_GPIOA3_FID))
#define BIT_GET_GPIOA3_FID(x)				(((x) >> BIT_SHIFT_GPIOA3_FID) & BIT_MASK_GPIOA3_FID)
#define BIT_SET_GPIOA3_FID(x, v)			(BIT_CLEAR_GPIOA3_FID(x) | BIT_GPIOA3_FID(v))

#define BIT_GPIOA2_PD					BIT(22)
#define BIT_GPIOA2_PU					BIT(21)

#define BIT_SHIFT_GPIOA2_FID				16
#define BIT_MASK_GPIOA2_FID				0x1f
#define BIT_GPIOA2_FID(x)				(((x) & BIT_MASK_GPIOA2_FID) << BIT_SHIFT_GPIOA2_FID)
#define BITS_GPIOA2_FID				(BIT_MASK_GPIOA2_FID << BIT_SHIFT_GPIOA2_FID)
#define BIT_CLEAR_GPIOA2_FID(x)			((x) & (~BITS_GPIOA2_FID))
#define BIT_GET_GPIOA2_FID(x)				(((x) >> BIT_SHIFT_GPIOA2_FID) & BIT_MASK_GPIOA2_FID)
#define BIT_SET_GPIOA2_FID(x, v)			(BIT_CLEAR_GPIOA2_FID(x) | BIT_GPIOA2_FID(v))

#define BIT_GPIOA1_PD					BIT(14)
#define BIT_GPIOA1_PU					BIT(13)

#define BIT_SHIFT_GPIOA1_FID				8
#define BIT_MASK_GPIOA1_FID				0x1f
#define BIT_GPIOA1_FID(x)				(((x) & BIT_MASK_GPIOA1_FID) << BIT_SHIFT_GPIOA1_FID)
#define BITS_GPIOA1_FID				(BIT_MASK_GPIOA1_FID << BIT_SHIFT_GPIOA1_FID)
#define BIT_CLEAR_GPIOA1_FID(x)			((x) & (~BITS_GPIOA1_FID))
#define BIT_GET_GPIOA1_FID(x)				(((x) >> BIT_SHIFT_GPIOA1_FID) & BIT_MASK_GPIOA1_FID)
#define BIT_SET_GPIOA1_FID(x, v)			(BIT_CLEAR_GPIOA1_FID(x) | BIT_GPIOA1_FID(v))

#define BIT_GPIOA0_PD					BIT(6)
#define BIT_GPIOA0_PU					BIT(5)

#define BIT_SHIFT_GPIOA0_FID				0
#define BIT_MASK_GPIOA0_FID				0x1f
#define BIT_GPIOA0_FID(x)				(((x) & BIT_MASK_GPIOA0_FID) << BIT_SHIFT_GPIOA0_FID)
#define BITS_GPIOA0_FID				(BIT_MASK_GPIOA0_FID << BIT_SHIFT_GPIOA0_FID)
#define BIT_CLEAR_GPIOA0_FID(x)			((x) & (~BITS_GPIOA0_FID))
#define BIT_GET_GPIOA0_FID(x)				(((x) >> BIT_SHIFT_GPIOA0_FID) & BIT_MASK_GPIOA0_FID)
#define BIT_SET_GPIOA0_FID(x, v)			(BIT_CLEAR_GPIOA0_FID(x) | BIT_GPIOA0_FID(v))

/* 2 REG_GPIO_1				(Offset 0x10D4) */

#define BIT_GPIOA7_PD					BIT(30)
#define BIT_GPIOA7_PU					BIT(29)

#define BIT_SHIFT_GPIOA7_FID				24
#define BIT_MASK_GPIOA7_FID				0x1f
#define BIT_GPIOA7_FID(x)				(((x) & BIT_MASK_GPIOA7_FID) << BIT_SHIFT_GPIOA7_FID)
#define BITS_GPIOA7_FID				(BIT_MASK_GPIOA7_FID << BIT_SHIFT_GPIOA7_FID)
#define BIT_CLEAR_GPIOA7_FID(x)			((x) & (~BITS_GPIOA7_FID))
#define BIT_GET_GPIOA7_FID(x)				(((x) >> BIT_SHIFT_GPIOA7_FID) & BIT_MASK_GPIOA7_FID)
#define BIT_SET_GPIOA7_FID(x, v)			(BIT_CLEAR_GPIOA7_FID(x) | BIT_GPIOA7_FID(v))

#define BIT_GPIOA6_PD					BIT(22)
#define BIT_GPIOA6_PU					BIT(21)

#define BIT_SHIFT_GPIOA6_FID				16
#define BIT_MASK_GPIOA6_FID				0x1f
#define BIT_GPIOA6_FID(x)				(((x) & BIT_MASK_GPIOA6_FID) << BIT_SHIFT_GPIOA6_FID)
#define BITS_GPIOA6_FID				(BIT_MASK_GPIOA6_FID << BIT_SHIFT_GPIOA6_FID)
#define BIT_CLEAR_GPIOA6_FID(x)			((x) & (~BITS_GPIOA6_FID))
#define BIT_GET_GPIOA6_FID(x)				(((x) >> BIT_SHIFT_GPIOA6_FID) & BIT_MASK_GPIOA6_FID)
#define BIT_SET_GPIOA6_FID(x, v)			(BIT_CLEAR_GPIOA6_FID(x) | BIT_GPIOA6_FID(v))

#define BIT_BIT_GPIOA5_PD				BIT(14)
#define BIT_GPIOA5_PU					BIT(13)

#define BIT_SHIFT_GPIOA5_FID				8
#define BIT_MASK_GPIOA5_FID				0x1f
#define BIT_GPIOA5_FID(x)				(((x) & BIT_MASK_GPIOA5_FID) << BIT_SHIFT_GPIOA5_FID)
#define BITS_GPIOA5_FID				(BIT_MASK_GPIOA5_FID << BIT_SHIFT_GPIOA5_FID)
#define BIT_CLEAR_GPIOA5_FID(x)			((x) & (~BITS_GPIOA5_FID))
#define BIT_GET_GPIOA5_FID(x)				(((x) >> BIT_SHIFT_GPIOA5_FID) & BIT_MASK_GPIOA5_FID)
#define BIT_SET_GPIOA5_FID(x, v)			(BIT_CLEAR_GPIOA5_FID(x) | BIT_GPIOA5_FID(v))

#define BIT_GPIOA4_PD					BIT(6)
#define BIT_GPIOA4_PU					BIT(5)

#define BIT_SHIFT_GPIOA4_FID				0
#define BIT_MASK_GPIOA4_FID				0x1f
#define BIT_GPIOA4_FID(x)				(((x) & BIT_MASK_GPIOA4_FID) << BIT_SHIFT_GPIOA4_FID)
#define BITS_GPIOA4_FID				(BIT_MASK_GPIOA4_FID << BIT_SHIFT_GPIOA4_FID)
#define BIT_CLEAR_GPIOA4_FID(x)			((x) & (~BITS_GPIOA4_FID))
#define BIT_GET_GPIOA4_FID(x)				(((x) >> BIT_SHIFT_GPIOA4_FID) & BIT_MASK_GPIOA4_FID)
#define BIT_SET_GPIOA4_FID(x, v)			(BIT_CLEAR_GPIOA4_FID(x) | BIT_GPIOA4_FID(v))

/* 2 REG_GPIO_2				(Offset 0x10D8) */

#define BIT_GPIOA11_PD					BIT(30)
#define BIT_GPIOA11_PU					BIT(29)

#define BIT_SHIFT_GPIOA11_FID				24
#define BIT_MASK_GPIOA11_FID				0x1f
#define BIT_GPIOA11_FID(x)				(((x) & BIT_MASK_GPIOA11_FID) << BIT_SHIFT_GPIOA11_FID)
#define BITS_GPIOA11_FID				(BIT_MASK_GPIOA11_FID << BIT_SHIFT_GPIOA11_FID)
#define BIT_CLEAR_GPIOA11_FID(x)			((x) & (~BITS_GPIOA11_FID))
#define BIT_GET_GPIOA11_FID(x)				(((x) >> BIT_SHIFT_GPIOA11_FID) & BIT_MASK_GPIOA11_FID)
#define BIT_SET_GPIOA11_FID(x, v)			(BIT_CLEAR_GPIOA11_FID(x) | BIT_GPIOA11_FID(v))

#define BIT_GPIOA10_PD					BIT(22)
#define BIT_GPIOA10_PU					BIT(21)

#define BIT_SHIFT_GPIOA10_FID				16
#define BIT_MASK_GPIOA10_FID				0x1f
#define BIT_GPIOA10_FID(x)				(((x) & BIT_MASK_GPIOA10_FID) << BIT_SHIFT_GPIOA10_FID)
#define BITS_GPIOA10_FID				(BIT_MASK_GPIOA10_FID << BIT_SHIFT_GPIOA10_FID)
#define BIT_CLEAR_GPIOA10_FID(x)			((x) & (~BITS_GPIOA10_FID))
#define BIT_GET_GPIOA10_FID(x)				(((x) >> BIT_SHIFT_GPIOA10_FID) & BIT_MASK_GPIOA10_FID)
#define BIT_SET_GPIOA10_FID(x, v)			(BIT_CLEAR_GPIOA10_FID(x) | BIT_GPIOA10_FID(v))

#define BIT_GPIOA9_PD					BIT(14)
#define BIT_GPIOA9_PU					BIT(13)

#define BIT_SHIFT_GPIOA9_FID				8
#define BIT_MASK_GPIOA9_FID				0x1f
#define BIT_GPIOA9_FID(x)				(((x) & BIT_MASK_GPIOA9_FID) << BIT_SHIFT_GPIOA9_FID)
#define BITS_GPIOA9_FID				(BIT_MASK_GPIOA9_FID << BIT_SHIFT_GPIOA9_FID)
#define BIT_CLEAR_GPIOA9_FID(x)			((x) & (~BITS_GPIOA9_FID))
#define BIT_GET_GPIOA9_FID(x)				(((x) >> BIT_SHIFT_GPIOA9_FID) & BIT_MASK_GPIOA9_FID)
#define BIT_SET_GPIOA9_FID(x, v)			(BIT_CLEAR_GPIOA9_FID(x) | BIT_GPIOA9_FID(v))

#define BIT_GPIOA8_PD					BIT(6)
#define BIT_GPIOA8_PU					BIT(5)

#define BIT_SHIFT_GPIOA8_FID				0
#define BIT_MASK_GPIOA8_FID				0x1f
#define BIT_GPIOA8_FID(x)				(((x) & BIT_MASK_GPIOA8_FID) << BIT_SHIFT_GPIOA8_FID)
#define BITS_GPIOA8_FID				(BIT_MASK_GPIOA8_FID << BIT_SHIFT_GPIOA8_FID)
#define BIT_CLEAR_GPIOA8_FID(x)			((x) & (~BITS_GPIOA8_FID))
#define BIT_GET_GPIOA8_FID(x)				(((x) >> BIT_SHIFT_GPIOA8_FID) & BIT_MASK_GPIOA8_FID)
#define BIT_SET_GPIOA8_FID(x, v)			(BIT_CLEAR_GPIOA8_FID(x) | BIT_GPIOA8_FID(v))

/* 2 REG_GPIO_3				(Offset 0x10DC) */

#define BIT_GPIOA15_PD					BIT(30)
#define BIT_GPIOA15_PU					BIT(29)

#define BIT_SHIFT_GPIOA15_FID				24
#define BIT_MASK_GPIOA15_FID				0x1f
#define BIT_GPIOA15_FID(x)				(((x) & BIT_MASK_GPIOA15_FID) << BIT_SHIFT_GPIOA15_FID)
#define BITS_GPIOA15_FID				(BIT_MASK_GPIOA15_FID << BIT_SHIFT_GPIOA15_FID)
#define BIT_CLEAR_GPIOA15_FID(x)			((x) & (~BITS_GPIOA15_FID))
#define BIT_GET_GPIOA15_FID(x)				(((x) >> BIT_SHIFT_GPIOA15_FID) & BIT_MASK_GPIOA15_FID)
#define BIT_SET_GPIOA15_FID(x, v)			(BIT_CLEAR_GPIOA15_FID(x) | BIT_GPIOA15_FID(v))

#define BIT_GPIOA14_PD					BIT(22)
#define BIT_GPIOA14_PU					BIT(21)

#define BIT_SHIFT_GPIOA14_FID				16
#define BIT_MASK_GPIOA14_FID				0x1f
#define BIT_GPIOA14_FID(x)				(((x) & BIT_MASK_GPIOA14_FID) << BIT_SHIFT_GPIOA14_FID)
#define BITS_GPIOA14_FID				(BIT_MASK_GPIOA14_FID << BIT_SHIFT_GPIOA14_FID)
#define BIT_CLEAR_GPIOA14_FID(x)			((x) & (~BITS_GPIOA14_FID))
#define BIT_GET_GPIOA14_FID(x)				(((x) >> BIT_SHIFT_GPIOA14_FID) & BIT_MASK_GPIOA14_FID)
#define BIT_SET_GPIOA14_FID(x, v)			(BIT_CLEAR_GPIOA14_FID(x) | BIT_GPIOA14_FID(v))

#define BIT_GPIOA13_PD					BIT(14)
#define BIT_GPIOA13_PU					BIT(13)

#define BIT_SHIFT_GPIOA13_FID				8
#define BIT_MASK_GPIOA13_FID				0x1f
#define BIT_GPIOA13_FID(x)				(((x) & BIT_MASK_GPIOA13_FID) << BIT_SHIFT_GPIOA13_FID)
#define BITS_GPIOA13_FID				(BIT_MASK_GPIOA13_FID << BIT_SHIFT_GPIOA13_FID)
#define BIT_CLEAR_GPIOA13_FID(x)			((x) & (~BITS_GPIOA13_FID))
#define BIT_GET_GPIOA13_FID(x)				(((x) >> BIT_SHIFT_GPIOA13_FID) & BIT_MASK_GPIOA13_FID)
#define BIT_SET_GPIOA13_FID(x, v)			(BIT_CLEAR_GPIOA13_FID(x) | BIT_GPIOA13_FID(v))

#define BIT_GPIOA12_PD					BIT(6)
#define BIT_GPIOA12_PU					BIT(5)

#define BIT_SHIFT_GPIOA12_FID				0
#define BIT_MASK_GPIOA12_FID				0x1f
#define BIT_GPIOA12_FID(x)				(((x) & BIT_MASK_GPIOA12_FID) << BIT_SHIFT_GPIOA12_FID)
#define BITS_GPIOA12_FID				(BIT_MASK_GPIOA12_FID << BIT_SHIFT_GPIOA12_FID)
#define BIT_CLEAR_GPIOA12_FID(x)			((x) & (~BITS_GPIOA12_FID))
#define BIT_GET_GPIOA12_FID(x)				(((x) >> BIT_SHIFT_GPIOA12_FID) & BIT_MASK_GPIOA12_FID)
#define BIT_SET_GPIOA12_FID(x, v)			(BIT_CLEAR_GPIOA12_FID(x) | BIT_GPIOA12_FID(v))

/* 2 REG_GPIO_4				(Offset 0x10E0) */

#define BIT_GPIOB3_SHDN				BIT(31)
#define BIT_GPIOB3_PD					BIT(30)
#define BIT_GPIOB3_PU					BIT(29)

#define BIT_SHIFT_GPIOB3_FID				24
#define BIT_MASK_GPIOB3_FID				0x1f
#define BIT_GPIOB3_FID(x)				(((x) & BIT_MASK_GPIOB3_FID) << BIT_SHIFT_GPIOB3_FID)
#define BITS_GPIOB3_FID				(BIT_MASK_GPIOB3_FID << BIT_SHIFT_GPIOB3_FID)
#define BIT_CLEAR_GPIOB3_FID(x)			((x) & (~BITS_GPIOB3_FID))
#define BIT_GET_GPIOB3_FID(x)				(((x) >> BIT_SHIFT_GPIOB3_FID) & BIT_MASK_GPIOB3_FID)
#define BIT_SET_GPIOB3_FID(x, v)			(BIT_CLEAR_GPIOB3_FID(x) | BIT_GPIOB3_FID(v))

#define BIT_GPIOB2_SHDN				BIT(23)
#define BIT_GPIOB2_PD					BIT(22)
#define BIT_GPIOB2_PU					BIT(21)

#define BIT_SHIFT_GPIOB2_FID				16
#define BIT_MASK_GPIOB2_FID				0x1f
#define BIT_GPIOB2_FID(x)				(((x) & BIT_MASK_GPIOB2_FID) << BIT_SHIFT_GPIOB2_FID)
#define BITS_GPIOB2_FID				(BIT_MASK_GPIOB2_FID << BIT_SHIFT_GPIOB2_FID)
#define BIT_CLEAR_GPIOB2_FID(x)			((x) & (~BITS_GPIOB2_FID))
#define BIT_GET_GPIOB2_FID(x)				(((x) >> BIT_SHIFT_GPIOB2_FID) & BIT_MASK_GPIOB2_FID)
#define BIT_SET_GPIOB2_FID(x, v)			(BIT_CLEAR_GPIOB2_FID(x) | BIT_GPIOB2_FID(v))

#define BIT_GPIOB1_SHDN				BIT(15)
#define BIT_GPIOB1_PD					BIT(14)
#define BIT_GPIOB1_PU					BIT(13)

#define BIT_SHIFT_GPIOB1_FID				8
#define BIT_MASK_GPIOB1_FID				0x1f
#define BIT_GPIOB1_FID(x)				(((x) & BIT_MASK_GPIOB1_FID) << BIT_SHIFT_GPIOB1_FID)
#define BITS_GPIOB1_FID				(BIT_MASK_GPIOB1_FID << BIT_SHIFT_GPIOB1_FID)
#define BIT_CLEAR_GPIOB1_FID(x)			((x) & (~BITS_GPIOB1_FID))
#define BIT_GET_GPIOB1_FID(x)				(((x) >> BIT_SHIFT_GPIOB1_FID) & BIT_MASK_GPIOB1_FID)
#define BIT_SET_GPIOB1_FID(x, v)			(BIT_CLEAR_GPIOB1_FID(x) | BIT_GPIOB1_FID(v))

#define BIT_GPIOB0_SHDN				BIT(7)
#define BIT_GPIOB0_PD					BIT(6)
#define BIT_GPIOB0_PU					BIT(5)

#define BIT_SHIFT_GPIOB0_FID				0
#define BIT_MASK_GPIOB0_FID				0x1f
#define BIT_GPIOB0_FID(x)				(((x) & BIT_MASK_GPIOB0_FID) << BIT_SHIFT_GPIOB0_FID)
#define BITS_GPIOB0_FID				(BIT_MASK_GPIOB0_FID << BIT_SHIFT_GPIOB0_FID)
#define BIT_CLEAR_GPIOB0_FID(x)			((x) & (~BITS_GPIOB0_FID))
#define BIT_GET_GPIOB0_FID(x)				(((x) >> BIT_SHIFT_GPIOB0_FID) & BIT_MASK_GPIOB0_FID)
#define BIT_SET_GPIOB0_FID(x, v)			(BIT_CLEAR_GPIOB0_FID(x) | BIT_GPIOB0_FID(v))

/* 2 REG_GPIO_5				(Offset 0x10E4) */

#define BIT_MEM_HV_ROM_TEST1				BIT(29)
#define BIT_MEM_USB_SD					BIT(29)
#define BIT_MEM_HV_ROM_RME				BIT(28)
#define BIT_MEM_USB_DS					BIT(28)
#define BIT_MEM_USB_LS					BIT(27)
#define BIT_MEM_BTOFF_SD				BIT(26)
#define BIT_MEM_BTOFF_DS				BIT(25)

#define BIT_SHIFT_MEM_HV_ROM_RM			24
#define BIT_MASK_MEM_HV_ROM_RM				0xf
#define BIT_MEM_HV_ROM_RM(x)				(((x) & BIT_MASK_MEM_HV_ROM_RM) << BIT_SHIFT_MEM_HV_ROM_RM)
#define BITS_MEM_HV_ROM_RM				(BIT_MASK_MEM_HV_ROM_RM << BIT_SHIFT_MEM_HV_ROM_RM)
#define BIT_CLEAR_MEM_HV_ROM_RM(x)			((x) & (~BITS_MEM_HV_ROM_RM))
#define BIT_GET_MEM_HV_ROM_RM(x)			(((x) >> BIT_SHIFT_MEM_HV_ROM_RM) & BIT_MASK_MEM_HV_ROM_RM)
#define BIT_SET_MEM_HV_ROM_RM(x, v)			(BIT_CLEAR_MEM_HV_ROM_RM(x) | BIT_MEM_HV_ROM_RM(v))

#define BIT_MEM_BTOFF_LS				BIT(24)
#define BIT_MEM_HV_2PRF1_TEST1B			BIT(23)
#define BIT_MEM_HV_2PRF1_TEST1A			BIT(22)

#define BIT_SHIFT_MEM_WPON_E0_GRP_EN			22
#define BIT_MASK_MEM_WPON_E0_GRP_EN			0x3f
#define BIT_MEM_WPON_E0_GRP_EN(x)			(((x) & BIT_MASK_MEM_WPON_E0_GRP_EN) << BIT_SHIFT_MEM_WPON_E0_GRP_EN)
#define BITS_MEM_WPON_E0_GRP_EN			(BIT_MASK_MEM_WPON_E0_GRP_EN << BIT_SHIFT_MEM_WPON_E0_GRP_EN)
#define BIT_CLEAR_MEM_WPON_E0_GRP_EN(x)		((x) & (~BITS_MEM_WPON_E0_GRP_EN))
#define BIT_GET_MEM_WPON_E0_GRP_EN(x)			(((x) >> BIT_SHIFT_MEM_WPON_E0_GRP_EN) & BIT_MASK_MEM_WPON_E0_GRP_EN)
#define BIT_SET_MEM_WPON_E0_GRP_EN(x, v)		(BIT_CLEAR_MEM_WPON_E0_GRP_EN(x) | BIT_MEM_WPON_E0_GRP_EN(v))

#define BIT_MEM_HV_1PSR_TEST1				BIT(21)
#define BIT_MEM_HV_2PRF0_TEST1B			BIT(21)
#define BIT_MEM_HV_1PSR_RME				BIT(20)
#define BIT_MEM_HV_2PRF0_TEST1A			BIT(20)
#define BIT_MEM_HV_2PRF1_RMEB				BIT(19)
#define BIT_MEM_HV_2PRF1_RMEA				BIT(18)

#define BIT_SHIFT_MEM_WPOFF_E3_GRP_EN			18
#define BIT_MASK_MEM_WPOFF_E3_GRP_EN			0xf
#define BIT_MEM_WPOFF_E3_GRP_EN(x)			(((x) & BIT_MASK_MEM_WPOFF_E3_GRP_EN) << BIT_SHIFT_MEM_WPOFF_E3_GRP_EN)
#define BITS_MEM_WPOFF_E3_GRP_EN			(BIT_MASK_MEM_WPOFF_E3_GRP_EN << BIT_SHIFT_MEM_WPOFF_E3_GRP_EN)
#define BIT_CLEAR_MEM_WPOFF_E3_GRP_EN(x)		((x) & (~BITS_MEM_WPOFF_E3_GRP_EN))
#define BIT_GET_MEM_WPOFF_E3_GRP_EN(x)			(((x) >> BIT_SHIFT_MEM_WPOFF_E3_GRP_EN) & BIT_MASK_MEM_WPOFF_E3_GRP_EN)
#define BIT_SET_MEM_WPOFF_E3_GRP_EN(x, v)		(BIT_CLEAR_MEM_WPOFF_E3_GRP_EN(x) | BIT_MEM_WPOFF_E3_GRP_EN(v))

#define BIT_MEM_HV_2PRF0_RMEB				BIT(17)

#define BIT_SHIFT_MEM_HV_1PSR_RM			16
#define BIT_MASK_MEM_HV_1PSR_RM			0xf
#define BIT_MEM_HV_1PSR_RM(x)				(((x) & BIT_MASK_MEM_HV_1PSR_RM) << BIT_SHIFT_MEM_HV_1PSR_RM)
#define BITS_MEM_HV_1PSR_RM				(BIT_MASK_MEM_HV_1PSR_RM << BIT_SHIFT_MEM_HV_1PSR_RM)
#define BIT_CLEAR_MEM_HV_1PSR_RM(x)			((x) & (~BITS_MEM_HV_1PSR_RM))
#define BIT_GET_MEM_HV_1PSR_RM(x)			(((x) >> BIT_SHIFT_MEM_HV_1PSR_RM) & BIT_MASK_MEM_HV_1PSR_RM)
#define BIT_SET_MEM_HV_1PSR_RM(x, v)			(BIT_CLEAR_MEM_HV_1PSR_RM(x) | BIT_MEM_HV_1PSR_RM(v))

#define BIT_MEM_HV_2PRF0_RMEA				BIT(16)
#define BIT_GPIOB5_SHDN				BIT(15)
#define BIT_GPIOB5_PD					BIT(14)
#define BIT_GPIOB5_PU					BIT(13)
#define BIT_MEM_HV_1PRF1_TEST1				BIT(13)
#define BIT_MEM_HV_1PRF1_RME				BIT(12)

#define BIT_SHIFT_MEM_HV_2PRF1_RMB			12
#define BIT_MASK_MEM_HV_2PRF1_RMB			0xf
#define BIT_MEM_HV_2PRF1_RMB(x)			(((x) & BIT_MASK_MEM_HV_2PRF1_RMB) << BIT_SHIFT_MEM_HV_2PRF1_RMB)
#define BITS_MEM_HV_2PRF1_RMB				(BIT_MASK_MEM_HV_2PRF1_RMB << BIT_SHIFT_MEM_HV_2PRF1_RMB)
#define BIT_CLEAR_MEM_HV_2PRF1_RMB(x)			((x) & (~BITS_MEM_HV_2PRF1_RMB))
#define BIT_GET_MEM_HV_2PRF1_RMB(x)			(((x) >> BIT_SHIFT_MEM_HV_2PRF1_RMB) & BIT_MASK_MEM_HV_2PRF1_RMB)
#define BIT_SET_MEM_HV_2PRF1_RMB(x, v)			(BIT_CLEAR_MEM_HV_2PRF1_RMB(x) | BIT_MEM_HV_2PRF1_RMB(v))

#define BIT_SHIFT_GPIOB5_FID				8
#define BIT_MASK_GPIOB5_FID				0x1f
#define BIT_GPIOB5_FID(x)				(((x) & BIT_MASK_GPIOB5_FID) << BIT_SHIFT_GPIOB5_FID)
#define BITS_GPIOB5_FID				(BIT_MASK_GPIOB5_FID << BIT_SHIFT_GPIOB5_FID)
#define BIT_CLEAR_GPIOB5_FID(x)			((x) & (~BITS_GPIOB5_FID))
#define BIT_GET_GPIOB5_FID(x)				(((x) >> BIT_SHIFT_GPIOB5_FID) & BIT_MASK_GPIOB5_FID)
#define BIT_SET_GPIOB5_FID(x, v)			(BIT_CLEAR_GPIOB5_FID(x) | BIT_GPIOB5_FID(v))

#define BIT_SHIFT_MEM_HV_1PRF1_RM			8
#define BIT_MASK_MEM_HV_1PRF1_RM			0xf
#define BIT_MEM_HV_1PRF1_RM(x)				(((x) & BIT_MASK_MEM_HV_1PRF1_RM) << BIT_SHIFT_MEM_HV_1PRF1_RM)
#define BITS_MEM_HV_1PRF1_RM				(BIT_MASK_MEM_HV_1PRF1_RM << BIT_SHIFT_MEM_HV_1PRF1_RM)
#define BIT_CLEAR_MEM_HV_1PRF1_RM(x)			((x) & (~BITS_MEM_HV_1PRF1_RM))
#define BIT_GET_MEM_HV_1PRF1_RM(x)			(((x) >> BIT_SHIFT_MEM_HV_1PRF1_RM) & BIT_MASK_MEM_HV_1PRF1_RM)
#define BIT_SET_MEM_HV_1PRF1_RM(x, v)			(BIT_CLEAR_MEM_HV_1PRF1_RM(x) | BIT_MEM_HV_1PRF1_RM(v))

#define BIT_SHIFT_MEM_HV_2PRF1_RMA			8
#define BIT_MASK_MEM_HV_2PRF1_RMA			0xf
#define BIT_MEM_HV_2PRF1_RMA(x)			(((x) & BIT_MASK_MEM_HV_2PRF1_RMA) << BIT_SHIFT_MEM_HV_2PRF1_RMA)
#define BITS_MEM_HV_2PRF1_RMA				(BIT_MASK_MEM_HV_2PRF1_RMA << BIT_SHIFT_MEM_HV_2PRF1_RMA)
#define BIT_CLEAR_MEM_HV_2PRF1_RMA(x)			((x) & (~BITS_MEM_HV_2PRF1_RMA))
#define BIT_GET_MEM_HV_2PRF1_RMA(x)			(((x) >> BIT_SHIFT_MEM_HV_2PRF1_RMA) & BIT_MASK_MEM_HV_2PRF1_RMA)
#define BIT_SET_MEM_HV_2PRF1_RMA(x, v)			(BIT_CLEAR_MEM_HV_2PRF1_RMA(x) | BIT_MEM_HV_2PRF1_RMA(v))

#define BIT_SHIFT_MEM_WPOFF_E0_GRP_EN			8
#define BIT_MASK_MEM_WPOFF_E0_GRP_EN			0x3ff
#define BIT_MEM_WPOFF_E0_GRP_EN(x)			(((x) & BIT_MASK_MEM_WPOFF_E0_GRP_EN) << BIT_SHIFT_MEM_WPOFF_E0_GRP_EN)
#define BITS_MEM_WPOFF_E0_GRP_EN			(BIT_MASK_MEM_WPOFF_E0_GRP_EN << BIT_SHIFT_MEM_WPOFF_E0_GRP_EN)
#define BIT_CLEAR_MEM_WPOFF_E0_GRP_EN(x)		((x) & (~BITS_MEM_WPOFF_E0_GRP_EN))
#define BIT_GET_MEM_WPOFF_E0_GRP_EN(x)			(((x) >> BIT_SHIFT_MEM_WPOFF_E0_GRP_EN) & BIT_MASK_MEM_WPOFF_E0_GRP_EN)
#define BIT_SET_MEM_WPOFF_E0_GRP_EN(x, v)		(BIT_CLEAR_MEM_WPOFF_E0_GRP_EN(x) | BIT_MEM_WPOFF_E0_GRP_EN(v))

#define BIT_GPIOB4_SHDN				BIT(7)
#define BIT_GPIOB4_PD					BIT(6)
#define BIT_GPIOB4_PU					BIT(5)
#define BIT_MEM_HV_1PRF0_TEST1				BIT(5)
#define BIT_MEM_HV_1PRF0_RME				BIT(4)

#define BIT_SHIFT_MEM_HV_2PRF0_RMB			4
#define BIT_MASK_MEM_HV_2PRF0_RMB			0xf
#define BIT_MEM_HV_2PRF0_RMB(x)			(((x) & BIT_MASK_MEM_HV_2PRF0_RMB) << BIT_SHIFT_MEM_HV_2PRF0_RMB)
#define BITS_MEM_HV_2PRF0_RMB				(BIT_MASK_MEM_HV_2PRF0_RMB << BIT_SHIFT_MEM_HV_2PRF0_RMB)
#define BIT_CLEAR_MEM_HV_2PRF0_RMB(x)			((x) & (~BITS_MEM_HV_2PRF0_RMB))
#define BIT_GET_MEM_HV_2PRF0_RMB(x)			(((x) >> BIT_SHIFT_MEM_HV_2PRF0_RMB) & BIT_MASK_MEM_HV_2PRF0_RMB)
#define BIT_SET_MEM_HV_2PRF0_RMB(x, v)			(BIT_CLEAR_MEM_HV_2PRF0_RMB(x) | BIT_MEM_HV_2PRF0_RMB(v))

#define BIT_SHIFT_GPIOB4_FID				0
#define BIT_MASK_GPIOB4_FID				0x1f
#define BIT_GPIOB4_FID(x)				(((x) & BIT_MASK_GPIOB4_FID) << BIT_SHIFT_GPIOB4_FID)
#define BITS_GPIOB4_FID				(BIT_MASK_GPIOB4_FID << BIT_SHIFT_GPIOB4_FID)
#define BIT_CLEAR_GPIOB4_FID(x)			((x) & (~BITS_GPIOB4_FID))
#define BIT_GET_GPIOB4_FID(x)				(((x) >> BIT_SHIFT_GPIOB4_FID) & BIT_MASK_GPIOB4_FID)
#define BIT_SET_GPIOB4_FID(x, v)			(BIT_CLEAR_GPIOB4_FID(x) | BIT_GPIOB4_FID(v))

#define BIT_SHIFT_MEM_HV_1PRF0_RM			0
#define BIT_MASK_MEM_HV_1PRF0_RM			0xf
#define BIT_MEM_HV_1PRF0_RM(x)				(((x) & BIT_MASK_MEM_HV_1PRF0_RM) << BIT_SHIFT_MEM_HV_1PRF0_RM)
#define BITS_MEM_HV_1PRF0_RM				(BIT_MASK_MEM_HV_1PRF0_RM << BIT_SHIFT_MEM_HV_1PRF0_RM)
#define BIT_CLEAR_MEM_HV_1PRF0_RM(x)			((x) & (~BITS_MEM_HV_1PRF0_RM))
#define BIT_GET_MEM_HV_1PRF0_RM(x)			(((x) >> BIT_SHIFT_MEM_HV_1PRF0_RM) & BIT_MASK_MEM_HV_1PRF0_RM)
#define BIT_SET_MEM_HV_1PRF0_RM(x, v)			(BIT_CLEAR_MEM_HV_1PRF0_RM(x) | BIT_MEM_HV_1PRF0_RM(v))

#define BIT_SHIFT_MEM_HV_2PRF0_RMA			0
#define BIT_MASK_MEM_HV_2PRF0_RMA			0xf
#define BIT_MEM_HV_2PRF0_RMA(x)			(((x) & BIT_MASK_MEM_HV_2PRF0_RMA) << BIT_SHIFT_MEM_HV_2PRF0_RMA)
#define BITS_MEM_HV_2PRF0_RMA				(BIT_MASK_MEM_HV_2PRF0_RMA << BIT_SHIFT_MEM_HV_2PRF0_RMA)
#define BIT_CLEAR_MEM_HV_2PRF0_RMA(x)			((x) & (~BITS_MEM_HV_2PRF0_RMA))
#define BIT_GET_MEM_HV_2PRF0_RMA(x)			(((x) >> BIT_SHIFT_MEM_HV_2PRF0_RMA) & BIT_MASK_MEM_HV_2PRF0_RMA)
#define BIT_SET_MEM_HV_2PRF0_RMA(x, v)			(BIT_CLEAR_MEM_HV_2PRF0_RMA(x) | BIT_MEM_HV_2PRF0_RMA(v))

#define BIT_SHIFT_MEM_USB_E0_GRP_EN			0
#define BIT_MASK_MEM_USB_E0_GRP_EN			0xff
#define BIT_MEM_USB_E0_GRP_EN(x)			(((x) & BIT_MASK_MEM_USB_E0_GRP_EN) << BIT_SHIFT_MEM_USB_E0_GRP_EN)
#define BITS_MEM_USB_E0_GRP_EN				(BIT_MASK_MEM_USB_E0_GRP_EN << BIT_SHIFT_MEM_USB_E0_GRP_EN)
#define BIT_CLEAR_MEM_USB_E0_GRP_EN(x)			((x) & (~BITS_MEM_USB_E0_GRP_EN))
#define BIT_GET_MEM_USB_E0_GRP_EN(x)			(((x) >> BIT_SHIFT_MEM_USB_E0_GRP_EN) & BIT_MASK_MEM_USB_E0_GRP_EN)
#define BIT_SET_MEM_USB_E0_GRP_EN(x, v)		(BIT_CLEAR_MEM_USB_E0_GRP_EN(x) | BIT_MEM_USB_E0_GRP_EN(v))

#define BIT_SHIFT_MEM_MBIST_CTRL_BT			0
#define BIT_MASK_MEM_MBIST_CTRL_BT			0xffffffffL
#define BIT_MEM_MBIST_CTRL_BT(x)			(((x) & BIT_MASK_MEM_MBIST_CTRL_BT) << BIT_SHIFT_MEM_MBIST_CTRL_BT)
#define BITS_MEM_MBIST_CTRL_BT				(BIT_MASK_MEM_MBIST_CTRL_BT << BIT_SHIFT_MEM_MBIST_CTRL_BT)
#define BIT_CLEAR_MEM_MBIST_CTRL_BT(x)			((x) & (~BITS_MEM_MBIST_CTRL_BT))
#define BIT_GET_MEM_MBIST_CTRL_BT(x)			(((x) >> BIT_SHIFT_MEM_MBIST_CTRL_BT) & BIT_MASK_MEM_MBIST_CTRL_BT)
#define BIT_SET_MEM_MBIST_CTRL_BT(x, v)		(BIT_CLEAR_MEM_MBIST_CTRL_BT(x) | BIT_MEM_MBIST_CTRL_BT(v))

/* 2 REG_CR_EXT				(Offset 0x1100) */

#define BIT_SHIFT_PHY_REQ_DELAY			24
#define BIT_MASK_PHY_REQ_DELAY				0xf
#define BIT_PHY_REQ_DELAY(x)				(((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY)
#define BITS_PHY_REQ_DELAY				(BIT_MASK_PHY_REQ_DELAY << BIT_SHIFT_PHY_REQ_DELAY)
#define BIT_CLEAR_PHY_REQ_DELAY(x)			((x) & (~BITS_PHY_REQ_DELAY))
#define BIT_GET_PHY_REQ_DELAY(x)			(((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY)
#define BIT_SET_PHY_REQ_DELAY(x, v)			(BIT_CLEAR_PHY_REQ_DELAY(x) | BIT_PHY_REQ_DELAY(v))

#define BIT_SHIFT_ROM_BIST_RPT_SEL			8
#define BIT_MASK_ROM_BIST_RPT_SEL			0x7
#define BIT_ROM_BIST_RPT_SEL(x)			(((x) & BIT_MASK_ROM_BIST_RPT_SEL) << BIT_SHIFT_ROM_BIST_RPT_SEL)
#define BITS_ROM_BIST_RPT_SEL				(BIT_MASK_ROM_BIST_RPT_SEL << BIT_SHIFT_ROM_BIST_RPT_SEL)
#define BIT_CLEAR_ROM_BIST_RPT_SEL(x)			((x) & (~BITS_ROM_BIST_RPT_SEL))
#define BIT_GET_ROM_BIST_RPT_SEL(x)			(((x) >> BIT_SHIFT_ROM_BIST_RPT_SEL) & BIT_MASK_ROM_BIST_RPT_SEL)
#define BIT_SET_ROM_BIST_RPT_SEL(x, v)			(BIT_CLEAR_ROM_BIST_RPT_SEL(x) | BIT_ROM_BIST_RPT_SEL(v))

#define BIT_SHIFT_P4_NETSTATE				4
#define BIT_MASK_P4_NETSTATE				0x3
#define BIT_P4_NETSTATE(x)				(((x) & BIT_MASK_P4_NETSTATE) << BIT_SHIFT_P4_NETSTATE)
#define BITS_P4_NETSTATE				(BIT_MASK_P4_NETSTATE << BIT_SHIFT_P4_NETSTATE)
#define BIT_CLEAR_P4_NETSTATE(x)			((x) & (~BITS_P4_NETSTATE))
#define BIT_GET_P4_NETSTATE(x)				(((x) >> BIT_SHIFT_P4_NETSTATE) & BIT_MASK_P4_NETSTATE)
#define BIT_SET_P4_NETSTATE(x, v)			(BIT_CLEAR_P4_NETSTATE(x) | BIT_P4_NETSTATE(v))

#define BIT_SHIFT_P3_NETSTATE				2
#define BIT_MASK_P3_NETSTATE				0x3
#define BIT_P3_NETSTATE(x)				(((x) & BIT_MASK_P3_NETSTATE) << BIT_SHIFT_P3_NETSTATE)
#define BITS_P3_NETSTATE				(BIT_MASK_P3_NETSTATE << BIT_SHIFT_P3_NETSTATE)
#define BIT_CLEAR_P3_NETSTATE(x)			((x) & (~BITS_P3_NETSTATE))
#define BIT_GET_P3_NETSTATE(x)				(((x) >> BIT_SHIFT_P3_NETSTATE) & BIT_MASK_P3_NETSTATE)
#define BIT_SET_P3_NETSTATE(x, v)			(BIT_CLEAR_P3_NETSTATE(x) | BIT_P3_NETSTATE(v))

#define BIT_SHIFT_P2_NETSTATE				0
#define BIT_MASK_P2_NETSTATE				0x3
#define BIT_P2_NETSTATE(x)				(((x) & BIT_MASK_P2_NETSTATE) << BIT_SHIFT_P2_NETSTATE)
#define BITS_P2_NETSTATE				(BIT_MASK_P2_NETSTATE << BIT_SHIFT_P2_NETSTATE)
#define BIT_CLEAR_P2_NETSTATE(x)			((x) & (~BITS_P2_NETSTATE))
#define BIT_GET_P2_NETSTATE(x)				(((x) >> BIT_SHIFT_P2_NETSTATE) & BIT_MASK_P2_NETSTATE)
#define BIT_SET_P2_NETSTATE(x, v)			(BIT_CLEAR_P2_NETSTATE(x) | BIT_P2_NETSTATE(v))

/* 2 REG_XTAL_CLK				(Offset 0x1104) */

#define BIT_SHIFT_R_XTAL_CLK_FREQ			0
#define BIT_MASK_R_XTAL_CLK_FREQ			0x7ffff
#define BIT_R_XTAL_CLK_FREQ(x)				(((x) & BIT_MASK_R_XTAL_CLK_FREQ) << BIT_SHIFT_R_XTAL_CLK_FREQ)
#define BITS_R_XTAL_CLK_FREQ				(BIT_MASK_R_XTAL_CLK_FREQ << BIT_SHIFT_R_XTAL_CLK_FREQ)
#define BIT_CLEAR_R_XTAL_CLK_FREQ(x)			((x) & (~BITS_R_XTAL_CLK_FREQ))
#define BIT_GET_R_XTAL_CLK_FREQ(x)			(((x) >> BIT_SHIFT_R_XTAL_CLK_FREQ) & BIT_MASK_R_XTAL_CLK_FREQ)
#define BIT_SET_R_XTAL_CLK_FREQ(x, v)			(BIT_CLEAR_R_XTAL_CLK_FREQ(x) | BIT_R_XTAL_CLK_FREQ(v))

/* 2 REG_LX_TO_OC				(Offset 0x1108) */

#define BIT_DEV_IDLE					BIT(31)

#define BIT_SHIFT_GUESS_BST_WIDTH			7
#define BIT_MASK_GUESS_BST_WIDTH			0x3f
#define BIT_GUESS_BST_WIDTH(x)				(((x) & BIT_MASK_GUESS_BST_WIDTH) << BIT_SHIFT_GUESS_BST_WIDTH)
#define BITS_GUESS_BST_WIDTH				(BIT_MASK_GUESS_BST_WIDTH << BIT_SHIFT_GUESS_BST_WIDTH)
#define BIT_CLEAR_GUESS_BST_WIDTH(x)			((x) & (~BITS_GUESS_BST_WIDTH))
#define BIT_GET_GUESS_BST_WIDTH(x)			(((x) >> BIT_SHIFT_GUESS_BST_WIDTH) & BIT_MASK_GUESS_BST_WIDTH)
#define BIT_SET_GUESS_BST_WIDTH(x, v)			(BIT_CLEAR_GUESS_BST_WIDTH(x) | BIT_GUESS_BST_WIDTH(v))

#define BIT_SHIFT_CHOP_WIDTH				1
#define BIT_MASK_CHOP_WIDTH				0x3f
#define BIT_CHOP_WIDTH(x)				(((x) & BIT_MASK_CHOP_WIDTH) << BIT_SHIFT_CHOP_WIDTH)
#define BITS_CHOP_WIDTH				(BIT_MASK_CHOP_WIDTH << BIT_SHIFT_CHOP_WIDTH)
#define BIT_CLEAR_CHOP_WIDTH(x)			((x) & (~BITS_CHOP_WIDTH))
#define BIT_GET_CHOP_WIDTH(x)				(((x) >> BIT_SHIFT_CHOP_WIDTH) & BIT_MASK_CHOP_WIDTH)
#define BIT_SET_CHOP_WIDTH(x, v)			(BIT_CLEAR_CHOP_WIDTH(x) | BIT_CHOP_WIDTH(v))

#define BIT_CHOP_EN					BIT(0)

/* 2 REG_FE2IMR				(Offset 0x1120) */

#define BIT__FE3ISR__INT_EN				BIT(29)
#define BIT_FS_ATIM_MB7_INT_EN				BIT(23)
#define BIT_FS_ATIM_MB6_INT_EN				BIT(22)
#define BIT_FS_ATIM_MB5_INT_EN				BIT(21)
#define BIT_FS_ATIM_MB4_INT_EN				BIT(20)
#define BIT_FS_ATIM_MB3_INT_EN				BIT(19)
#define BIT_FS_ATIM_MB2_INT_EN				BIT(18)
#define BIT_FS_ATIM_MB1_INT_EN				BIT(17)
#define BIT_FS_ATIM_MB0_INT_EN				BIT(16)
#define BIT_FS_CTWE_INT_EN				BIT(14)
#define BIT_FS_TBTTALL_INT_EN				BIT(12)
#define BIT_FS_TBTT4INT_EN				BIT(11)
#define BIT_FS_TBTT3INT_EN				BIT(10)
#define BIT_FS_TBTT2INT_EN				BIT(9)
#define BIT_FS_TBTT1INT_EN				BIT(8)
#define BIT_FS_TBTT0_MB7INT_EN				BIT(7)
#define BIT_FS_TBTT0_MB6INT_EN				BIT(6)
#define BIT_FS_TBTT0_MB5INT_EN				BIT(5)
#define BIT_FS_TBTT0_MB4INT_EN				BIT(4)
#define BIT_FS_TBTT0_MB3INT_EN				BIT(3)
#define BIT_FS_TBTT0_MB2INT_EN				BIT(2)
#define BIT_FS_TBTT0_MB1INT_EN				BIT(1)
#define BIT_FS_TBTT0_INT_EN				BIT(0)

/* 2 REG_FE2ISR				(Offset 0x1124) */

#define BIT__FE3ISR__INT				BIT(29)
#define BIT_FS_ATIM_MB7_INT				BIT(23)
#define BIT_FS_ATIM_MB6_INT				BIT(22)
#define BIT_FS_ATIM_MB5_INT				BIT(21)
#define BIT_FS_ATIM_MB4_INT				BIT(20)
#define BIT_FS_ATIM_MB3_INT				BIT(19)
#define BIT_FS_ATIM_MB2_INT				BIT(18)
#define BIT_FS_ATIM_MB1_INT				BIT(17)
#define BIT_FS_ATIM_MB0_INT				BIT(16)
#define BIT_FS_CTWE_INT				BIT(14)
#define BIT_FS_TBTTALL_INT				BIT(12)
#define BIT_FS_TBTT4INT				BIT(11)
#define BIT_FS_TBTT3INT				BIT(10)
#define BIT_FS_TBTT2INT				BIT(9)
#define BIT_FS_TBTT1INT				BIT(8)
#define BIT_FS_TBTT0_MB7INT				BIT(7)
#define BIT_FS_TBTT0_MB6INT				BIT(6)
#define BIT_FS_TBTT0_MB5INT				BIT(5)
#define BIT_FS_TBTT0_MB4INT				BIT(4)
#define BIT_FS_TBTT0_MB3INT				BIT(3)
#define BIT_FS_TBTT0_MB2INT				BIT(2)
#define BIT_FS_TBTT0_MB1INT				BIT(1)
#define BIT_FS_TBTT0_INT				BIT(0)

/* 2 REG_FE3IMR				(Offset 0x1128) */

#define BIT_FS_BCNELY4_AGGR_INT_EN			BIT(31)
#define BIT_FS_BCNELY3_AGGR_INT_EN			BIT(30)
#define BIT_FS_BCNELY2_AGGR_INT_EN			BIT(29)
#define BIT_FS_BCNELY1_AGGR_INT_EN			BIT(28)
#define BIT_FS_BCNDMA4_INT_EN				BIT(27)
#define BIT_FS_BCNDMA3_INT_EN				BIT(26)
#define BIT_FS_BCNDMA2_INT_EN				BIT(25)
#define BIT_FS_BCNDMA1_INT_EN				BIT(24)
#define BIT_FS_BCNDMA0_MB7_INT_EN			BIT(23)
#define BIT_FS_BCNDMA0_MB6_INT_EN			BIT(22)
#define BIT_FS_BCNDMA0_MB5_INT_EN			BIT(21)
#define BIT_FS_BCNDMA0_MB4_INT_EN			BIT(20)
#define BIT_FS_BCNDMA0_MB3_INT_EN			BIT(19)
#define BIT_FS_BCNDMA0_MB2_INT_EN			BIT(18)
#define BIT_FS_BCNDMA0_MB1_INT_EN			BIT(17)
#define BIT_FS_BCNDMA0_INT_EN				BIT(16)
#define BIT_FS_BCNELY0_AGGR_INT_EN			BIT(15)
#define BIT_FS_TSF_SCK_INT_EN				BIT(14)
#define BIT_FS_BCNERLY4_INT_EN				BIT(11)
#define BIT_FS_BCNERLY3_INT_EN				BIT(10)
#define BIT_FS_BCNERLY2_INT_EN				BIT(9)
#define BIT_FS_BCNERLY1_INT_EN				BIT(8)
#define BIT_FS_BCNERLY0_MB7INT_EN			BIT(7)
#define BIT_FS_BCNERLY0_MB6INT_EN			BIT(6)
#define BIT_FS_BCNERLY0_MB5INT_EN			BIT(5)
#define BIT_FS_BCNERLY0_MB4INT_EN			BIT(4)
#define BIT_FS_BCNERLY0_MB3INT_EN			BIT(3)
#define BIT_FS_BCNERLY0_MB2INT_EN			BIT(2)
#define BIT_FS_BCNERLY0_MB1INT_EN			BIT(1)
#define BIT_FS_BCNERLY0_INT_EN				BIT(0)

/* 2 REG_FE3ISR				(Offset 0x112C) */

#define BIT_FS_BCNELY4_AGGR_INT			BIT(31)
#define BIT_FS_BCNELY3_AGGR_INT			BIT(30)
#define BIT_FS_BCNELY2_AGGR_INT			BIT(29)
#define BIT_FS_BCNELY1_AGGR_INT			BIT(28)
#define BIT_FS_BCNDMA4_INT				BIT(27)
#define BIT_FS_BCNDMA3_INT				BIT(26)
#define BIT_FS_BCNDMA2_INT				BIT(25)
#define BIT_FS_BCNDMA1_INT				BIT(24)
#define BIT_FS_BCNDMA0_MB7_INT				BIT(23)
#define BIT_FS_BCNDMA0_MB6_INT				BIT(22)
#define BIT_FS_BCNDMA0_MB5_INT				BIT(21)
#define BIT_FS_BCNDMA0_MB4_INT				BIT(20)
#define BIT_FS_BCNDMA0_MB3_INT				BIT(19)
#define BIT_FS_BCNDMA0_MB2_INT				BIT(18)
#define BIT_FS_BCNDMA0_MB1_INT				BIT(17)
#define BIT_FS_BCNDMA0_INT				BIT(16)
#define BIT_FS_BCNELY0_AGGR_INT			BIT(15)
#define BIT_FS_TSF_SCK_INT				BIT(14)
#define BIT_FS_BCNERLY4_INT				BIT(11)
#define BIT_FS_BCNERLY3_INT				BIT(10)
#define BIT_FS_BCNERLY2_INT				BIT(9)
#define BIT_FS_BCNERLY1_INT				BIT(8)
#define BIT_FS_BCNERLY0_MB7INT				BIT(7)
#define BIT_FS_BCNERLY0_MB6INT				BIT(6)
#define BIT_FS_BCNERLY0_MB5INT				BIT(5)
#define BIT_FS_BCNERLY0_MB4INT				BIT(4)
#define BIT_FS_BCNERLY0_MB3INT				BIT(3)
#define BIT_FS_BCNERLY0_MB2INT				BIT(2)
#define BIT_FS_BCNERLY0_MB1INT				BIT(1)
#define BIT_FS_BCNERLY0_INT				BIT(0)

/* 2 REG_FE4IMR				(Offset 0x1130) */

#define BIT_PORT4_PKTIN_INT_EN				BIT(19)
#define BIT_PORT3_PKTIN_INT_EN				BIT(18)
#define BIT_PORT2_PKTIN_INT_EN				BIT(17)
#define BIT_PORT1_PKTIN_INT_EN				BIT(16)
#define BIT_PORT4_RXUCMD0_OK_INT_EN			BIT(15)
#define BIT_PORT4_RXUCMD1_OK_INT_EN			BIT(14)
#define BIT_PORT4_RXBCMD0_OK_INT_EN			BIT(13)
#define BIT_PORT4_RXBCMD1_OK_INT_EN			BIT(12)
#define BIT_PORT3_RXUCMD0_OK_INT_EN			BIT(11)
#define BIT_PORT3_RXUCMD1_OK_INT_EN			BIT(10)
#define BIT_PORT3_RXBCMD0_OK_INT_EN			BIT(9)
#define BIT_PORT3_RXBCMD1_OK_INT_EN			BIT(8)
#define BIT_PORT2_RXUCMD0_OK_INT_EN			BIT(7)
#define BIT_PORT2_RXUCMD1_OK_INT_EN			BIT(6)
#define BIT_PORT2_RXBCMD0_OK_INT_EN			BIT(5)
#define BIT_PORT2_RXBCMD1_OK_INT_EN			BIT(4)
#define BIT_PORT1_RXUCMD0_OK_INT_EN			BIT(3)
#define BIT_PORT1_RXUCMD1_OK_INT_EN			BIT(2)
#define BIT_PORT1_RXBCMD0_OK_INT_EN			BIT(1)
#define BIT_PORT1_RXBCMD1_OK_INT_EN			BIT(0)

/* 2 REG_FE4ISR				(Offset 0x1134) */

#define BIT_PORT4_PKTIN_INT				BIT(19)
#define BIT_PORT3_PKTIN_INT				BIT(18)
#define BIT_PORT2_PKTIN_INT				BIT(17)
#define BIT_PORT1_PKTIN_INT				BIT(16)
#define BIT_PORT4_RXUCMD0_OK_INT			BIT(15)
#define BIT_PORT4_RXUCMD1_OK_INT			BIT(14)
#define BIT_PORT4_RXBCMD0_OK_INT			BIT(13)
#define BIT_PORT4_RXBCMD1_OK_INT			BIT(12)
#define BIT_PORT3_RXUCMD0_OK_INT			BIT(11)
#define BIT_PORT3_RXUCMD1_OK_INT			BIT(10)
#define BIT_PORT3_RXBCMD0_OK_INT			BIT(9)
#define BIT_PORT3_RXBCMD1_OK_INT			BIT(8)
#define BIT_PORT2_RXUCMD0_OK_INT			BIT(7)
#define BIT_PORT2_RXUCMD1_OK_INT			BIT(6)
#define BIT_PORT2_RXBCMD0_OK_INT			BIT(5)
#define BIT_PORT2_RXBCMD1_OK_INT			BIT(4)
#define BIT_PORT1_RXUCMD0_OK_INT			BIT(3)
#define BIT_PORT1_RXUCMD1_OK_INT			BIT(2)
#define BIT_PORT1_RXBCMD0_OK_INT			BIT(1)
#define BIT_PORT1_RXBCMD1_OK_INT			BIT(0)

/* 2 REG_FT1IMR				(Offset 0x1138) */

#define BIT__FT2ISR__INT_EN				BIT(30)
#define BIT_FTM_PTT_INT_EN				BIT(29)
#define BIT_RXFTMREQ_INT_EN				BIT(28)
#define BIT_RXFTM_INT_EN				BIT(27)
#define BIT_TXFTM_INT_EN				BIT(26)
#define BIT_FS_CTWEND2_INT_EN				BIT(17)
#define BIT_FS_CTWEND1_INT_EN				BIT(16)
#define BIT_FS_CTWEND0_INT_EN				BIT(15)
#define BIT_FS_TX_NULL1_P0_INT_EN			BIT(14)
#define BIT_FS_TX_NULL0_P0_INT_EN			BIT(13)
#define BIT_FS_TSF_BIT32_INT0_EN			BIT(12)
#define BIT_FS_P2P_RFON2_INT_EN			BIT(11)
#define BIT_FS_P2P_RFOFF2_INT_EN			BIT(10)
#define BIT_FS_P2P_RFON1_INT_EN			BIT(9)
#define BIT_FS_P2P_RFOFF1_INT_EN			BIT(8)
#define BIT_FS_P2P_RFON0_INT_EN			BIT(7)
#define BIT_FS_P2P_RFOFF0_INT_EN			BIT(6)
#define BIT_FS_RX_UAPSDMD1_EN				BIT(5)
#define BIT_FS_RX_UAPSDMD0_EN				BIT(4)
#define BIT_FS_TRIGGER_PKT_EN				BIT(3)
#define BIT_FS_EOSP_INT_EN				BIT(2)
#define BIT_FS_RPWM2_INT_EN				BIT(1)
#define BIT_FS_RPWM_INT_EN				BIT(0)

/* 2 REG_FT1ISR				(Offset 0x113C) */

#define BIT__FT2ISR__INT				BIT(30)
#define BIT_FTM_PTT_INT				BIT(29)
#define BIT_RXFTMREQ_INT				BIT(28)
#define BIT_RXFTM_INT					BIT(27)
#define BIT_TXFTM_INT					BIT(26)
#define BIT_FS_CTWEND2_INT				BIT(17)
#define BIT_FS_CTWEND1_INT				BIT(16)
#define BIT_FS_CTWEND0_INT				BIT(15)
#define BIT_FS_TX_NULL1_P0_INT				BIT(14)
#define BIT_FS_TX_NULL0_P0_INT				BIT(13)
#define BIT_FS_TSF_BIT32_INT0				BIT(12)
#define BIT_FS_P2P_RFON2_INT				BIT(11)
#define BIT_FS_P2P_RFOFF2_INT				BIT(10)
#define BIT_FS_P2P_RFON1_INT				BIT(9)
#define BIT_FS_P2P_RFOFF1_INT				BIT(8)
#define BIT_FS_P2P_RFON0_INT				BIT(7)
#define BIT_FS_P2P_RFOFF0_INT				BIT(6)
#define BIT_FS_RX_UAPSDMD1				BIT(5)
#define BIT_FS_RX_UAPSDMD0				BIT(4)
#define BIT_FS_TRIGGER_PKT				BIT(3)
#define BIT_FS_EOSP_INT				BIT(2)
#define BIT_FS_RPWM2_INT				BIT(1)
#define BIT_FS_RPWM_INT				BIT(0)

/* 2 REG_MBIST_DONE				(Offset 0x1140) */

#define BIT_SHIFT_BIST_DONE				0
#define BIT_MASK_BIST_DONE				0xffffffffL
#define BIT_BIST_DONE(x)				(((x) & BIT_MASK_BIST_DONE) << BIT_SHIFT_BIST_DONE)
#define BITS_BIST_DONE					(BIT_MASK_BIST_DONE << BIT_SHIFT_BIST_DONE)
#define BIT_CLEAR_BIST_DONE(x)				((x) & (~BITS_BIST_DONE))
#define BIT_GET_BIST_DONE(x)				(((x) >> BIT_SHIFT_BIST_DONE) & BIT_MASK_BIST_DONE)
#define BIT_SET_BIST_DONE(x, v)			(BIT_CLEAR_BIST_DONE(x) | BIT_BIST_DONE(v))

/* 2 REG_MBIST_FAIL_NRML_L			(Offset 0x1144) */

#define BIT_SHIFT_BIST_FAIL_NRML_L			0
#define BIT_MASK_BIST_FAIL_NRML_L			0xffffffffL
#define BIT_BIST_FAIL_NRML_L(x)			(((x) & BIT_MASK_BIST_FAIL_NRML_L) << BIT_SHIFT_BIST_FAIL_NRML_L)
#define BITS_BIST_FAIL_NRML_L				(BIT_MASK_BIST_FAIL_NRML_L << BIT_SHIFT_BIST_FAIL_NRML_L)
#define BIT_CLEAR_BIST_FAIL_NRML_L(x)			((x) & (~BITS_BIST_FAIL_NRML_L))
#define BIT_GET_BIST_FAIL_NRML_L(x)			(((x) >> BIT_SHIFT_BIST_FAIL_NRML_L) & BIT_MASK_BIST_FAIL_NRML_L)
#define BIT_SET_BIST_FAIL_NRML_L(x, v)			(BIT_CLEAR_BIST_FAIL_NRML_L(x) | BIT_BIST_FAIL_NRML_L(v))

/* 2 REG_MBIST_FAIL_NRML_H			(Offset 0x114C) */

#define BIT_SHIFT_BIST_FAIL_NRML_H			(32 & CPU_OPT_WIDTH)
#define BIT_MASK_BIST_FAIL_NRML_H			0xffffffffL
#define BIT_BIST_FAIL_NRML_H(x)			(((x) & BIT_MASK_BIST_FAIL_NRML_H) << BIT_SHIFT_BIST_FAIL_NRML_H)
#define BITS_BIST_FAIL_NRML_H				(BIT_MASK_BIST_FAIL_NRML_H << BIT_SHIFT_BIST_FAIL_NRML_H)
#define BIT_CLEAR_BIST_FAIL_NRML_H(x)			((x) & (~BITS_BIST_FAIL_NRML_H))
#define BIT_GET_BIST_FAIL_NRML_H(x)			(((x) >> BIT_SHIFT_BIST_FAIL_NRML_H) & BIT_MASK_BIST_FAIL_NRML_H)
#define BIT_SET_BIST_FAIL_NRML_H(x, v)			(BIT_CLEAR_BIST_FAIL_NRML_H(x) | BIT_BIST_FAIL_NRML_H(v))

#define BIT_SHIFT_BIST_FAIL_DRF_L			0
#define BIT_MASK_BIST_FAIL_DRF_L			0xffffffffL
#define BIT_BIST_FAIL_DRF_L(x)				(((x) & BIT_MASK_BIST_FAIL_DRF_L) << BIT_SHIFT_BIST_FAIL_DRF_L)
#define BITS_BIST_FAIL_DRF_L				(BIT_MASK_BIST_FAIL_DRF_L << BIT_SHIFT_BIST_FAIL_DRF_L)
#define BIT_CLEAR_BIST_FAIL_DRF_L(x)			((x) & (~BITS_BIST_FAIL_DRF_L))
#define BIT_GET_BIST_FAIL_DRF_L(x)			(((x) >> BIT_SHIFT_BIST_FAIL_DRF_L) & BIT_MASK_BIST_FAIL_DRF_L)
#define BIT_SET_BIST_FAIL_DRF_L(x, v)			(BIT_CLEAR_BIST_FAIL_DRF_L(x) | BIT_BIST_FAIL_DRF_L(v))

/* 2 REG_MBIST_DRF_FAIL_H			(Offset 0x1154) */

#define BIT_SHIFT_BIST_FAIL_DRF_H			(32 & CPU_OPT_WIDTH)
#define BIT_MASK_BIST_FAIL_DRF_H			0xffffffffL
#define BIT_BIST_FAIL_DRF_H(x)				(((x) & BIT_MASK_BIST_FAIL_DRF_H) << BIT_SHIFT_BIST_FAIL_DRF_H)
#define BITS_BIST_FAIL_DRF_H				(BIT_MASK_BIST_FAIL_DRF_H << BIT_SHIFT_BIST_FAIL_DRF_H)
#define BIT_CLEAR_BIST_FAIL_DRF_H(x)			((x) & (~BITS_BIST_FAIL_DRF_H))
#define BIT_GET_BIST_FAIL_DRF_H(x)			(((x) >> BIT_SHIFT_BIST_FAIL_DRF_H) & BIT_MASK_BIST_FAIL_DRF_H)
#define BIT_SET_BIST_FAIL_DRF_H(x, v)			(BIT_CLEAR_BIST_FAIL_DRF_H(x) | BIT_BIST_FAIL_DRF_H(v))

#define BIT_SHIFT_BIST_START_PAUSE_V1			0
#define BIT_MASK_BIST_START_PAUSE_V1			0xffffffffL
#define BIT_BIST_START_PAUSE_V1(x)			(((x) & BIT_MASK_BIST_START_PAUSE_V1) << BIT_SHIFT_BIST_START_PAUSE_V1)
#define BITS_BIST_START_PAUSE_V1			(BIT_MASK_BIST_START_PAUSE_V1 << BIT_SHIFT_BIST_START_PAUSE_V1)
#define BIT_CLEAR_BIST_START_PAUSE_V1(x)		((x) & (~BITS_BIST_START_PAUSE_V1))
#define BIT_GET_BIST_START_PAUSE_V1(x)			(((x) >> BIT_SHIFT_BIST_START_PAUSE_V1) & BIT_MASK_BIST_START_PAUSE_V1)
#define BIT_SET_BIST_START_PAUSE_V1(x, v)		(BIT_CLEAR_BIST_START_PAUSE_V1(x) | BIT_BIST_START_PAUSE_V1(v))

/* 2 REG_MBIST_RPT				(Offset 0x1158) */

#define BIT_SHIFT_RXBCN_TBTT_ITVL_CLI2			24
#define BIT_MASK_RXBCN_TBTT_ITVL_CLI2			0xff
#define BIT_RXBCN_TBTT_ITVL_CLI2(x)			(((x) & BIT_MASK_RXBCN_TBTT_ITVL_CLI2) << BIT_SHIFT_RXBCN_TBTT_ITVL_CLI2)
#define BITS_RXBCN_TBTT_ITVL_CLI2			(BIT_MASK_RXBCN_TBTT_ITVL_CLI2 << BIT_SHIFT_RXBCN_TBTT_ITVL_CLI2)
#define BIT_CLEAR_RXBCN_TBTT_ITVL_CLI2(x)		((x) & (~BITS_RXBCN_TBTT_ITVL_CLI2))
#define BIT_GET_RXBCN_TBTT_ITVL_CLI2(x)		(((x) >> BIT_SHIFT_RXBCN_TBTT_ITVL_CLI2) & BIT_MASK_RXBCN_TBTT_ITVL_CLI2)
#define BIT_SET_RXBCN_TBTT_ITVL_CLI2(x, v)		(BIT_CLEAR_RXBCN_TBTT_ITVL_CLI2(x) | BIT_RXBCN_TBTT_ITVL_CLI2(v))

#define BIT_SHIFT_RXBCN_TBTT_ITVL_CLI1			16
#define BIT_MASK_RXBCN_TBTT_ITVL_CLI1			0xff
#define BIT_RXBCN_TBTT_ITVL_CLI1(x)			(((x) & BIT_MASK_RXBCN_TBTT_ITVL_CLI1) << BIT_SHIFT_RXBCN_TBTT_ITVL_CLI1)
#define BITS_RXBCN_TBTT_ITVL_CLI1			(BIT_MASK_RXBCN_TBTT_ITVL_CLI1 << BIT_SHIFT_RXBCN_TBTT_ITVL_CLI1)
#define BIT_CLEAR_RXBCN_TBTT_ITVL_CLI1(x)		((x) & (~BITS_RXBCN_TBTT_ITVL_CLI1))
#define BIT_GET_RXBCN_TBTT_ITVL_CLI1(x)		(((x) >> BIT_SHIFT_RXBCN_TBTT_ITVL_CLI1) & BIT_MASK_RXBCN_TBTT_ITVL_CLI1)
#define BIT_SET_RXBCN_TBTT_ITVL_CLI1(x, v)		(BIT_CLEAR_RXBCN_TBTT_ITVL_CLI1(x) | BIT_RXBCN_TBTT_ITVL_CLI1(v))

#define BIT_SHIFT_RXBCN_TBTT_ITVL_CLI0			8
#define BIT_MASK_RXBCN_TBTT_ITVL_CLI0			0xff
#define BIT_RXBCN_TBTT_ITVL_CLI0(x)			(((x) & BIT_MASK_RXBCN_TBTT_ITVL_CLI0) << BIT_SHIFT_RXBCN_TBTT_ITVL_CLI0)
#define BITS_RXBCN_TBTT_ITVL_CLI0			(BIT_MASK_RXBCN_TBTT_ITVL_CLI0 << BIT_SHIFT_RXBCN_TBTT_ITVL_CLI0)
#define BIT_CLEAR_RXBCN_TBTT_ITVL_CLI0(x)		((x) & (~BITS_RXBCN_TBTT_ITVL_CLI0))
#define BIT_GET_RXBCN_TBTT_ITVL_CLI0(x)		(((x) >> BIT_SHIFT_RXBCN_TBTT_ITVL_CLI0) & BIT_MASK_RXBCN_TBTT_ITVL_CLI0)
#define BIT_SET_RXBCN_TBTT_ITVL_CLI0(x, v)		(BIT_CLEAR_RXBCN_TBTT_ITVL_CLI0(x) | BIT_RXBCN_TBTT_ITVL_CLI0(v))

#define BIT_SHIFT_REG_MBIST_BT_RPT			0
#define BIT_MASK_REG_MBIST_BT_RPT			0xffffffffL
#define BIT_REG_MBIST_BT_RPT(x)			(((x) & BIT_MASK_REG_MBIST_BT_RPT) << BIT_SHIFT_REG_MBIST_BT_RPT)
#define BITS_REG_MBIST_BT_RPT				(BIT_MASK_REG_MBIST_BT_RPT << BIT_SHIFT_REG_MBIST_BT_RPT)
#define BIT_CLEAR_REG_MBIST_BT_RPT(x)			((x) & (~BITS_REG_MBIST_BT_RPT))
#define BIT_GET_REG_MBIST_BT_RPT(x)			(((x) >> BIT_SHIFT_REG_MBIST_BT_RPT) & BIT_MASK_REG_MBIST_BT_RPT)
#define BIT_SET_REG_MBIST_BT_RPT(x, v)			(BIT_CLEAR_REG_MBIST_BT_RPT(x) | BIT_REG_MBIST_BT_RPT(v))

#define BIT_SHIFT_WL_ROM_BIST_RPT			0
#define BIT_MASK_WL_ROM_BIST_RPT			0xffffffffL
#define BIT_WL_ROM_BIST_RPT(x)				(((x) & BIT_MASK_WL_ROM_BIST_RPT) << BIT_SHIFT_WL_ROM_BIST_RPT)
#define BITS_WL_ROM_BIST_RPT				(BIT_MASK_WL_ROM_BIST_RPT << BIT_SHIFT_WL_ROM_BIST_RPT)
#define BIT_CLEAR_WL_ROM_BIST_RPT(x)			((x) & (~BITS_WL_ROM_BIST_RPT))
#define BIT_GET_WL_ROM_BIST_RPT(x)			(((x) >> BIT_SHIFT_WL_ROM_BIST_RPT) & BIT_MASK_WL_ROM_BIST_RPT)
#define BIT_SET_WL_ROM_BIST_RPT(x, v)			(BIT_CLEAR_WL_ROM_BIST_RPT(x) | BIT_WL_ROM_BIST_RPT(v))

#define BIT_SHIFT_RXBCN_TBTT_ITVL_P0			0
#define BIT_MASK_RXBCN_TBTT_ITVL_P0			0xff
#define BIT_RXBCN_TBTT_ITVL_P0(x)			(((x) & BIT_MASK_RXBCN_TBTT_ITVL_P0) << BIT_SHIFT_RXBCN_TBTT_ITVL_P0)
#define BITS_RXBCN_TBTT_ITVL_P0			(BIT_MASK_RXBCN_TBTT_ITVL_P0 << BIT_SHIFT_RXBCN_TBTT_ITVL_P0)
#define BIT_CLEAR_RXBCN_TBTT_ITVL_P0(x)		((x) & (~BITS_RXBCN_TBTT_ITVL_P0))
#define BIT_GET_RXBCN_TBTT_ITVL_P0(x)			(((x) >> BIT_SHIFT_RXBCN_TBTT_ITVL_P0) & BIT_MASK_RXBCN_TBTT_ITVL_P0)
#define BIT_SET_RXBCN_TBTT_ITVL_P0(x, v)		(BIT_CLEAR_RXBCN_TBTT_ITVL_P0(x) | BIT_RXBCN_TBTT_ITVL_P0(v))

#define BIT_SHIFT_RXBCN_TBTT_ITVL_CLI3			0
#define BIT_MASK_RXBCN_TBTT_ITVL_CLI3			0xff
#define BIT_RXBCN_TBTT_ITVL_CLI3(x)			(((x) & BIT_MASK_RXBCN_TBTT_ITVL_CLI3) << BIT_SHIFT_RXBCN_TBTT_ITVL_CLI3)
#define BITS_RXBCN_TBTT_ITVL_CLI3			(BIT_MASK_RXBCN_TBTT_ITVL_CLI3 << BIT_SHIFT_RXBCN_TBTT_ITVL_CLI3)
#define BIT_CLEAR_RXBCN_TBTT_ITVL_CLI3(x)		((x) & (~BITS_RXBCN_TBTT_ITVL_CLI3))
#define BIT_GET_RXBCN_TBTT_ITVL_CLI3(x)		(((x) >> BIT_SHIFT_RXBCN_TBTT_ITVL_CLI3) & BIT_MASK_RXBCN_TBTT_ITVL_CLI3)
#define BIT_SET_RXBCN_TBTT_ITVL_CLI3(x, v)		(BIT_CLEAR_RXBCN_TBTT_ITVL_CLI3(x) | BIT_RXBCN_TBTT_ITVL_CLI3(v))

/* 2 REG_BT_MBIST_DONE			(Offset 0x1180) */

#define BIT_SHIFT_BIST_DONE_BT_0			0
#define BIT_MASK_BIST_DONE_BT_0			0xffffffffL
#define BIT_BIST_DONE_BT_0(x)				(((x) & BIT_MASK_BIST_DONE_BT_0) << BIT_SHIFT_BIST_DONE_BT_0)
#define BITS_BIST_DONE_BT_0				(BIT_MASK_BIST_DONE_BT_0 << BIT_SHIFT_BIST_DONE_BT_0)
#define BIT_CLEAR_BIST_DONE_BT_0(x)			((x) & (~BITS_BIST_DONE_BT_0))
#define BIT_GET_BIST_DONE_BT_0(x)			(((x) >> BIT_SHIFT_BIST_DONE_BT_0) & BIT_MASK_BIST_DONE_BT_0)
#define BIT_SET_BIST_DONE_BT_0(x, v)			(BIT_CLEAR_BIST_DONE_BT_0(x) | BIT_BIST_DONE_BT_0(v))

/* 2 REG_BT_MBIST_FAIL			(Offset 0x1184) */

#define BIT_SHIFT_BIST_FAIL_BT_0			9
#define BIT_MASK_BIST_FAIL_BT_0			0x7fffff
#define BIT_BIST_FAIL_BT_0(x)				(((x) & BIT_MASK_BIST_FAIL_BT_0) << BIT_SHIFT_BIST_FAIL_BT_0)
#define BITS_BIST_FAIL_BT_0				(BIT_MASK_BIST_FAIL_BT_0 << BIT_SHIFT_BIST_FAIL_BT_0)
#define BIT_CLEAR_BIST_FAIL_BT_0(x)			((x) & (~BITS_BIST_FAIL_BT_0))
#define BIT_GET_BIST_FAIL_BT_0(x)			(((x) >> BIT_SHIFT_BIST_FAIL_BT_0) & BIT_MASK_BIST_FAIL_BT_0)
#define BIT_SET_BIST_FAIL_BT_0(x, v)			(BIT_CLEAR_BIST_FAIL_BT_0(x) | BIT_BIST_FAIL_BT_0(v))

#define BIT_SHIFT_BIST_DONE_BT_1			0
#define BIT_MASK_BIST_DONE_BT_1			0x1ff
#define BIT_BIST_DONE_BT_1(x)				(((x) & BIT_MASK_BIST_DONE_BT_1) << BIT_SHIFT_BIST_DONE_BT_1)
#define BITS_BIST_DONE_BT_1				(BIT_MASK_BIST_DONE_BT_1 << BIT_SHIFT_BIST_DONE_BT_1)
#define BIT_CLEAR_BIST_DONE_BT_1(x)			((x) & (~BITS_BIST_DONE_BT_1))
#define BIT_GET_BIST_DONE_BT_1(x)			(((x) >> BIT_SHIFT_BIST_DONE_BT_1) & BIT_MASK_BIST_DONE_BT_1)
#define BIT_SET_BIST_DONE_BT_1(x, v)			(BIT_CLEAR_BIST_DONE_BT_1(x) | BIT_BIST_DONE_BT_1(v))

/* 2 REG_BT_MBIST_START_PAUSE		(Offset 0x1188) */

#define BIT_SHIFT_DRF_START_PAUSE_BT_0			18
#define BIT_MASK_DRF_START_PAUSE_BT_0			0x3fff
#define BIT_DRF_START_PAUSE_BT_0(x)			(((x) & BIT_MASK_DRF_START_PAUSE_BT_0) << BIT_SHIFT_DRF_START_PAUSE_BT_0)
#define BITS_DRF_START_PAUSE_BT_0			(BIT_MASK_DRF_START_PAUSE_BT_0 << BIT_SHIFT_DRF_START_PAUSE_BT_0)
#define BIT_CLEAR_DRF_START_PAUSE_BT_0(x)		((x) & (~BITS_DRF_START_PAUSE_BT_0))
#define BIT_GET_DRF_START_PAUSE_BT_0(x)		(((x) >> BIT_SHIFT_DRF_START_PAUSE_BT_0) & BIT_MASK_DRF_START_PAUSE_BT_0)
#define BIT_SET_DRF_START_PAUSE_BT_0(x, v)		(BIT_CLEAR_DRF_START_PAUSE_BT_0(x) | BIT_DRF_START_PAUSE_BT_0(v))

#define BIT_SHIFT_BIST_FAIL_BT_1			0
#define BIT_MASK_BIST_FAIL_BT_1			0x3ffff
#define BIT_BIST_FAIL_BT_1(x)				(((x) & BIT_MASK_BIST_FAIL_BT_1) << BIT_SHIFT_BIST_FAIL_BT_1)
#define BITS_BIST_FAIL_BT_1				(BIT_MASK_BIST_FAIL_BT_1 << BIT_SHIFT_BIST_FAIL_BT_1)
#define BIT_CLEAR_BIST_FAIL_BT_1(x)			((x) & (~BITS_BIST_FAIL_BT_1))
#define BIT_GET_BIST_FAIL_BT_1(x)			(((x) >> BIT_SHIFT_BIST_FAIL_BT_1) & BIT_MASK_BIST_FAIL_BT_1)
#define BIT_SET_BIST_FAIL_BT_1(x, v)			(BIT_CLEAR_BIST_FAIL_BT_1(x) | BIT_BIST_FAIL_BT_1(v))

/* 2 REG_BT_MBIST_START_PAUSE1		(Offset 0x118C) */

#define BIT_SHIFT_DRF_START_PAUSE_BT_1			0
#define BIT_MASK_DRF_START_PAUSE_BT_1			0x7ffffff
#define BIT_DRF_START_PAUSE_BT_1(x)			(((x) & BIT_MASK_DRF_START_PAUSE_BT_1) << BIT_SHIFT_DRF_START_PAUSE_BT_1)
#define BITS_DRF_START_PAUSE_BT_1			(BIT_MASK_DRF_START_PAUSE_BT_1 << BIT_SHIFT_DRF_START_PAUSE_BT_1)
#define BIT_CLEAR_DRF_START_PAUSE_BT_1(x)		((x) & (~BITS_DRF_START_PAUSE_BT_1))
#define BIT_GET_DRF_START_PAUSE_BT_1(x)		(((x) >> BIT_SHIFT_DRF_START_PAUSE_BT_1) & BIT_MASK_DRF_START_PAUSE_BT_1)
#define BIT_SET_DRF_START_PAUSE_BT_1(x, v)		(BIT_CLEAR_DRF_START_PAUSE_BT_1(x) | BIT_DRF_START_PAUSE_BT_1(v))

/* 2 REG_FT2IMR				(Offset 0x11E0) */

#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT_EN		BIT(31)
#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT_EN		BIT(30)
#define BIT_PORT4_TRIPKT_OK_INT_EN			BIT(29)
#define BIT_PORT4_RX_EOSP_OK_INT_EN			BIT(28)
#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT_EN		BIT(27)
#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT_EN		BIT(26)
#define BIT_PORT3_TRIPKT_OK_INT_EN			BIT(25)
#define BIT_PORT3_RX_EOSP_OK_INT_EN			BIT(24)
#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT_EN		BIT(23)
#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT_EN		BIT(22)
#define BIT_PORT2_TRIPKT_OK_INT_EN			BIT(21)
#define BIT_PORT2_RX_EOSP_OK_INT_EN			BIT(20)
#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT_EN		BIT(19)
#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT_EN		BIT(18)
#define BIT_PORT1_TRIPKT_OK_INT_EN			BIT(17)
#define BIT_PORT1_RX_EOSP_OK_INT_EN			BIT(16)
#define BIT_NOA2_TSFT_BIT32_INT_EN			BIT(9)
#define BIT_NOA1_TSFT_BIT32_INT_EN			BIT(8)
#define BIT_PORT4_TX_NULL1_DONE_INT_EN			BIT(7)
#define BIT_PORT4_TX_NULL0_DONE_INT_EN			BIT(6)
#define BIT_PORT3_TX_NULL1_DONE_INT_EN			BIT(5)
#define BIT_PORT3_TX_NULL0_DONE_INT_EN			BIT(4)
#define BIT_PORT2_TX_NULL1_DONE_INT_EN			BIT(3)
#define BIT_PORT2_TX_NULL0_DONE_INT_EN			BIT(2)
#define BIT_PORT1_TX_NULL1_DONE_INT_EN			BIT(1)
#define BIT_PORT1_TX_NULL0_DONE_INT_EN			BIT(0)

/* 2 REG_FT2ISR				(Offset 0x11E4) */

#define BIT_PORT4_RX_UCMD1_UAPSD0_OK_INT		BIT(31)
#define BIT_PORT4_RX_UCMD0_UAPSD0_OK_INT		BIT(30)
#define BIT_PORT4_TRIPKT_OK_INT			BIT(29)
#define BIT_PORT4_RX_EOSP_OK_INT			BIT(28)
#define BIT_PORT3_RX_UCMD1_UAPSD0_OK_INT		BIT(27)
#define BIT_PORT3_RX_UCMD0_UAPSD0_OK_INT		BIT(26)
#define BIT_PORT3_TRIPKT_OK_INT			BIT(25)
#define BIT_PORT3_RX_EOSP_OK_INT			BIT(24)
#define BIT_PORT2_RX_UCMD1_UAPSD0_OK_INT		BIT(23)
#define BIT_PORT2_RX_UCMD0_UAPSD0_OK_INT		BIT(22)
#define BIT_PORT2_TRIPKT_OK_INT			BIT(21)
#define BIT_PORT2_RX_EOSP_OK_INT			BIT(20)
#define BIT_PORT1_RX_UCMD1_UAPSD0_OK_INT		BIT(19)
#define BIT_PORT1_RX_UCMD0_UAPSD0_OK_INT		BIT(18)
#define BIT_PORT1_TRIPKT_OK_INT			BIT(17)
#define BIT_PORT1_RX_EOSP_OK_INT			BIT(16)
#define BIT_NOA2_TSFT_BIT32_INT			BIT(9)
#define BIT_NOA1_TSFT_BIT32_INT			BIT(8)
#define BIT_PORT4_TX_NULL1_DONE_INT			BIT(7)
#define BIT_PORT4_TX_NULL0_DONE_INT			BIT(6)
#define BIT_PORT3_TX_NULL1_DONE_INT			BIT(5)
#define BIT_PORT3_TX_NULL0_DONE_INT			BIT(4)
#define BIT_PORT2_TX_NULL1_DONE_INT			BIT(3)
#define BIT_PORT2_TX_NULL0_DONE_INT			BIT(2)
#define BIT_PORT1_TX_NULL1_DONE_INT			BIT(1)
#define BIT_PORT1_TX_NULL0_DONE_INT			BIT(0)

/* 2 REG_MSG2				(Offset 0x11F0) */

#define BIT_SHIFT_FW_MSG2				0
#define BIT_MASK_FW_MSG2				0xffffffffL
#define BIT_FW_MSG2(x)					(((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2)
#define BITS_FW_MSG2					(BIT_MASK_FW_MSG2 << BIT_SHIFT_FW_MSG2)
#define BIT_CLEAR_FW_MSG2(x)				((x) & (~BITS_FW_MSG2))
#define BIT_GET_FW_MSG2(x)				(((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2)
#define BIT_SET_FW_MSG2(x, v)				(BIT_CLEAR_FW_MSG2(x) | BIT_FW_MSG2(v))

/* 2 REG_MSG3				(Offset 0x11F4) */

#define BIT_SHIFT_FW_MSG3				0
#define BIT_MASK_FW_MSG3				0xffffffffL
#define BIT_FW_MSG3(x)					(((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3)
#define BITS_FW_MSG3					(BIT_MASK_FW_MSG3 << BIT_SHIFT_FW_MSG3)
#define BIT_CLEAR_FW_MSG3(x)				((x) & (~BITS_FW_MSG3))
#define BIT_GET_FW_MSG3(x)				(((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3)
#define BIT_SET_FW_MSG3(x, v)				(BIT_CLEAR_FW_MSG3(x) | BIT_FW_MSG3(v))

/* 2 REG_MSG4				(Offset 0x11F8) */

#define BIT_SHIFT_FW_MSG4				0
#define BIT_MASK_FW_MSG4				0xffffffffL
#define BIT_FW_MSG4(x)					(((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4)
#define BITS_FW_MSG4					(BIT_MASK_FW_MSG4 << BIT_SHIFT_FW_MSG4)
#define BIT_CLEAR_FW_MSG4(x)				((x) & (~BITS_FW_MSG4))
#define BIT_GET_FW_MSG4(x)				(((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4)
#define BIT_SET_FW_MSG4(x, v)				(BIT_CLEAR_FW_MSG4(x) | BIT_FW_MSG4(v))

/* 2 REG_MSG5				(Offset 0x11FC) */

#define BIT_LOAD_R_PGNUM				BIT(31)
#define BIT_EPQ_PUBLIC_DIS				BIT(27)
#define BIT_NPQ_PUBLIC_DIS				BIT(26)
#define BIT_LPQ_PUBLIC_DIS				BIT(25)
#define BIT_HPQ_PUBLIC_DIS				BIT(24)

#define BIT_SHIFT_PUBQ					16
#define BIT_MASK_PUBQ					0xff
#define BIT_PUBQ(x)					(((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ)
#define BITS_PUBQ					(BIT_MASK_PUBQ << BIT_SHIFT_PUBQ)
#define BIT_CLEAR_PUBQ(x)				((x) & (~BITS_PUBQ))
#define BIT_GET_PUBQ(x)				(((x) >> BIT_SHIFT_PUBQ) & BIT_MASK_PUBQ)
#define BIT_SET_PUBQ(x, v)				(BIT_CLEAR_PUBQ(x) | BIT_PUBQ(v))

#define BIT_SHIFT_LPQ					8
#define BIT_MASK_LPQ					0xff
#define BIT_LPQ(x)					(((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ)
#define BITS_LPQ					(BIT_MASK_LPQ << BIT_SHIFT_LPQ)
#define BIT_CLEAR_LPQ(x)				((x) & (~BITS_LPQ))
#define BIT_GET_LPQ(x)					(((x) >> BIT_SHIFT_LPQ) & BIT_MASK_LPQ)
#define BIT_SET_LPQ(x, v)				(BIT_CLEAR_LPQ(x) | BIT_LPQ(v))

#define BIT_SHIFT_FW_MSG5				0
#define BIT_MASK_FW_MSG5				0xffffffffL
#define BIT_FW_MSG5(x)					(((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5)
#define BITS_FW_MSG5					(BIT_MASK_FW_MSG5 << BIT_SHIFT_FW_MSG5)
#define BIT_CLEAR_FW_MSG5(x)				((x) & (~BITS_FW_MSG5))
#define BIT_GET_FW_MSG5(x)				(((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5)
#define BIT_SET_FW_MSG5(x, v)				(BIT_CLEAR_FW_MSG5(x) | BIT_FW_MSG5(v))

#define BIT_SHIFT_HPQ					0
#define BIT_MASK_HPQ					0xff
#define BIT_HPQ(x)					(((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ)
#define BITS_HPQ					(BIT_MASK_HPQ << BIT_SHIFT_HPQ)
#define BIT_CLEAR_HPQ(x)				((x) & (~BITS_HPQ))
#define BIT_GET_HPQ(x)					(((x) >> BIT_SHIFT_HPQ) & BIT_MASK_HPQ)
#define BIT_SET_HPQ(x, v)				(BIT_CLEAR_HPQ(x) | BIT_HPQ(v))

/* 2 REG_DDMA_CH0SA				(Offset 0x1200) */

#define BIT_SHIFT_DDMACH0_SA				0
#define BIT_MASK_DDMACH0_SA				0xffffffffL
#define BIT_DDMACH0_SA(x)				(((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA)
#define BITS_DDMACH0_SA				(BIT_MASK_DDMACH0_SA << BIT_SHIFT_DDMACH0_SA)
#define BIT_CLEAR_DDMACH0_SA(x)			((x) & (~BITS_DDMACH0_SA))
#define BIT_GET_DDMACH0_SA(x)				(((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA)
#define BIT_SET_DDMACH0_SA(x, v)			(BIT_CLEAR_DDMACH0_SA(x) | BIT_DDMACH0_SA(v))

/* 2 REG_DDMA_CH0DA				(Offset 0x1204) */

#define BIT_SHIFT_DDMACH0_DA				0
#define BIT_MASK_DDMACH0_DA				0xffffffffL
#define BIT_DDMACH0_DA(x)				(((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA)
#define BITS_DDMACH0_DA				(BIT_MASK_DDMACH0_DA << BIT_SHIFT_DDMACH0_DA)
#define BIT_CLEAR_DDMACH0_DA(x)			((x) & (~BITS_DDMACH0_DA))
#define BIT_GET_DDMACH0_DA(x)				(((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA)
#define BIT_SET_DDMACH0_DA(x, v)			(BIT_CLEAR_DDMACH0_DA(x) | BIT_DDMACH0_DA(v))

/* 2 REG_DDMA_CH0CTRL			(Offset 0x1208) */

#define BIT_DDMACH0_OWN				BIT(31)
#define BIT_DDMACH0_IDMEM_ERR				BIT(30)
#define BIT_DDMACH0_CHKSUM_EN				BIT(29)
#define BIT_DDMACH0_DA_W_DISABLE			BIT(28)
#define BIT_DDMACH0_CHKSUM_STS				BIT(27)
#define BIT_DDMACH0_DDMA_MODE				BIT(26)
#define BIT_DDMACH0_RESET_CHKSUM_STS			BIT(25)
#define BIT_DDMACH0_CHKSUM_CONT			BIT(24)

#define BIT_SHIFT_DDMACH0_DLEN				0
#define BIT_MASK_DDMACH0_DLEN				0x3ffff
#define BIT_DDMACH0_DLEN(x)				(((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN)
#define BITS_DDMACH0_DLEN				(BIT_MASK_DDMACH0_DLEN << BIT_SHIFT_DDMACH0_DLEN)
#define BIT_CLEAR_DDMACH0_DLEN(x)			((x) & (~BITS_DDMACH0_DLEN))
#define BIT_GET_DDMACH0_DLEN(x)			(((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN)
#define BIT_SET_DDMACH0_DLEN(x, v)			(BIT_CLEAR_DDMACH0_DLEN(x) | BIT_DDMACH0_DLEN(v))

/* 2 REG_DDMA_CH1SA				(Offset 0x1210) */

#define BIT_SHIFT_DDMACH1_SA				0
#define BIT_MASK_DDMACH1_SA				0xffffffffL
#define BIT_DDMACH1_SA(x)				(((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA)
#define BITS_DDMACH1_SA				(BIT_MASK_DDMACH1_SA << BIT_SHIFT_DDMACH1_SA)
#define BIT_CLEAR_DDMACH1_SA(x)			((x) & (~BITS_DDMACH1_SA))
#define BIT_GET_DDMACH1_SA(x)				(((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA)
#define BIT_SET_DDMACH1_SA(x, v)			(BIT_CLEAR_DDMACH1_SA(x) | BIT_DDMACH1_SA(v))

/* 2 REG_DDMA_CH1DA				(Offset 0x1214) */

#define BIT_SHIFT_DDMACH1_DA				0
#define BIT_MASK_DDMACH1_DA				0xffffffffL
#define BIT_DDMACH1_DA(x)				(((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA)
#define BITS_DDMACH1_DA				(BIT_MASK_DDMACH1_DA << BIT_SHIFT_DDMACH1_DA)
#define BIT_CLEAR_DDMACH1_DA(x)			((x) & (~BITS_DDMACH1_DA))
#define BIT_GET_DDMACH1_DA(x)				(((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA)
#define BIT_SET_DDMACH1_DA(x, v)			(BIT_CLEAR_DDMACH1_DA(x) | BIT_DDMACH1_DA(v))

/* 2 REG_DDMA_CH1CTRL			(Offset 0x1218) */

#define BIT_DDMACH1_OWN				BIT(31)
#define BIT_DDMACH1_IDMEM_ERR				BIT(30)
#define BIT_DDMACH1_CHKSUM_EN				BIT(29)
#define BIT_DDMACH1_DA_W_DISABLE			BIT(28)
#define BIT_DDMACH1_CHKSUM_STS				BIT(27)
#define BIT_DDMACH1_DDMA_MODE				BIT(26)
#define BIT_DDMACH1_RESET_CHKSUM_STS			BIT(25)
#define BIT_DDMACH1_CHKSUM_CONT			BIT(24)

#define BIT_SHIFT_DDMACH1_DLEN				0
#define BIT_MASK_DDMACH1_DLEN				0x3ffff
#define BIT_DDMACH1_DLEN(x)				(((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN)
#define BITS_DDMACH1_DLEN				(BIT_MASK_DDMACH1_DLEN << BIT_SHIFT_DDMACH1_DLEN)
#define BIT_CLEAR_DDMACH1_DLEN(x)			((x) & (~BITS_DDMACH1_DLEN))
#define BIT_GET_DDMACH1_DLEN(x)			(((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN)
#define BIT_SET_DDMACH1_DLEN(x, v)			(BIT_CLEAR_DDMACH1_DLEN(x) | BIT_DDMACH1_DLEN(v))

/* 2 REG_DDMA_CH2SA				(Offset 0x1220) */

#define BIT_SHIFT_DDMACH2_SA				0
#define BIT_MASK_DDMACH2_SA				0xffffffffL
#define BIT_DDMACH2_SA(x)				(((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA)
#define BITS_DDMACH2_SA				(BIT_MASK_DDMACH2_SA << BIT_SHIFT_DDMACH2_SA)
#define BIT_CLEAR_DDMACH2_SA(x)			((x) & (~BITS_DDMACH2_SA))
#define BIT_GET_DDMACH2_SA(x)				(((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA)
#define BIT_SET_DDMACH2_SA(x, v)			(BIT_CLEAR_DDMACH2_SA(x) | BIT_DDMACH2_SA(v))

/* 2 REG_DDMA_CH2DA				(Offset 0x1224) */

#define BIT_SHIFT_DDMACH2_DA				0
#define BIT_MASK_DDMACH2_DA				0xffffffffL
#define BIT_DDMACH2_DA(x)				(((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA)
#define BITS_DDMACH2_DA				(BIT_MASK_DDMACH2_DA << BIT_SHIFT_DDMACH2_DA)
#define BIT_CLEAR_DDMACH2_DA(x)			((x) & (~BITS_DDMACH2_DA))
#define BIT_GET_DDMACH2_DA(x)				(((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA)
#define BIT_SET_DDMACH2_DA(x, v)			(BIT_CLEAR_DDMACH2_DA(x) | BIT_DDMACH2_DA(v))

/* 2 REG_DDMA_CH2CTRL			(Offset 0x1228) */

#define BIT_DDMACH2_OWN				BIT(31)
#define BIT_DDMACH2_IDMEM_ERR				BIT(30)
#define BIT_DDMACH2_CHKSUM_EN				BIT(29)
#define BIT_DDMACH2_DA_W_DISABLE			BIT(28)
#define BIT_DDMACH2_CHKSUM_STS				BIT(27)
#define BIT_DDMACH2_DDMA_MODE				BIT(26)
#define BIT_DDMACH2_RESET_CHKSUM_STS			BIT(25)
#define BIT_DDMACH2_CHKSUM_CONT			BIT(24)

#define BIT_SHIFT_DDMACH2_DLEN				0
#define BIT_MASK_DDMACH2_DLEN				0x3ffff
#define BIT_DDMACH2_DLEN(x)				(((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN)
#define BITS_DDMACH2_DLEN				(BIT_MASK_DDMACH2_DLEN << BIT_SHIFT_DDMACH2_DLEN)
#define BIT_CLEAR_DDMACH2_DLEN(x)			((x) & (~BITS_DDMACH2_DLEN))
#define BIT_GET_DDMACH2_DLEN(x)			(((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN)
#define BIT_SET_DDMACH2_DLEN(x, v)			(BIT_CLEAR_DDMACH2_DLEN(x) | BIT_DDMACH2_DLEN(v))

/* 2 REG_DDMA_CH3SA				(Offset 0x1230) */

#define BIT_SHIFT_DDMACH3_SA				0
#define BIT_MASK_DDMACH3_SA				0xffffffffL
#define BIT_DDMACH3_SA(x)				(((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA)
#define BITS_DDMACH3_SA				(BIT_MASK_DDMACH3_SA << BIT_SHIFT_DDMACH3_SA)
#define BIT_CLEAR_DDMACH3_SA(x)			((x) & (~BITS_DDMACH3_SA))
#define BIT_GET_DDMACH3_SA(x)				(((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA)
#define BIT_SET_DDMACH3_SA(x, v)			(BIT_CLEAR_DDMACH3_SA(x) | BIT_DDMACH3_SA(v))

/* 2 REG_DDMA_CH3DA				(Offset 0x1234) */

#define BIT_SHIFT_DDMACH3_DA				0
#define BIT_MASK_DDMACH3_DA				0xffffffffL
#define BIT_DDMACH3_DA(x)				(((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA)
#define BITS_DDMACH3_DA				(BIT_MASK_DDMACH3_DA << BIT_SHIFT_DDMACH3_DA)
#define BIT_CLEAR_DDMACH3_DA(x)			((x) & (~BITS_DDMACH3_DA))
#define BIT_GET_DDMACH3_DA(x)				(((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA)
#define BIT_SET_DDMACH3_DA(x, v)			(BIT_CLEAR_DDMACH3_DA(x) | BIT_DDMACH3_DA(v))

/* 2 REG_DDMA_CH3CTRL			(Offset 0x1238) */

#define BIT_DDMACH3_OWN				BIT(31)
#define BIT_DDMACH3_IDMEM_ERR				BIT(30)
#define BIT_DDMACH3_CHKSUM_EN				BIT(29)
#define BIT_DDMACH3_DA_W_DISABLE			BIT(28)
#define BIT_DDMACH3_CHKSUM_STS				BIT(27)
#define BIT_DDMACH3_DDMA_MODE				BIT(26)
#define BIT_DDMACH3_RESET_CHKSUM_STS			BIT(25)
#define BIT_DDMACH3_CHKSUM_CONT			BIT(24)

#define BIT_SHIFT_DDMACH3_DLEN				0
#define BIT_MASK_DDMACH3_DLEN				0x3ffff
#define BIT_DDMACH3_DLEN(x)				(((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN)
#define BITS_DDMACH3_DLEN				(BIT_MASK_DDMACH3_DLEN << BIT_SHIFT_DDMACH3_DLEN)
#define BIT_CLEAR_DDMACH3_DLEN(x)			((x) & (~BITS_DDMACH3_DLEN))
#define BIT_GET_DDMACH3_DLEN(x)			(((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN)
#define BIT_SET_DDMACH3_DLEN(x, v)			(BIT_CLEAR_DDMACH3_DLEN(x) | BIT_DDMACH3_DLEN(v))

/* 2 REG_DDMA_CH4SA				(Offset 0x1240) */

#define BIT_SHIFT_DDMACH4_SA				0
#define BIT_MASK_DDMACH4_SA				0xffffffffL
#define BIT_DDMACH4_SA(x)				(((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA)
#define BITS_DDMACH4_SA				(BIT_MASK_DDMACH4_SA << BIT_SHIFT_DDMACH4_SA)
#define BIT_CLEAR_DDMACH4_SA(x)			((x) & (~BITS_DDMACH4_SA))
#define BIT_GET_DDMACH4_SA(x)				(((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA)
#define BIT_SET_DDMACH4_SA(x, v)			(BIT_CLEAR_DDMACH4_SA(x) | BIT_DDMACH4_SA(v))

/* 2 REG_DDMA_CH4DA				(Offset 0x1244) */

#define BIT_SHIFT_DDMACH4_DA				0
#define BIT_MASK_DDMACH4_DA				0xffffffffL
#define BIT_DDMACH4_DA(x)				(((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA)
#define BITS_DDMACH4_DA				(BIT_MASK_DDMACH4_DA << BIT_SHIFT_DDMACH4_DA)
#define BIT_CLEAR_DDMACH4_DA(x)			((x) & (~BITS_DDMACH4_DA))
#define BIT_GET_DDMACH4_DA(x)				(((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA)
#define BIT_SET_DDMACH4_DA(x, v)			(BIT_CLEAR_DDMACH4_DA(x) | BIT_DDMACH4_DA(v))

/* 2 REG_DDMA_CH4CTRL			(Offset 0x1248) */

#define BIT_DDMACH4_OWN				BIT(31)
#define BIT_DDMACH4_IDMEM_ERR				BIT(30)
#define BIT_DDMACH4_CHKSUM_EN				BIT(29)
#define BIT_DDMACH4_DA_W_DISABLE			BIT(28)
#define BIT_DDMACH4_CHKSUM_STS				BIT(27)
#define BIT_DDMACH4_DDMA_MODE				BIT(26)
#define BIT_DDMACH4_RESET_CHKSUM_STS			BIT(25)
#define BIT_DDMACH4_CHKSUM_CONT			BIT(24)

#define BIT_SHIFT_DDMACH4_DLEN				0
#define BIT_MASK_DDMACH4_DLEN				0x3ffff
#define BIT_DDMACH4_DLEN(x)				(((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN)
#define BITS_DDMACH4_DLEN				(BIT_MASK_DDMACH4_DLEN << BIT_SHIFT_DDMACH4_DLEN)
#define BIT_CLEAR_DDMACH4_DLEN(x)			((x) & (~BITS_DDMACH4_DLEN))
#define BIT_GET_DDMACH4_DLEN(x)			(((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN)
#define BIT_SET_DDMACH4_DLEN(x, v)			(BIT_CLEAR_DDMACH4_DLEN(x) | BIT_DDMACH4_DLEN(v))

/* 2 REG_DDMA_CH5SA				(Offset 0x1250) */

#define BIT_SHIFT_DDMACH5_SA				0
#define BIT_MASK_DDMACH5_SA				0xffffffffL
#define BIT_DDMACH5_SA(x)				(((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA)
#define BITS_DDMACH5_SA				(BIT_MASK_DDMACH5_SA << BIT_SHIFT_DDMACH5_SA)
#define BIT_CLEAR_DDMACH5_SA(x)			((x) & (~BITS_DDMACH5_SA))
#define BIT_GET_DDMACH5_SA(x)				(((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA)
#define BIT_SET_DDMACH5_SA(x, v)			(BIT_CLEAR_DDMACH5_SA(x) | BIT_DDMACH5_SA(v))

/* 2 REG_DDMA_CH5DA				(Offset 0x1254) */

#define BIT_SHIFT_DDMACH5_DA				0
#define BIT_MASK_DDMACH5_DA				0xffffffffL
#define BIT_DDMACH5_DA(x)				(((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA)
#define BITS_DDMACH5_DA				(BIT_MASK_DDMACH5_DA << BIT_SHIFT_DDMACH5_DA)
#define BIT_CLEAR_DDMACH5_DA(x)			((x) & (~BITS_DDMACH5_DA))
#define BIT_GET_DDMACH5_DA(x)				(((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA)
#define BIT_SET_DDMACH5_DA(x, v)			(BIT_CLEAR_DDMACH5_DA(x) | BIT_DDMACH5_DA(v))

/* 2 REG_DDMA_CH5CTRL			(Offset 0x1258) */

#define BIT_DDMACH5_OWN				BIT(31)
#define BIT_DDMACH5_IDMEM_ERR				BIT(30)
#define BIT_DDMACH5_CHKSUM_EN				BIT(29)
#define BIT_DDMACH5_DA_W_DISABLE			BIT(28)
#define BIT_DDMACH5_CHKSUM_STS				BIT(27)
#define BIT_DDMACH5_DDMA_MODE				BIT(26)
#define BIT_DDMACH5_RESET_CHKSUM_STS			BIT(25)
#define BIT_DDMACH5_CHKSUM_CONT			BIT(24)

#define BIT_SHIFT_DDMACH5_DLEN				0
#define BIT_MASK_DDMACH5_DLEN				0x3ffff
#define BIT_DDMACH5_DLEN(x)				(((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN)
#define BITS_DDMACH5_DLEN				(BIT_MASK_DDMACH5_DLEN << BIT_SHIFT_DDMACH5_DLEN)
#define BIT_CLEAR_DDMACH5_DLEN(x)			((x) & (~BITS_DDMACH5_DLEN))
#define BIT_GET_DDMACH5_DLEN(x)			(((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN)
#define BIT_SET_DDMACH5_DLEN(x, v)			(BIT_CLEAR_DDMACH5_DLEN(x) | BIT_DDMACH5_DLEN(v))

/* 2 REG_DDMA_INT_MSK			(Offset 0x12E0) */

#define BIT_DDMACH5_MSK				BIT(5)
#define BIT_DDMACH4_MSK				BIT(4)
#define BIT_DDMACH3_MSK				BIT(3)
#define BIT_DDMACH2_MSK				BIT(2)
#define BIT_DDMACH1_MSK				BIT(1)
#define BIT_DDMACH0_MSK				BIT(0)

/* 2 REG_DDMA_CHSTATUS			(Offset 0x12E8) */

#define BIT_DDMACH5_BUSY				BIT(5)
#define BIT_DDMACH4_BUSY				BIT(4)
#define BIT_DDMACH3_BUSY				BIT(3)
#define BIT_DDMACH2_BUSY				BIT(2)
#define BIT_DDMACH1_BUSY				BIT(1)
#define BIT_DDMACH0_BUSY				BIT(0)

/* 2 REG_DDMA_CHKSUM				(Offset 0x12F0) */

#define BIT_SHIFT_DDMA_OCP_CS				24
#define BIT_MASK_DDMA_OCP_CS				0x7
#define BIT_DDMA_OCP_CS(x)				(((x) & BIT_MASK_DDMA_OCP_CS) << BIT_SHIFT_DDMA_OCP_CS)
#define BITS_DDMA_OCP_CS				(BIT_MASK_DDMA_OCP_CS << BIT_SHIFT_DDMA_OCP_CS)
#define BIT_CLEAR_DDMA_OCP_CS(x)			((x) & (~BITS_DDMA_OCP_CS))
#define BIT_GET_DDMA_OCP_CS(x)				(((x) >> BIT_SHIFT_DDMA_OCP_CS) & BIT_MASK_DDMA_OCP_CS)
#define BIT_SET_DDMA_OCP_CS(x, v)			(BIT_CLEAR_DDMA_OCP_CS(x) | BIT_DDMA_OCP_CS(v))

#define BIT_SHIFT_DDMA_DST_CS				22
#define BIT_MASK_DDMA_DST_CS				0x3
#define BIT_DDMA_DST_CS(x)				(((x) & BIT_MASK_DDMA_DST_CS) << BIT_SHIFT_DDMA_DST_CS)
#define BITS_DDMA_DST_CS				(BIT_MASK_DDMA_DST_CS << BIT_SHIFT_DDMA_DST_CS)
#define BIT_CLEAR_DDMA_DST_CS(x)			((x) & (~BITS_DDMA_DST_CS))
#define BIT_GET_DDMA_DST_CS(x)				(((x) >> BIT_SHIFT_DDMA_DST_CS) & BIT_MASK_DDMA_DST_CS)
#define BIT_SET_DDMA_DST_CS(x, v)			(BIT_CLEAR_DDMA_DST_CS(x) | BIT_DDMA_DST_CS(v))

#define BIT_SHIFT_DDMA_SRC_CS				20
#define BIT_MASK_DDMA_SRC_CS				0x3
#define BIT_DDMA_SRC_CS(x)				(((x) & BIT_MASK_DDMA_SRC_CS) << BIT_SHIFT_DDMA_SRC_CS)
#define BITS_DDMA_SRC_CS				(BIT_MASK_DDMA_SRC_CS << BIT_SHIFT_DDMA_SRC_CS)
#define BIT_CLEAR_DDMA_SRC_CS(x)			((x) & (~BITS_DDMA_SRC_CS))
#define BIT_GET_DDMA_SRC_CS(x)				(((x) >> BIT_SHIFT_DDMA_SRC_CS) & BIT_MASK_DDMA_SRC_CS)
#define BIT_SET_DDMA_SRC_CS(x, v)			(BIT_CLEAR_DDMA_SRC_CS(x) | BIT_DDMA_SRC_CS(v))

#define BIT_SHIFT_DDMA_ARB_CS				16
#define BIT_MASK_DDMA_ARB_CS				0xf
#define BIT_DDMA_ARB_CS(x)				(((x) & BIT_MASK_DDMA_ARB_CS) << BIT_SHIFT_DDMA_ARB_CS)
#define BITS_DDMA_ARB_CS				(BIT_MASK_DDMA_ARB_CS << BIT_SHIFT_DDMA_ARB_CS)
#define BIT_CLEAR_DDMA_ARB_CS(x)			((x) & (~BITS_DDMA_ARB_CS))
#define BIT_GET_DDMA_ARB_CS(x)				(((x) >> BIT_SHIFT_DDMA_ARB_CS) & BIT_MASK_DDMA_ARB_CS)
#define BIT_SET_DDMA_ARB_CS(x, v)			(BIT_CLEAR_DDMA_ARB_CS(x) | BIT_DDMA_ARB_CS(v))

#define BIT_SHIFT_IDDMA0_CHKSUM			0
#define BIT_MASK_IDDMA0_CHKSUM				0xffff
#define BIT_IDDMA0_CHKSUM(x)				(((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM)
#define BITS_IDDMA0_CHKSUM				(BIT_MASK_IDDMA0_CHKSUM << BIT_SHIFT_IDDMA0_CHKSUM)
#define BIT_CLEAR_IDDMA0_CHKSUM(x)			((x) & (~BITS_IDDMA0_CHKSUM))
#define BIT_GET_IDDMA0_CHKSUM(x)			(((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM)
#define BIT_SET_IDDMA0_CHKSUM(x, v)			(BIT_CLEAR_IDDMA0_CHKSUM(x) | BIT_IDDMA0_CHKSUM(v))

/* 2 REG_DDMA_MONITOR			(Offset 0x12FC) */

#define BIT_IDDMA0_PERMU_UNDERFLOW			BIT(14)
#define BIT_IDDMA0_FIFO_UNDERFLOW			BIT(13)
#define BIT_IDDMA0_FIFO_OVERFLOW			BIT(12)
#define BIT_CH5_ERR					BIT(5)
#define BIT_CH4_ERR					BIT(4)
#define BIT_CH3_ERR					BIT(3)
#define BIT_CH2_ERR					BIT(2)
#define BIT_CH1_ERR					BIT(1)
#define BIT_CH0_ERR					BIT(0)

/* 2 REG_ARFR6				(Offset 0x1400) */

#define BIT_SHIFT_ADPT_RATE_TABLE_L6			0
#define BIT_MASK_ADPT_RATE_TABLE_L6			0xffffffffL
#define BIT_ADPT_RATE_TABLE_L6(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_L6) << BIT_SHIFT_ADPT_RATE_TABLE_L6)
#define BITS_ADPT_RATE_TABLE_L6			(BIT_MASK_ADPT_RATE_TABLE_L6 << BIT_SHIFT_ADPT_RATE_TABLE_L6)
#define BIT_CLEAR_ADPT_RATE_TABLE_L6(x)		((x) & (~BITS_ADPT_RATE_TABLE_L6))
#define BIT_GET_ADPT_RATE_TABLE_L6(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_L6) & BIT_MASK_ADPT_RATE_TABLE_L6)
#define BIT_SET_ADPT_RATE_TABLE_L6(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_L6(x) | BIT_ADPT_RATE_TABLE_L6(v))

/* 2 REG_ARFRH6				(Offset 0x1404) */

#define BIT_SHIFT_ADPT_RATE_TABLE_H6			0
#define BIT_MASK_ADPT_RATE_TABLE_H6			0xffffffffL
#define BIT_ADPT_RATE_TABLE_H6(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_H6) << BIT_SHIFT_ADPT_RATE_TABLE_H6)
#define BITS_ADPT_RATE_TABLE_H6			(BIT_MASK_ADPT_RATE_TABLE_H6 << BIT_SHIFT_ADPT_RATE_TABLE_H6)
#define BIT_CLEAR_ADPT_RATE_TABLE_H6(x)		((x) & (~BITS_ADPT_RATE_TABLE_H6))
#define BIT_GET_ADPT_RATE_TABLE_H6(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_H6) & BIT_MASK_ADPT_RATE_TABLE_H6)
#define BIT_SET_ADPT_RATE_TABLE_H6(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_H6(x) | BIT_ADPT_RATE_TABLE_H6(v))

/* 2 REG_ARFR7				(Offset 0x1408) */

#define BIT_SHIFT_ADPT_RATE_TABLE_L7			0
#define BIT_MASK_ADPT_RATE_TABLE_L7			0xffffffffL
#define BIT_ADPT_RATE_TABLE_L7(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_L7) << BIT_SHIFT_ADPT_RATE_TABLE_L7)
#define BITS_ADPT_RATE_TABLE_L7			(BIT_MASK_ADPT_RATE_TABLE_L7 << BIT_SHIFT_ADPT_RATE_TABLE_L7)
#define BIT_CLEAR_ADPT_RATE_TABLE_L7(x)		((x) & (~BITS_ADPT_RATE_TABLE_L7))
#define BIT_GET_ADPT_RATE_TABLE_L7(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_L7) & BIT_MASK_ADPT_RATE_TABLE_L7)
#define BIT_SET_ADPT_RATE_TABLE_L7(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_L7(x) | BIT_ADPT_RATE_TABLE_L7(v))

/* 2 REG_ARFRH7				(Offset 0x140C) */

#define BIT_SHIFT_ADPT_RATE_TABLE_H7			0
#define BIT_MASK_ADPT_RATE_TABLE_H7			0xffffffffL
#define BIT_ADPT_RATE_TABLE_H7(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_H7) << BIT_SHIFT_ADPT_RATE_TABLE_H7)
#define BITS_ADPT_RATE_TABLE_H7			(BIT_MASK_ADPT_RATE_TABLE_H7 << BIT_SHIFT_ADPT_RATE_TABLE_H7)
#define BIT_CLEAR_ADPT_RATE_TABLE_H7(x)		((x) & (~BITS_ADPT_RATE_TABLE_H7))
#define BIT_GET_ADPT_RATE_TABLE_H7(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_H7) & BIT_MASK_ADPT_RATE_TABLE_H7)
#define BIT_SET_ADPT_RATE_TABLE_H7(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_H7(x) | BIT_ADPT_RATE_TABLE_H7(v))

/* 2 REG_ARFR8				(Offset 0x1410) */

#define BIT_SHIFT_ADPT_RATE_TABLE_L8			0
#define BIT_MASK_ADPT_RATE_TABLE_L8			0xffffffffL
#define BIT_ADPT_RATE_TABLE_L8(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_L8) << BIT_SHIFT_ADPT_RATE_TABLE_L8)
#define BITS_ADPT_RATE_TABLE_L8			(BIT_MASK_ADPT_RATE_TABLE_L8 << BIT_SHIFT_ADPT_RATE_TABLE_L8)
#define BIT_CLEAR_ADPT_RATE_TABLE_L8(x)		((x) & (~BITS_ADPT_RATE_TABLE_L8))
#define BIT_GET_ADPT_RATE_TABLE_L8(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_L8) & BIT_MASK_ADPT_RATE_TABLE_L8)
#define BIT_SET_ADPT_RATE_TABLE_L8(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_L8(x) | BIT_ADPT_RATE_TABLE_L8(v))

/* 2 REG_ARFRH8				(Offset 0x1414) */

#define BIT_SHIFT_ADPT_RATE_TABLE_H8			0
#define BIT_MASK_ADPT_RATE_TABLE_H8			0xffffffffL
#define BIT_ADPT_RATE_TABLE_H8(x)			(((x) & BIT_MASK_ADPT_RATE_TABLE_H8) << BIT_SHIFT_ADPT_RATE_TABLE_H8)
#define BITS_ADPT_RATE_TABLE_H8			(BIT_MASK_ADPT_RATE_TABLE_H8 << BIT_SHIFT_ADPT_RATE_TABLE_H8)
#define BIT_CLEAR_ADPT_RATE_TABLE_H8(x)		((x) & (~BITS_ADPT_RATE_TABLE_H8))
#define BIT_GET_ADPT_RATE_TABLE_H8(x)			(((x) >> BIT_SHIFT_ADPT_RATE_TABLE_H8) & BIT_MASK_ADPT_RATE_TABLE_H8)
#define BIT_SET_ADPT_RATE_TABLE_H8(x, v)		(BIT_CLEAR_ADPT_RATE_TABLE_H8(x) | BIT_ADPT_RATE_TABLE_H8(v))

#define BIT_SHIFT_AESIV_OFFSET				0
#define BIT_MASK_AESIV_OFFSET				0xfff
#define BIT_AESIV_OFFSET(x)				(((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET)
#define BITS_AESIV_OFFSET				(BIT_MASK_AESIV_OFFSET << BIT_SHIFT_AESIV_OFFSET)
#define BIT_CLEAR_AESIV_OFFSET(x)			((x) & (~BITS_AESIV_OFFSET))
#define BIT_GET_AESIV_OFFSET(x)			(((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET)
#define BIT_SET_AESIV_OFFSET(x, v)			(BIT_CLEAR_AESIV_OFFSET(x) | BIT_AESIV_OFFSET(v))

/* 2 REG_BF0_TIME_SETTING			(Offset 0x1428) */

#define BIT_BF0_TIMER_SET				BIT(31)
#define BIT_BF0_TIMER_CLR				BIT(30)
#define BIT_EN_BF0_UPDATE				BIT(29)
#define BIT_EN_BF0_TIMER				BIT(28)

#define BIT_SHIFT_BF0_PRETIME_OVER			16
#define BIT_MASK_BF0_PRETIME_OVER			0xfff
#define BIT_BF0_PRETIME_OVER(x)			(((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER)
#define BITS_BF0_PRETIME_OVER				(BIT_MASK_BF0_PRETIME_OVER << BIT_SHIFT_BF0_PRETIME_OVER)
#define BIT_CLEAR_BF0_PRETIME_OVER(x)			((x) & (~BITS_BF0_PRETIME_OVER))
#define BIT_GET_BF0_PRETIME_OVER(x)			(((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER)
#define BIT_SET_BF0_PRETIME_OVER(x, v)			(BIT_CLEAR_BF0_PRETIME_OVER(x) | BIT_BF0_PRETIME_OVER(v))

#define BIT_SHIFT_BF0_LIFETIME				0
#define BIT_MASK_BF0_LIFETIME				0xffff
#define BIT_BF0_LIFETIME(x)				(((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME)
#define BITS_BF0_LIFETIME				(BIT_MASK_BF0_LIFETIME << BIT_SHIFT_BF0_LIFETIME)
#define BIT_CLEAR_BF0_LIFETIME(x)			((x) & (~BITS_BF0_LIFETIME))
#define BIT_GET_BF0_LIFETIME(x)			(((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME)
#define BIT_SET_BF0_LIFETIME(x, v)			(BIT_CLEAR_BF0_LIFETIME(x) | BIT_BF0_LIFETIME(v))

/* 2 REG_BF1_TIME_SETTING			(Offset 0x142C) */

#define BIT_BF1_TIMER_SET				BIT(31)
#define BIT_BF1_TIMER_CLR				BIT(30)
#define BIT_EN_BF1_UPDATE				BIT(29)
#define BIT_EN_BF1_TIMER				BIT(28)

#define BIT_SHIFT_BF1_PRETIME_OVER			16
#define BIT_MASK_BF1_PRETIME_OVER			0xfff
#define BIT_BF1_PRETIME_OVER(x)			(((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER)
#define BITS_BF1_PRETIME_OVER				(BIT_MASK_BF1_PRETIME_OVER << BIT_SHIFT_BF1_PRETIME_OVER)
#define BIT_CLEAR_BF1_PRETIME_OVER(x)			((x) & (~BITS_BF1_PRETIME_OVER))
#define BIT_GET_BF1_PRETIME_OVER(x)			(((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER)
#define BIT_SET_BF1_PRETIME_OVER(x, v)			(BIT_CLEAR_BF1_PRETIME_OVER(x) | BIT_BF1_PRETIME_OVER(v))

#define BIT_SHIFT_BF1_LIFETIME				0
#define BIT_MASK_BF1_LIFETIME				0xffff
#define BIT_BF1_LIFETIME(x)				(((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME)
#define BITS_BF1_LIFETIME				(BIT_MASK_BF1_LIFETIME << BIT_SHIFT_BF1_LIFETIME)
#define BIT_CLEAR_BF1_LIFETIME(x)			((x) & (~BITS_BF1_LIFETIME))
#define BIT_GET_BF1_LIFETIME(x)			(((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME)
#define BIT_SET_BF1_LIFETIME(x, v)			(BIT_CLEAR_BF1_LIFETIME(x) | BIT_BF1_LIFETIME(v))

/* 2 REG_BF_TIMEOUT_EN			(Offset 0x1430) */

#define BIT_EN_VHT_LDPC				BIT(9)
#define BIT_EN_HT_LDPC					BIT(8)
#define BIT_BF1_TIMEOUT_EN				BIT(1)
#define BIT_BF0_TIMEOUT_EN				BIT(0)

/* 2 REG_MACID_RELEASE0			(Offset 0x1434) */

#define BIT_SHIFT_MACID31_0_RELEASE			0
#define BIT_MASK_MACID31_0_RELEASE			0xffffffffL
#define BIT_MACID31_0_RELEASE(x)			(((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE)
#define BITS_MACID31_0_RELEASE				(BIT_MASK_MACID31_0_RELEASE << BIT_SHIFT_MACID31_0_RELEASE)
#define BIT_CLEAR_MACID31_0_RELEASE(x)			((x) & (~BITS_MACID31_0_RELEASE))
#define BIT_GET_MACID31_0_RELEASE(x)			(((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE)
#define BIT_SET_MACID31_0_RELEASE(x, v)		(BIT_CLEAR_MACID31_0_RELEASE(x) | BIT_MACID31_0_RELEASE(v))

/* 2 REG_MACID_RELEASE1			(Offset 0x1438) */

#define BIT_SHIFT_MACID63_32_RELEASE			0
#define BIT_MASK_MACID63_32_RELEASE			0xffffffffL
#define BIT_MACID63_32_RELEASE(x)			(((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE)
#define BITS_MACID63_32_RELEASE			(BIT_MASK_MACID63_32_RELEASE << BIT_SHIFT_MACID63_32_RELEASE)
#define BIT_CLEAR_MACID63_32_RELEASE(x)		((x) & (~BITS_MACID63_32_RELEASE))
#define BIT_GET_MACID63_32_RELEASE(x)			(((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE)
#define BIT_SET_MACID63_32_RELEASE(x, v)		(BIT_CLEAR_MACID63_32_RELEASE(x) | BIT_MACID63_32_RELEASE(v))

/* 2 REG_MACID_RELEASE2			(Offset 0x143C) */

#define BIT_SHIFT_MACID95_64_RELEASE			0
#define BIT_MASK_MACID95_64_RELEASE			0xffffffffL
#define BIT_MACID95_64_RELEASE(x)			(((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE)
#define BITS_MACID95_64_RELEASE			(BIT_MASK_MACID95_64_RELEASE << BIT_SHIFT_MACID95_64_RELEASE)
#define BIT_CLEAR_MACID95_64_RELEASE(x)		((x) & (~BITS_MACID95_64_RELEASE))
#define BIT_GET_MACID95_64_RELEASE(x)			(((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE)
#define BIT_SET_MACID95_64_RELEASE(x, v)		(BIT_CLEAR_MACID95_64_RELEASE(x) | BIT_MACID95_64_RELEASE(v))

/* 2 REG_MACID_RELEASE3			(Offset 0x1440) */

#define BIT_SHIFT_MACID127_96_RELEASE			0
#define BIT_MASK_MACID127_96_RELEASE			0xffffffffL
#define BIT_MACID127_96_RELEASE(x)			(((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE)
#define BITS_MACID127_96_RELEASE			(BIT_MASK_MACID127_96_RELEASE << BIT_SHIFT_MACID127_96_RELEASE)
#define BIT_CLEAR_MACID127_96_RELEASE(x)		((x) & (~BITS_MACID127_96_RELEASE))
#define BIT_GET_MACID127_96_RELEASE(x)			(((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE)
#define BIT_SET_MACID127_96_RELEASE(x, v)		(BIT_CLEAR_MACID127_96_RELEASE(x) | BIT_MACID127_96_RELEASE(v))

/* 2 REG_MACID_RELEASE_SETTING		(Offset 0x1444) */

#define BIT_MACID_VALUE				BIT(7)

#define BIT_SHIFT_MACID_OFFSET				0
#define BIT_MASK_MACID_OFFSET				0x7f
#define BIT_MACID_OFFSET(x)				(((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET)
#define BITS_MACID_OFFSET				(BIT_MASK_MACID_OFFSET << BIT_SHIFT_MACID_OFFSET)
#define BIT_CLEAR_MACID_OFFSET(x)			((x) & (~BITS_MACID_OFFSET))
#define BIT_GET_MACID_OFFSET(x)			(((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET)
#define BIT_SET_MACID_OFFSET(x, v)			(BIT_CLEAR_MACID_OFFSET(x) | BIT_MACID_OFFSET(v))

/* 2 REG_FAST_EDCA_VOVI_SETTING		(Offset 0x1448) */

#define BIT_SHIFT_VI_FAST_EDCA_TO			24
#define BIT_MASK_VI_FAST_EDCA_TO			0xff
#define BIT_VI_FAST_EDCA_TO(x)				(((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO)
#define BITS_VI_FAST_EDCA_TO				(BIT_MASK_VI_FAST_EDCA_TO << BIT_SHIFT_VI_FAST_EDCA_TO)
#define BIT_CLEAR_VI_FAST_EDCA_TO(x)			((x) & (~BITS_VI_FAST_EDCA_TO))
#define BIT_GET_VI_FAST_EDCA_TO(x)			(((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO)
#define BIT_SET_VI_FAST_EDCA_TO(x, v)			(BIT_CLEAR_VI_FAST_EDCA_TO(x) | BIT_VI_FAST_EDCA_TO(v))

#define BIT_VI_THRESHOLD_SEL				BIT(23)

#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH			16
#define BIT_MASK_VI_FAST_EDCA_PKT_TH			0x7f
#define BIT_VI_FAST_EDCA_PKT_TH(x)			(((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH)
#define BITS_VI_FAST_EDCA_PKT_TH			(BIT_MASK_VI_FAST_EDCA_PKT_TH << BIT_SHIFT_VI_FAST_EDCA_PKT_TH)
#define BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x)		((x) & (~BITS_VI_FAST_EDCA_PKT_TH))
#define BIT_GET_VI_FAST_EDCA_PKT_TH(x)			(((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH)
#define BIT_SET_VI_FAST_EDCA_PKT_TH(x, v)		(BIT_CLEAR_VI_FAST_EDCA_PKT_TH(x) | BIT_VI_FAST_EDCA_PKT_TH(v))

#define BIT_SHIFT_VO_FAST_EDCA_TO			8
#define BIT_MASK_VO_FAST_EDCA_TO			0xff
#define BIT_VO_FAST_EDCA_TO(x)				(((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO)
#define BITS_VO_FAST_EDCA_TO				(BIT_MASK_VO_FAST_EDCA_TO << BIT_SHIFT_VO_FAST_EDCA_TO)
#define BIT_CLEAR_VO_FAST_EDCA_TO(x)			((x) & (~BITS_VO_FAST_EDCA_TO))
#define BIT_GET_VO_FAST_EDCA_TO(x)			(((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO)
#define BIT_SET_VO_FAST_EDCA_TO(x, v)			(BIT_CLEAR_VO_FAST_EDCA_TO(x) | BIT_VO_FAST_EDCA_TO(v))

#define BIT_VO_THRESHOLD_SEL				BIT(7)

#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH			0
#define BIT_MASK_VO_FAST_EDCA_PKT_TH			0x7f
#define BIT_VO_FAST_EDCA_PKT_TH(x)			(((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH)
#define BITS_VO_FAST_EDCA_PKT_TH			(BIT_MASK_VO_FAST_EDCA_PKT_TH << BIT_SHIFT_VO_FAST_EDCA_PKT_TH)
#define BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x)		((x) & (~BITS_VO_FAST_EDCA_PKT_TH))
#define BIT_GET_VO_FAST_EDCA_PKT_TH(x)			(((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH)
#define BIT_SET_VO_FAST_EDCA_PKT_TH(x, v)		(BIT_CLEAR_VO_FAST_EDCA_PKT_TH(x) | BIT_VO_FAST_EDCA_PKT_TH(v))

/* 2 REG_FAST_EDCA_BEBK_SETTING		(Offset 0x144C) */

#define BIT_SHIFT_BK_FAST_EDCA_TO			24
#define BIT_MASK_BK_FAST_EDCA_TO			0xff
#define BIT_BK_FAST_EDCA_TO(x)				(((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO)
#define BITS_BK_FAST_EDCA_TO				(BIT_MASK_BK_FAST_EDCA_TO << BIT_SHIFT_BK_FAST_EDCA_TO)
#define BIT_CLEAR_BK_FAST_EDCA_TO(x)			((x) & (~BITS_BK_FAST_EDCA_TO))
#define BIT_GET_BK_FAST_EDCA_TO(x)			(((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO)
#define BIT_SET_BK_FAST_EDCA_TO(x, v)			(BIT_CLEAR_BK_FAST_EDCA_TO(x) | BIT_BK_FAST_EDCA_TO(v))

#define BIT_BK_THRESHOLD_SEL				BIT(23)

#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH			16
#define BIT_MASK_BK_FAST_EDCA_PKT_TH			0x7f
#define BIT_BK_FAST_EDCA_PKT_TH(x)			(((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH)
#define BITS_BK_FAST_EDCA_PKT_TH			(BIT_MASK_BK_FAST_EDCA_PKT_TH << BIT_SHIFT_BK_FAST_EDCA_PKT_TH)
#define BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x)		((x) & (~BITS_BK_FAST_EDCA_PKT_TH))
#define BIT_GET_BK_FAST_EDCA_PKT_TH(x)			(((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH)
#define BIT_SET_BK_FAST_EDCA_PKT_TH(x, v)		(BIT_CLEAR_BK_FAST_EDCA_PKT_TH(x) | BIT_BK_FAST_EDCA_PKT_TH(v))

#define BIT_SHIFT_BE_FAST_EDCA_TO			8
#define BIT_MASK_BE_FAST_EDCA_TO			0xff
#define BIT_BE_FAST_EDCA_TO(x)				(((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO)
#define BITS_BE_FAST_EDCA_TO				(BIT_MASK_BE_FAST_EDCA_TO << BIT_SHIFT_BE_FAST_EDCA_TO)
#define BIT_CLEAR_BE_FAST_EDCA_TO(x)			((x) & (~BITS_BE_FAST_EDCA_TO))
#define BIT_GET_BE_FAST_EDCA_TO(x)			(((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO)
#define BIT_SET_BE_FAST_EDCA_TO(x, v)			(BIT_CLEAR_BE_FAST_EDCA_TO(x) | BIT_BE_FAST_EDCA_TO(v))

#define BIT_BE_THRESHOLD_SEL				BIT(7)

#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH			0
#define BIT_MASK_BE_FAST_EDCA_PKT_TH			0x7f
#define BIT_BE_FAST_EDCA_PKT_TH(x)			(((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH)
#define BITS_BE_FAST_EDCA_PKT_TH			(BIT_MASK_BE_FAST_EDCA_PKT_TH << BIT_SHIFT_BE_FAST_EDCA_PKT_TH)
#define BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x)		((x) & (~BITS_BE_FAST_EDCA_PKT_TH))
#define BIT_GET_BE_FAST_EDCA_PKT_TH(x)			(((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH)
#define BIT_SET_BE_FAST_EDCA_PKT_TH(x, v)		(BIT_CLEAR_BE_FAST_EDCA_PKT_TH(x) | BIT_BE_FAST_EDCA_PKT_TH(v))

/* 2 REG_MACID_DROP0				(Offset 0x1450) */

#define BIT_SHIFT_MACID31_0_DROP			0
#define BIT_MASK_MACID31_0_DROP			0xffffffffL
#define BIT_MACID31_0_DROP(x)				(((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP)
#define BITS_MACID31_0_DROP				(BIT_MASK_MACID31_0_DROP << BIT_SHIFT_MACID31_0_DROP)
#define BIT_CLEAR_MACID31_0_DROP(x)			((x) & (~BITS_MACID31_0_DROP))
#define BIT_GET_MACID31_0_DROP(x)			(((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP)
#define BIT_SET_MACID31_0_DROP(x, v)			(BIT_CLEAR_MACID31_0_DROP(x) | BIT_MACID31_0_DROP(v))

/* 2 REG_MACID_DROP1				(Offset 0x1454) */

#define BIT_SHIFT_MACID63_32_DROP			0
#define BIT_MASK_MACID63_32_DROP			0xffffffffL
#define BIT_MACID63_32_DROP(x)				(((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP)
#define BITS_MACID63_32_DROP				(BIT_MASK_MACID63_32_DROP << BIT_SHIFT_MACID63_32_DROP)
#define BIT_CLEAR_MACID63_32_DROP(x)			((x) & (~BITS_MACID63_32_DROP))
#define BIT_GET_MACID63_32_DROP(x)			(((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP)
#define BIT_SET_MACID63_32_DROP(x, v)			(BIT_CLEAR_MACID63_32_DROP(x) | BIT_MACID63_32_DROP(v))

/* 2 REG_MACID_DROP2				(Offset 0x1458) */

#define BIT_SHIFT_MACID95_64_DROP			0
#define BIT_MASK_MACID95_64_DROP			0xffffffffL
#define BIT_MACID95_64_DROP(x)				(((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP)
#define BITS_MACID95_64_DROP				(BIT_MASK_MACID95_64_DROP << BIT_SHIFT_MACID95_64_DROP)
#define BIT_CLEAR_MACID95_64_DROP(x)			((x) & (~BITS_MACID95_64_DROP))
#define BIT_GET_MACID95_64_DROP(x)			(((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP)
#define BIT_SET_MACID95_64_DROP(x, v)			(BIT_CLEAR_MACID95_64_DROP(x) | BIT_MACID95_64_DROP(v))

/* 2 REG_MACID_DROP3				(Offset 0x145C) */

#define BIT_SHIFT_MACID127_96_DROP			0
#define BIT_MASK_MACID127_96_DROP			0xffffffffL
#define BIT_MACID127_96_DROP(x)			(((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP)
#define BITS_MACID127_96_DROP				(BIT_MASK_MACID127_96_DROP << BIT_SHIFT_MACID127_96_DROP)
#define BIT_CLEAR_MACID127_96_DROP(x)			((x) & (~BITS_MACID127_96_DROP))
#define BIT_GET_MACID127_96_DROP(x)			(((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP)
#define BIT_SET_MACID127_96_DROP(x, v)			(BIT_CLEAR_MACID127_96_DROP(x) | BIT_MACID127_96_DROP(v))

/* 2 REG_R_MACID_RELEASE_SUCCESS_0		(Offset 0x1460) */

#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0		0
#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0		0xffffffffL
#define BIT_R_MACID_RELEASE_SUCCESS_0(x)		(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0)
#define BITS_R_MACID_RELEASE_SUCCESS_0			(BIT_MASK_R_MACID_RELEASE_SUCCESS_0 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0)
#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x)	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_0))
#define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x)		(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0)
#define BIT_SET_R_MACID_RELEASE_SUCCESS_0(x, v)	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_0(x) | BIT_R_MACID_RELEASE_SUCCESS_0(v))

/* 2 REG_R_MACID_RELEASE_SUCCESS_1		(Offset 0x1464) */

#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1		0
#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1		0xffffffffL
#define BIT_R_MACID_RELEASE_SUCCESS_1(x)		(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1)
#define BITS_R_MACID_RELEASE_SUCCESS_1			(BIT_MASK_R_MACID_RELEASE_SUCCESS_1 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1)
#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x)	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_1))
#define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x)		(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1)
#define BIT_SET_R_MACID_RELEASE_SUCCESS_1(x, v)	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_1(x) | BIT_R_MACID_RELEASE_SUCCESS_1(v))

/* 2 REG_R_MACID_RELEASE_SUCCESS_2		(Offset 0x1468) */

#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2		0
#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2		0xffffffffL
#define BIT_R_MACID_RELEASE_SUCCESS_2(x)		(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2)
#define BITS_R_MACID_RELEASE_SUCCESS_2			(BIT_MASK_R_MACID_RELEASE_SUCCESS_2 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2)
#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x)	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_2))
#define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x)		(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2)
#define BIT_SET_R_MACID_RELEASE_SUCCESS_2(x, v)	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_2(x) | BIT_R_MACID_RELEASE_SUCCESS_2(v))

/* 2 REG_R_MACID_RELEASE_SUCCESS_3		(Offset 0x146C) */

#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3		0
#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3		0xffffffffL
#define BIT_R_MACID_RELEASE_SUCCESS_3(x)		(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3)
#define BITS_R_MACID_RELEASE_SUCCESS_3			(BIT_MASK_R_MACID_RELEASE_SUCCESS_3 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3)
#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x)	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_3))
#define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x)		(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3)
#define BIT_SET_R_MACID_RELEASE_SUCCESS_3(x, v)	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_3(x) | BIT_R_MACID_RELEASE_SUCCESS_3(v))

/* 2 REG_MGQ_FIFO_WRITE_POINTER		(Offset 0x1470) */

#define BIT_MGQ_FIFO_OV				BIT(7)
#define BIT_MGQ_FIFO_WPTR_ERR				BIT(6)
#define BIT_CPUM_LIFETIME_EN				BIT(5)

#define BIT_SHIFT_MGQ_FIFO_WPTR			0
#define BIT_MASK_MGQ_FIFO_WPTR				0x1f
#define BIT_MGQ_FIFO_WPTR(x)				(((x) & BIT_MASK_MGQ_FIFO_WPTR) << BIT_SHIFT_MGQ_FIFO_WPTR)
#define BITS_MGQ_FIFO_WPTR				(BIT_MASK_MGQ_FIFO_WPTR << BIT_SHIFT_MGQ_FIFO_WPTR)
#define BIT_CLEAR_MGQ_FIFO_WPTR(x)			((x) & (~BITS_MGQ_FIFO_WPTR))
#define BIT_GET_MGQ_FIFO_WPTR(x)			(((x) >> BIT_SHIFT_MGQ_FIFO_WPTR) & BIT_MASK_MGQ_FIFO_WPTR)
#define BIT_SET_MGQ_FIFO_WPTR(x, v)			(BIT_CLEAR_MGQ_FIFO_WPTR(x) | BIT_MGQ_FIFO_WPTR(v))

/* 2 REG_MGQ_FIFO_READ_POINTER		(Offset 0x1471) */

#define BIT_SHIFT_MGQ_FIFO_SIZE			6
#define BIT_MASK_MGQ_FIFO_SIZE				0x3
#define BIT_MGQ_FIFO_SIZE(x)				(((x) & BIT_MASK_MGQ_FIFO_SIZE) << BIT_SHIFT_MGQ_FIFO_SIZE)
#define BITS_MGQ_FIFO_SIZE				(BIT_MASK_MGQ_FIFO_SIZE << BIT_SHIFT_MGQ_FIFO_SIZE)
#define BIT_CLEAR_MGQ_FIFO_SIZE(x)			((x) & (~BITS_MGQ_FIFO_SIZE))
#define BIT_GET_MGQ_FIFO_SIZE(x)			(((x) >> BIT_SHIFT_MGQ_FIFO_SIZE) & BIT_MASK_MGQ_FIFO_SIZE)
#define BIT_SET_MGQ_FIFO_SIZE(x, v)			(BIT_CLEAR_MGQ_FIFO_SIZE(x) | BIT_MGQ_FIFO_SIZE(v))

#define BIT_MGQ_FIFO_PAUSE				BIT(5)

#define BIT_SHIFT_MGQ_FIFO_RPTR			0
#define BIT_MASK_MGQ_FIFO_RPTR				0x1f
#define BIT_MGQ_FIFO_RPTR(x)				(((x) & BIT_MASK_MGQ_FIFO_RPTR) << BIT_SHIFT_MGQ_FIFO_RPTR)
#define BITS_MGQ_FIFO_RPTR				(BIT_MASK_MGQ_FIFO_RPTR << BIT_SHIFT_MGQ_FIFO_RPTR)
#define BIT_CLEAR_MGQ_FIFO_RPTR(x)			((x) & (~BITS_MGQ_FIFO_RPTR))
#define BIT_GET_MGQ_FIFO_RPTR(x)			(((x) >> BIT_SHIFT_MGQ_FIFO_RPTR) & BIT_MASK_MGQ_FIFO_RPTR)
#define BIT_SET_MGQ_FIFO_RPTR(x, v)			(BIT_CLEAR_MGQ_FIFO_RPTR(x) | BIT_MGQ_FIFO_RPTR(v))

/* 2 REG_MGQ_FIFO_ENABLE			(Offset 0x1472) */

#define BIT_MGQ_FIFO_EN				BIT(15)

#define BIT_SHIFT_MGQ_FIFO_PG_SIZE			12
#define BIT_MASK_MGQ_FIFO_PG_SIZE			0x7
#define BIT_MGQ_FIFO_PG_SIZE(x)			(((x) & BIT_MASK_MGQ_FIFO_PG_SIZE) << BIT_SHIFT_MGQ_FIFO_PG_SIZE)
#define BITS_MGQ_FIFO_PG_SIZE				(BIT_MASK_MGQ_FIFO_PG_SIZE << BIT_SHIFT_MGQ_FIFO_PG_SIZE)
#define BIT_CLEAR_MGQ_FIFO_PG_SIZE(x)			((x) & (~BITS_MGQ_FIFO_PG_SIZE))
#define BIT_GET_MGQ_FIFO_PG_SIZE(x)			(((x) >> BIT_SHIFT_MGQ_FIFO_PG_SIZE) & BIT_MASK_MGQ_FIFO_PG_SIZE)
#define BIT_SET_MGQ_FIFO_PG_SIZE(x, v)			(BIT_CLEAR_MGQ_FIFO_PG_SIZE(x) | BIT_MGQ_FIFO_PG_SIZE(v))

#define BIT_SHIFT_MGQ_FIFO_START_PG			0
#define BIT_MASK_MGQ_FIFO_START_PG			0xfff
#define BIT_MGQ_FIFO_START_PG(x)			(((x) & BIT_MASK_MGQ_FIFO_START_PG) << BIT_SHIFT_MGQ_FIFO_START_PG)
#define BITS_MGQ_FIFO_START_PG				(BIT_MASK_MGQ_FIFO_START_PG << BIT_SHIFT_MGQ_FIFO_START_PG)
#define BIT_CLEAR_MGQ_FIFO_START_PG(x)			((x) & (~BITS_MGQ_FIFO_START_PG))
#define BIT_GET_MGQ_FIFO_START_PG(x)			(((x) >> BIT_SHIFT_MGQ_FIFO_START_PG) & BIT_MASK_MGQ_FIFO_START_PG)
#define BIT_SET_MGQ_FIFO_START_PG(x, v)		(BIT_CLEAR_MGQ_FIFO_START_PG(x) | BIT_MGQ_FIFO_START_PG(v))

/* 2 REG_MGQ_FIFO_RELEASE_INT_MASK		(Offset 0x1474) */

#define BIT_SHIFT_MGQ_FIFO_INT_MASK			0
#define BIT_MASK_MGQ_FIFO_INT_MASK			0xffff
#define BIT_MGQ_FIFO_INT_MASK(x)			(((x) & BIT_MASK_MGQ_FIFO_INT_MASK) << BIT_SHIFT_MGQ_FIFO_INT_MASK)
#define BITS_MGQ_FIFO_INT_MASK				(BIT_MASK_MGQ_FIFO_INT_MASK << BIT_SHIFT_MGQ_FIFO_INT_MASK)
#define BIT_CLEAR_MGQ_FIFO_INT_MASK(x)			((x) & (~BITS_MGQ_FIFO_INT_MASK))
#define BIT_GET_MGQ_FIFO_INT_MASK(x)			(((x) >> BIT_SHIFT_MGQ_FIFO_INT_MASK) & BIT_MASK_MGQ_FIFO_INT_MASK)
#define BIT_SET_MGQ_FIFO_INT_MASK(x, v)		(BIT_CLEAR_MGQ_FIFO_INT_MASK(x) | BIT_MGQ_FIFO_INT_MASK(v))

/* 2 REG_MGQ_FIFO_RELEASE_INT_FLAG		(Offset 0x1476) */

#define BIT_SHIFT_MGQ_FIFO_VALID_CLR_1			8
#define BIT_MASK_MGQ_FIFO_VALID_CLR_1			0xff
#define BIT_MGQ_FIFO_VALID_CLR_1(x)			(((x) & BIT_MASK_MGQ_FIFO_VALID_CLR_1) << BIT_SHIFT_MGQ_FIFO_VALID_CLR_1)
#define BITS_MGQ_FIFO_VALID_CLR_1			(BIT_MASK_MGQ_FIFO_VALID_CLR_1 << BIT_SHIFT_MGQ_FIFO_VALID_CLR_1)
#define BIT_CLEAR_MGQ_FIFO_VALID_CLR_1(x)		((x) & (~BITS_MGQ_FIFO_VALID_CLR_1))
#define BIT_GET_MGQ_FIFO_VALID_CLR_1(x)		(((x) >> BIT_SHIFT_MGQ_FIFO_VALID_CLR_1) & BIT_MASK_MGQ_FIFO_VALID_CLR_1)
#define BIT_SET_MGQ_FIFO_VALID_CLR_1(x, v)		(BIT_CLEAR_MGQ_FIFO_VALID_CLR_1(x) | BIT_MGQ_FIFO_VALID_CLR_1(v))

#define BIT_SHIFT_MGQ_FIFO_INT_FLAG			0
#define BIT_MASK_MGQ_FIFO_INT_FLAG			0xffff
#define BIT_MGQ_FIFO_INT_FLAG(x)			(((x) & BIT_MASK_MGQ_FIFO_INT_FLAG) << BIT_SHIFT_MGQ_FIFO_INT_FLAG)
#define BITS_MGQ_FIFO_INT_FLAG				(BIT_MASK_MGQ_FIFO_INT_FLAG << BIT_SHIFT_MGQ_FIFO_INT_FLAG)
#define BIT_CLEAR_MGQ_FIFO_INT_FLAG(x)			((x) & (~BITS_MGQ_FIFO_INT_FLAG))
#define BIT_GET_MGQ_FIFO_INT_FLAG(x)			(((x) >> BIT_SHIFT_MGQ_FIFO_INT_FLAG) & BIT_MASK_MGQ_FIFO_INT_FLAG)
#define BIT_SET_MGQ_FIFO_INT_FLAG(x, v)		(BIT_CLEAR_MGQ_FIFO_INT_FLAG(x) | BIT_MGQ_FIFO_INT_FLAG(v))

#define BIT_SHIFT_MGQ_FIFO_VALID_CLR_0			0
#define BIT_MASK_MGQ_FIFO_VALID_CLR_0			0xff
#define BIT_MGQ_FIFO_VALID_CLR_0(x)			(((x) & BIT_MASK_MGQ_FIFO_VALID_CLR_0) << BIT_SHIFT_MGQ_FIFO_VALID_CLR_0)
#define BITS_MGQ_FIFO_VALID_CLR_0			(BIT_MASK_MGQ_FIFO_VALID_CLR_0 << BIT_SHIFT_MGQ_FIFO_VALID_CLR_0)
#define BIT_CLEAR_MGQ_FIFO_VALID_CLR_0(x)		((x) & (~BITS_MGQ_FIFO_VALID_CLR_0))
#define BIT_GET_MGQ_FIFO_VALID_CLR_0(x)		(((x) >> BIT_SHIFT_MGQ_FIFO_VALID_CLR_0) & BIT_MASK_MGQ_FIFO_VALID_CLR_0)
#define BIT_SET_MGQ_FIFO_VALID_CLR_0(x, v)		(BIT_CLEAR_MGQ_FIFO_VALID_CLR_0(x) | BIT_MGQ_FIFO_VALID_CLR_0(v))

/* 2 REG_MGQ_FIFO_LIFETIME			(Offset 0x147A) */

#define BIT_SHIFT_MGQ_FIFO_LIFETIME			0
#define BIT_MASK_MGQ_FIFO_LIFETIME			0xffff
#define BIT_MGQ_FIFO_LIFETIME(x)			(((x) & BIT_MASK_MGQ_FIFO_LIFETIME) << BIT_SHIFT_MGQ_FIFO_LIFETIME)
#define BITS_MGQ_FIFO_LIFETIME				(BIT_MASK_MGQ_FIFO_LIFETIME << BIT_SHIFT_MGQ_FIFO_LIFETIME)
#define BIT_CLEAR_MGQ_FIFO_LIFETIME(x)			((x) & (~BITS_MGQ_FIFO_LIFETIME))
#define BIT_GET_MGQ_FIFO_LIFETIME(x)			(((x) >> BIT_SHIFT_MGQ_FIFO_LIFETIME) & BIT_MASK_MGQ_FIFO_LIFETIME)
#define BIT_SET_MGQ_FIFO_LIFETIME(x, v)		(BIT_CLEAR_MGQ_FIFO_LIFETIME(x) | BIT_MGQ_FIFO_LIFETIME(v))

/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET (Offset 0x147C) */

#define BIT_SHIFT_RANDOM_VALUE_SHIFT			9
#define BIT_MASK_RANDOM_VALUE_SHIFT			0x7
#define BIT_RANDOM_VALUE_SHIFT(x)			(((x) & BIT_MASK_RANDOM_VALUE_SHIFT) << BIT_SHIFT_RANDOM_VALUE_SHIFT)
#define BITS_RANDOM_VALUE_SHIFT			(BIT_MASK_RANDOM_VALUE_SHIFT << BIT_SHIFT_RANDOM_VALUE_SHIFT)
#define BIT_CLEAR_RANDOM_VALUE_SHIFT(x)		((x) & (~BITS_RANDOM_VALUE_SHIFT))
#define BIT_GET_RANDOM_VALUE_SHIFT(x)			(((x) >> BIT_SHIFT_RANDOM_VALUE_SHIFT) & BIT_MASK_RANDOM_VALUE_SHIFT)
#define BIT_SET_RANDOM_VALUE_SHIFT(x, v)		(BIT_CLEAR_RANDOM_VALUE_SHIFT(x) | BIT_RANDOM_VALUE_SHIFT(v))

#define BIT_ENABLE_NEW_EDCA				BIT(8)

#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET	0
#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET	0x7f
#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x)	(((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
#define BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET	(BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
#define BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x)	((x) & (~BITS_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET))
#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x)	(((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET)
#define BIT_SET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x, v)	(BIT_CLEAR_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) | BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(v))

#define BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER		0
#define BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER		0xff
#define BIT_MEDIUM_HAS_IDLE_TRIGGER(x)			(((x) & BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER) << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER)
#define BITS_MEDIUM_HAS_IDLE_TRIGGER			(BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER << BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER)
#define BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x)		((x) & (~BITS_MEDIUM_HAS_IDLE_TRIGGER))
#define BIT_GET_MEDIUM_HAS_IDLE_TRIGGER(x)		(((x) >> BIT_SHIFT_MEDIUM_HAS_IDLE_TRIGGER) & BIT_MASK_MEDIUM_HAS_IDLE_TRIGGER)
#define BIT_SET_MEDIUM_HAS_IDLE_TRIGGER(x, v)		(BIT_CLEAR_MEDIUM_HAS_IDLE_TRIGGER(x) | BIT_MEDIUM_HAS_IDLE_TRIGGER(v))

/* 2 REG_SWPS_CTRL				(Offset 0x14F4) */

#define BIT_SHIFT_SWPS_PKT_TH_V1			16
#define BIT_MASK_SWPS_PKT_TH_V1			0xffff
#define BIT_SWPS_PKT_TH_V1(x)				(((x) & BIT_MASK_SWPS_PKT_TH_V1) << BIT_SHIFT_SWPS_PKT_TH_V1)
#define BITS_SWPS_PKT_TH_V1				(BIT_MASK_SWPS_PKT_TH_V1 << BIT_SHIFT_SWPS_PKT_TH_V1)
#define BIT_CLEAR_SWPS_PKT_TH_V1(x)			((x) & (~BITS_SWPS_PKT_TH_V1))
#define BIT_GET_SWPS_PKT_TH_V1(x)			(((x) >> BIT_SHIFT_SWPS_PKT_TH_V1) & BIT_MASK_SWPS_PKT_TH_V1)
#define BIT_SET_SWPS_PKT_TH_V1(x, v)			(BIT_CLEAR_SWPS_PKT_TH_V1(x) | BIT_SWPS_PKT_TH_V1(v))

#define BIT_SHIFT_SWPS_RPT_LENGTH			8
#define BIT_MASK_SWPS_RPT_LENGTH			0x7f
#define BIT_SWPS_RPT_LENGTH(x)				(((x) & BIT_MASK_SWPS_RPT_LENGTH) << BIT_SHIFT_SWPS_RPT_LENGTH)
#define BITS_SWPS_RPT_LENGTH				(BIT_MASK_SWPS_RPT_LENGTH << BIT_SHIFT_SWPS_RPT_LENGTH)
#define BIT_CLEAR_SWPS_RPT_LENGTH(x)			((x) & (~BITS_SWPS_RPT_LENGTH))
#define BIT_GET_SWPS_RPT_LENGTH(x)			(((x) >> BIT_SHIFT_SWPS_RPT_LENGTH) & BIT_MASK_SWPS_RPT_LENGTH)
#define BIT_SET_SWPS_RPT_LENGTH(x, v)			(BIT_CLEAR_SWPS_RPT_LENGTH(x) | BIT_SWPS_RPT_LENGTH(v))

#define BIT_MACID_SWPS_EN_SEL_V1			BIT(2)
#define BIT_SWPS_MANUALL_POLLING			BIT(1)
#define BIT_SWPS_EN					BIT(0)

/* 2 REG_SWPS_TIME_TH			(Offset 0x14F8) */

#define BIT_SHIFT_SWPS_PSTIME_TH			16
#define BIT_MASK_SWPS_PSTIME_TH			0xffff
#define BIT_SWPS_PSTIME_TH(x)				(((x) & BIT_MASK_SWPS_PSTIME_TH) << BIT_SHIFT_SWPS_PSTIME_TH)
#define BITS_SWPS_PSTIME_TH				(BIT_MASK_SWPS_PSTIME_TH << BIT_SHIFT_SWPS_PSTIME_TH)
#define BIT_CLEAR_SWPS_PSTIME_TH(x)			((x) & (~BITS_SWPS_PSTIME_TH))
#define BIT_GET_SWPS_PSTIME_TH(x)			(((x) >> BIT_SHIFT_SWPS_PSTIME_TH) & BIT_MASK_SWPS_PSTIME_TH)
#define BIT_SET_SWPS_PSTIME_TH(x, v)			(BIT_CLEAR_SWPS_PSTIME_TH(x) | BIT_SWPS_PSTIME_TH(v))

#define BIT_SHIFT_SWPS_TIME_TH				0
#define BIT_MASK_SWPS_TIME_TH				0xffff
#define BIT_SWPS_TIME_TH(x)				(((x) & BIT_MASK_SWPS_TIME_TH) << BIT_SHIFT_SWPS_TIME_TH)
#define BITS_SWPS_TIME_TH				(BIT_MASK_SWPS_TIME_TH << BIT_SHIFT_SWPS_TIME_TH)
#define BIT_CLEAR_SWPS_TIME_TH(x)			((x) & (~BITS_SWPS_TIME_TH))
#define BIT_GET_SWPS_TIME_TH(x)			(((x) >> BIT_SHIFT_SWPS_TIME_TH) & BIT_MASK_SWPS_TIME_TH)
#define BIT_SET_SWPS_TIME_TH(x, v)			(BIT_CLEAR_SWPS_TIME_TH(x) | BIT_SWPS_TIME_TH(v))

/* 2 REG_MACID_SWPS_EN			(Offset 0x14FC) */

#define BIT_SHIFT_MACID_SWPS_EN			0
#define BIT_MASK_MACID_SWPS_EN				0xffffffffL
#define BIT_MACID_SWPS_EN(x)				(((x) & BIT_MASK_MACID_SWPS_EN) << BIT_SHIFT_MACID_SWPS_EN)
#define BITS_MACID_SWPS_EN				(BIT_MASK_MACID_SWPS_EN << BIT_SHIFT_MACID_SWPS_EN)
#define BIT_CLEAR_MACID_SWPS_EN(x)			((x) & (~BITS_MACID_SWPS_EN))
#define BIT_GET_MACID_SWPS_EN(x)			(((x) >> BIT_SHIFT_MACID_SWPS_EN) & BIT_MASK_MACID_SWPS_EN)
#define BIT_SET_MACID_SWPS_EN(x, v)			(BIT_CLEAR_MACID_SWPS_EN(x) | BIT_MACID_SWPS_EN(v))

/* 2 REG_CPUMGQ_TX_TIMER			(Offset 0x1500) */

#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1			0
#define BIT_MASK_CPUMGQ_TX_TIMER_V1			0xffffffffL
#define BIT_CPUMGQ_TX_TIMER_V1(x)			(((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1)
#define BITS_CPUMGQ_TX_TIMER_V1			(BIT_MASK_CPUMGQ_TX_TIMER_V1 << BIT_SHIFT_CPUMGQ_TX_TIMER_V1)
#define BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x)		((x) & (~BITS_CPUMGQ_TX_TIMER_V1))
#define BIT_GET_CPUMGQ_TX_TIMER_V1(x)			(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1)
#define BIT_SET_CPUMGQ_TX_TIMER_V1(x, v)		(BIT_CLEAR_CPUMGQ_TX_TIMER_V1(x) | BIT_CPUMGQ_TX_TIMER_V1(v))

/* 2 REG_PS_TIMER_A				(Offset 0x1504) */

#define BIT_SHIFT_PS_TIMER_A_V1			0
#define BIT_MASK_PS_TIMER_A_V1				0xffffffffL
#define BIT_PS_TIMER_A_V1(x)				(((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1)
#define BITS_PS_TIMER_A_V1				(BIT_MASK_PS_TIMER_A_V1 << BIT_SHIFT_PS_TIMER_A_V1)
#define BIT_CLEAR_PS_TIMER_A_V1(x)			((x) & (~BITS_PS_TIMER_A_V1))
#define BIT_GET_PS_TIMER_A_V1(x)			(((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1)
#define BIT_SET_PS_TIMER_A_V1(x, v)			(BIT_CLEAR_PS_TIMER_A_V1(x) | BIT_PS_TIMER_A_V1(v))

/* 2 REG_PS_TIMER_B				(Offset 0x1508) */

#define BIT_SHIFT_PS_TIMER_B_V1			0
#define BIT_MASK_PS_TIMER_B_V1				0xffffffffL
#define BIT_PS_TIMER_B_V1(x)				(((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1)
#define BITS_PS_TIMER_B_V1				(BIT_MASK_PS_TIMER_B_V1 << BIT_SHIFT_PS_TIMER_B_V1)
#define BIT_CLEAR_PS_TIMER_B_V1(x)			((x) & (~BITS_PS_TIMER_B_V1))
#define BIT_GET_PS_TIMER_B_V1(x)			(((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1)
#define BIT_SET_PS_TIMER_B_V1(x, v)			(BIT_CLEAR_PS_TIMER_B_V1(x) | BIT_PS_TIMER_B_V1(v))

/* 2 REG_PS_TIMER_C				(Offset 0x150C) */

#define BIT_SHIFT_PS_TIMER_C_V1			0
#define BIT_MASK_PS_TIMER_C_V1				0xffffffffL
#define BIT_PS_TIMER_C_V1(x)				(((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1)
#define BITS_PS_TIMER_C_V1				(BIT_MASK_PS_TIMER_C_V1 << BIT_SHIFT_PS_TIMER_C_V1)
#define BIT_CLEAR_PS_TIMER_C_V1(x)			((x) & (~BITS_PS_TIMER_C_V1))
#define BIT_GET_PS_TIMER_C_V1(x)			(((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1)
#define BIT_SET_PS_TIMER_C_V1(x, v)			(BIT_CLEAR_PS_TIMER_C_V1(x) | BIT_PS_TIMER_C_V1(v))

/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL	(Offset 0x1510) */

#define BIT_CPUMGQ_TIMER_EN				BIT(31)
#define BIT_CPUMGQ_TX_EN				BIT(28)

#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL			24
#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL			0x7
#define BIT_CPUMGQ_TIMER_TSF_SEL(x)			(((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL)
#define BITS_CPUMGQ_TIMER_TSF_SEL			(BIT_MASK_CPUMGQ_TIMER_TSF_SEL << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL)
#define BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x)		((x) & (~BITS_CPUMGQ_TIMER_TSF_SEL))
#define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x)		(((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL)
#define BIT_SET_CPUMGQ_TIMER_TSF_SEL(x, v)		(BIT_CLEAR_CPUMGQ_TIMER_TSF_SEL(x) | BIT_CPUMGQ_TIMER_TSF_SEL(v))

#define BIT_PS_TIMER_C_EN				BIT(23)

#define BIT_SHIFT_PS_TIMER_C_TSF_SEL			16
#define BIT_MASK_PS_TIMER_C_TSF_SEL			0x7
#define BIT_PS_TIMER_C_TSF_SEL(x)			(((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL)
#define BITS_PS_TIMER_C_TSF_SEL			(BIT_MASK_PS_TIMER_C_TSF_SEL << BIT_SHIFT_PS_TIMER_C_TSF_SEL)
#define BIT_CLEAR_PS_TIMER_C_TSF_SEL(x)		((x) & (~BITS_PS_TIMER_C_TSF_SEL))
#define BIT_GET_PS_TIMER_C_TSF_SEL(x)			(((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL)
#define BIT_SET_PS_TIMER_C_TSF_SEL(x, v)		(BIT_CLEAR_PS_TIMER_C_TSF_SEL(x) | BIT_PS_TIMER_C_TSF_SEL(v))

#define BIT_PS_TIMER_B_EN				BIT(15)

#define BIT_SHIFT_PS_TIMER_B_TSF_SEL			8
#define BIT_MASK_PS_TIMER_B_TSF_SEL			0x7
#define BIT_PS_TIMER_B_TSF_SEL(x)			(((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL)
#define BITS_PS_TIMER_B_TSF_SEL			(BIT_MASK_PS_TIMER_B_TSF_SEL << BIT_SHIFT_PS_TIMER_B_TSF_SEL)
#define BIT_CLEAR_PS_TIMER_B_TSF_SEL(x)		((x) & (~BITS_PS_TIMER_B_TSF_SEL))
#define BIT_GET_PS_TIMER_B_TSF_SEL(x)			(((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL)
#define BIT_SET_PS_TIMER_B_TSF_SEL(x, v)		(BIT_CLEAR_PS_TIMER_B_TSF_SEL(x) | BIT_PS_TIMER_B_TSF_SEL(v))

#define BIT_PS_TIMER_A_EN				BIT(7)

#define BIT_SHIFT_PS_TIMER_A_TSF_SEL			0
#define BIT_MASK_PS_TIMER_A_TSF_SEL			0x7
#define BIT_PS_TIMER_A_TSF_SEL(x)			(((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL)
#define BITS_PS_TIMER_A_TSF_SEL			(BIT_MASK_PS_TIMER_A_TSF_SEL << BIT_SHIFT_PS_TIMER_A_TSF_SEL)
#define BIT_CLEAR_PS_TIMER_A_TSF_SEL(x)		((x) & (~BITS_PS_TIMER_A_TSF_SEL))
#define BIT_GET_PS_TIMER_A_TSF_SEL(x)			(((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL)
#define BIT_SET_PS_TIMER_A_TSF_SEL(x, v)		(BIT_CLEAR_PS_TIMER_A_TSF_SEL(x) | BIT_PS_TIMER_A_TSF_SEL(v))

/* 2 REG_CPUMGQ_TX_TIMER_EARLY		(Offset 0x1514) */

#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY		0
#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY			0xff
#define BIT_CPUMGQ_TX_TIMER_EARLY(x)			(((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY)
#define BITS_CPUMGQ_TX_TIMER_EARLY			(BIT_MASK_CPUMGQ_TX_TIMER_EARLY << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY)
#define BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x)		((x) & (~BITS_CPUMGQ_TX_TIMER_EARLY))
#define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x)		(((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY)
#define BIT_SET_CPUMGQ_TX_TIMER_EARLY(x, v)		(BIT_CLEAR_CPUMGQ_TX_TIMER_EARLY(x) | BIT_CPUMGQ_TX_TIMER_EARLY(v))

/* 2 REG_PS_TIMER_A_EARLY			(Offset 0x1515) */

#define BIT_SHIFT_PS_TIMER_A_EARLY			0
#define BIT_MASK_PS_TIMER_A_EARLY			0xff
#define BIT_PS_TIMER_A_EARLY(x)			(((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY)
#define BITS_PS_TIMER_A_EARLY				(BIT_MASK_PS_TIMER_A_EARLY << BIT_SHIFT_PS_TIMER_A_EARLY)
#define BIT_CLEAR_PS_TIMER_A_EARLY(x)			((x) & (~BITS_PS_TIMER_A_EARLY))
#define BIT_GET_PS_TIMER_A_EARLY(x)			(((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY)
#define BIT_SET_PS_TIMER_A_EARLY(x, v)			(BIT_CLEAR_PS_TIMER_A_EARLY(x) | BIT_PS_TIMER_A_EARLY(v))

/* 2 REG_PS_TIMER_B_EARLY			(Offset 0x1516) */

#define BIT_SHIFT_PS_TIMER_B_EARLY			0
#define BIT_MASK_PS_TIMER_B_EARLY			0xff
#define BIT_PS_TIMER_B_EARLY(x)			(((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY)
#define BITS_PS_TIMER_B_EARLY				(BIT_MASK_PS_TIMER_B_EARLY << BIT_SHIFT_PS_TIMER_B_EARLY)
#define BIT_CLEAR_PS_TIMER_B_EARLY(x)			((x) & (~BITS_PS_TIMER_B_EARLY))
#define BIT_GET_PS_TIMER_B_EARLY(x)			(((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY)
#define BIT_SET_PS_TIMER_B_EARLY(x, v)			(BIT_CLEAR_PS_TIMER_B_EARLY(x) | BIT_PS_TIMER_B_EARLY(v))

/* 2 REG_PS_TIMER_C_EARLY			(Offset 0x1517) */

#define BIT_MAC_STOP_CPUMGQ				BIT(16)

#define BIT_SHIFT_PS_TIMER_C_EARLY			0
#define BIT_MASK_PS_TIMER_C_EARLY			0xff
#define BIT_PS_TIMER_C_EARLY(x)			(((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY)
#define BITS_PS_TIMER_C_EARLY				(BIT_MASK_PS_TIMER_C_EARLY << BIT_SHIFT_PS_TIMER_C_EARLY)
#define BIT_CLEAR_PS_TIMER_C_EARLY(x)			((x) & (~BITS_PS_TIMER_C_EARLY))
#define BIT_GET_PS_TIMER_C_EARLY(x)			(((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY)
#define BIT_SET_PS_TIMER_C_EARLY(x, v)			(BIT_CLEAR_PS_TIMER_C_EARLY(x) | BIT_PS_TIMER_C_EARLY(v))

/* 2 REG_TSF_SYN_CTRL0			(Offset 0x1520) */

#define BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0_V1		16
#define BIT_MASK_TSF_SYNC_INTERVAL_PORT0_V1		0xffff
#define BIT_TSF_SYNC_INTERVAL_PORT0_V1(x)		(((x) & BIT_MASK_TSF_SYNC_INTERVAL_PORT0_V1) << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0_V1)
#define BITS_TSF_SYNC_INTERVAL_PORT0_V1		(BIT_MASK_TSF_SYNC_INTERVAL_PORT0_V1 << BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0_V1)
#define BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0_V1(x)	((x) & (~BITS_TSF_SYNC_INTERVAL_PORT0_V1))
#define BIT_GET_TSF_SYNC_INTERVAL_PORT0_V1(x)		(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_PORT0_V1) & BIT_MASK_TSF_SYNC_INTERVAL_PORT0_V1)
#define BIT_SET_TSF_SYNC_INTERVAL_PORT0_V1(x, v)	(BIT_CLEAR_TSF_SYNC_INTERVAL_PORT0_V1(x) | BIT_TSF_SYNC_INTERVAL_PORT0_V1(v))

#define BIT_TSF_SYNC_SIGNAL_V1				BIT(8)
#define BIT_TSF_SYNC_COMPARE_POLLING			BIT(7)
#define BIT_TSF_SYNC_POLLING				BIT(6)

#define BIT_SHIFT_TSF_SYNC_DUT				3
#define BIT_MASK_TSF_SYNC_DUT				0x7
#define BIT_TSF_SYNC_DUT(x)				(((x) & BIT_MASK_TSF_SYNC_DUT) << BIT_SHIFT_TSF_SYNC_DUT)
#define BITS_TSF_SYNC_DUT				(BIT_MASK_TSF_SYNC_DUT << BIT_SHIFT_TSF_SYNC_DUT)
#define BIT_CLEAR_TSF_SYNC_DUT(x)			((x) & (~BITS_TSF_SYNC_DUT))
#define BIT_GET_TSF_SYNC_DUT(x)			(((x) >> BIT_SHIFT_TSF_SYNC_DUT) & BIT_MASK_TSF_SYNC_DUT)
#define BIT_SET_TSF_SYNC_DUT(x, v)			(BIT_CLEAR_TSF_SYNC_DUT(x) | BIT_TSF_SYNC_DUT(v))

#define BIT_SHIFT_TSF_SYNC_SOURCE			0
#define BIT_MASK_TSF_SYNC_SOURCE			0x7
#define BIT_TSF_SYNC_SOURCE(x)				(((x) & BIT_MASK_TSF_SYNC_SOURCE) << BIT_SHIFT_TSF_SYNC_SOURCE)
#define BITS_TSF_SYNC_SOURCE				(BIT_MASK_TSF_SYNC_SOURCE << BIT_SHIFT_TSF_SYNC_SOURCE)
#define BIT_CLEAR_TSF_SYNC_SOURCE(x)			((x) & (~BITS_TSF_SYNC_SOURCE))
#define BIT_GET_TSF_SYNC_SOURCE(x)			(((x) >> BIT_SHIFT_TSF_SYNC_SOURCE) & BIT_MASK_TSF_SYNC_SOURCE)
#define BIT_SET_TSF_SYNC_SOURCE(x, v)			(BIT_CLEAR_TSF_SYNC_SOURCE(x) | BIT_TSF_SYNC_SOURCE(v))

/* 2 REG_TSF_SYN_OFFSET1			(Offset 0x1524) */

#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1		16
#define BIT_MASK_TSF_SYNC_INTERVAL_CLI1		0xffff
#define BIT_TSF_SYNC_INTERVAL_CLI1(x)			(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI1) << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1)
#define BITS_TSF_SYNC_INTERVAL_CLI1			(BIT_MASK_TSF_SYNC_INTERVAL_CLI1 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1)
#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x)		((x) & (~BITS_TSF_SYNC_INTERVAL_CLI1))
#define BIT_GET_TSF_SYNC_INTERVAL_CLI1(x)		(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI1) & BIT_MASK_TSF_SYNC_INTERVAL_CLI1)
#define BIT_SET_TSF_SYNC_INTERVAL_CLI1(x, v)		(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI1(x) | BIT_TSF_SYNC_INTERVAL_CLI1(v))

#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0		0
#define BIT_MASK_TSF_SYNC_INTERVAL_CLI0		0xffff
#define BIT_TSF_SYNC_INTERVAL_CLI0(x)			(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI0) << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0)
#define BITS_TSF_SYNC_INTERVAL_CLI0			(BIT_MASK_TSF_SYNC_INTERVAL_CLI0 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0)
#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x)		((x) & (~BITS_TSF_SYNC_INTERVAL_CLI0))
#define BIT_GET_TSF_SYNC_INTERVAL_CLI0(x)		(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI0) & BIT_MASK_TSF_SYNC_INTERVAL_CLI0)
#define BIT_SET_TSF_SYNC_INTERVAL_CLI0(x, v)		(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI0(x) | BIT_TSF_SYNC_INTERVAL_CLI0(v))

/* 2 REG_TSF_SYN_OFFSET2			(Offset 0x1528) */

#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3		16
#define BIT_MASK_TSF_SYNC_INTERVAL_CLI3		0xffff
#define BIT_TSF_SYNC_INTERVAL_CLI3(x)			(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI3) << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3)
#define BITS_TSF_SYNC_INTERVAL_CLI3			(BIT_MASK_TSF_SYNC_INTERVAL_CLI3 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3)
#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x)		((x) & (~BITS_TSF_SYNC_INTERVAL_CLI3))
#define BIT_GET_TSF_SYNC_INTERVAL_CLI3(x)		(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI3) & BIT_MASK_TSF_SYNC_INTERVAL_CLI3)
#define BIT_SET_TSF_SYNC_INTERVAL_CLI3(x, v)		(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI3(x) | BIT_TSF_SYNC_INTERVAL_CLI3(v))

#define BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2		0
#define BIT_MASK_TSF_SYNC_INTERVAL_CLI2		0xffff
#define BIT_TSF_SYNC_INTERVAL_CLI2(x)			(((x) & BIT_MASK_TSF_SYNC_INTERVAL_CLI2) << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2)
#define BITS_TSF_SYNC_INTERVAL_CLI2			(BIT_MASK_TSF_SYNC_INTERVAL_CLI2 << BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2)
#define BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x)		((x) & (~BITS_TSF_SYNC_INTERVAL_CLI2))
#define BIT_GET_TSF_SYNC_INTERVAL_CLI2(x)		(((x) >> BIT_SHIFT_TSF_SYNC_INTERVAL_CLI2) & BIT_MASK_TSF_SYNC_INTERVAL_CLI2)
#define BIT_SET_TSF_SYNC_INTERVAL_CLI2(x, v)		(BIT_CLEAR_TSF_SYNC_INTERVAL_CLI2(x) | BIT_TSF_SYNC_INTERVAL_CLI2(v))

/* 2 REG_TSF_SYN_COMPARE_VALUE_L		(Offset 0x1530) */

#define BIT_SHIFT_TSF_SYN_COMPARE_VALUE_L		0
#define BIT_MASK_TSF_SYN_COMPARE_VALUE_L		0xffffffffL
#define BIT_TSF_SYN_COMPARE_VALUE_L(x)			(((x) & BIT_MASK_TSF_SYN_COMPARE_VALUE_L) << BIT_SHIFT_TSF_SYN_COMPARE_VALUE_L)
#define BITS_TSF_SYN_COMPARE_VALUE_L			(BIT_MASK_TSF_SYN_COMPARE_VALUE_L << BIT_SHIFT_TSF_SYN_COMPARE_VALUE_L)
#define BIT_CLEAR_TSF_SYN_COMPARE_VALUE_L(x)		((x) & (~BITS_TSF_SYN_COMPARE_VALUE_L))
#define BIT_GET_TSF_SYN_COMPARE_VALUE_L(x)		(((x) >> BIT_SHIFT_TSF_SYN_COMPARE_VALUE_L) & BIT_MASK_TSF_SYN_COMPARE_VALUE_L)
#define BIT_SET_TSF_SYN_COMPARE_VALUE_L(x, v)		(BIT_CLEAR_TSF_SYN_COMPARE_VALUE_L(x) | BIT_TSF_SYN_COMPARE_VALUE_L(v))

/* 2 REG_TSF_SYN_COMPARE_VALUE_H		(Offset 0x1534) */

#define BIT_SHIFT_TSF_SYN_COMPARE_VALUE_H		0
#define BIT_MASK_TSF_SYN_COMPARE_VALUE_H		0xffffffffL
#define BIT_TSF_SYN_COMPARE_VALUE_H(x)			(((x) & BIT_MASK_TSF_SYN_COMPARE_VALUE_H) << BIT_SHIFT_TSF_SYN_COMPARE_VALUE_H)
#define BITS_TSF_SYN_COMPARE_VALUE_H			(BIT_MASK_TSF_SYN_COMPARE_VALUE_H << BIT_SHIFT_TSF_SYN_COMPARE_VALUE_H)
#define BIT_CLEAR_TSF_SYN_COMPARE_VALUE_H(x)		((x) & (~BITS_TSF_SYN_COMPARE_VALUE_H))
#define BIT_GET_TSF_SYN_COMPARE_VALUE_H(x)		(((x) >> BIT_SHIFT_TSF_SYN_COMPARE_VALUE_H) & BIT_MASK_TSF_SYN_COMPARE_VALUE_H)
#define BIT_SET_TSF_SYN_COMPARE_VALUE_H(x, v)		(BIT_CLEAR_TSF_SYN_COMPARE_VALUE_H(x) | BIT_TSF_SYN_COMPARE_VALUE_H(v))

/* 2 REG_SCHEDULER_COUNTER			(Offset 0x15D0) */

#define BIT_SHIFT_SCHEDULER_COUNTER			16
#define BIT_MASK_SCHEDULER_COUNTER			0xffff
#define BIT_SCHEDULER_COUNTER(x)			(((x) & BIT_MASK_SCHEDULER_COUNTER) << BIT_SHIFT_SCHEDULER_COUNTER)
#define BITS_SCHEDULER_COUNTER				(BIT_MASK_SCHEDULER_COUNTER << BIT_SHIFT_SCHEDULER_COUNTER)
#define BIT_CLEAR_SCHEDULER_COUNTER(x)			((x) & (~BITS_SCHEDULER_COUNTER))
#define BIT_GET_SCHEDULER_COUNTER(x)			(((x) >> BIT_SHIFT_SCHEDULER_COUNTER) & BIT_MASK_SCHEDULER_COUNTER)
#define BIT_SET_SCHEDULER_COUNTER(x, v)		(BIT_CLEAR_SCHEDULER_COUNTER(x) | BIT_SCHEDULER_COUNTER(v))

#define BIT_SCHEDULER_COUNTER_RST			BIT(8)

#define BIT_SHIFT_SCHEDULER_COUNTER_SEL		0
#define BIT_MASK_SCHEDULER_COUNTER_SEL			0xff
#define BIT_SCHEDULER_COUNTER_SEL(x)			(((x) & BIT_MASK_SCHEDULER_COUNTER_SEL) << BIT_SHIFT_SCHEDULER_COUNTER_SEL)
#define BITS_SCHEDULER_COUNTER_SEL			(BIT_MASK_SCHEDULER_COUNTER_SEL << BIT_SHIFT_SCHEDULER_COUNTER_SEL)
#define BIT_CLEAR_SCHEDULER_COUNTER_SEL(x)		((x) & (~BITS_SCHEDULER_COUNTER_SEL))
#define BIT_GET_SCHEDULER_COUNTER_SEL(x)		(((x) >> BIT_SHIFT_SCHEDULER_COUNTER_SEL) & BIT_MASK_SCHEDULER_COUNTER_SEL)
#define BIT_SET_SCHEDULER_COUNTER_SEL(x, v)		(BIT_CLEAR_SCHEDULER_COUNTER_SEL(x) | BIT_SCHEDULER_COUNTER_SEL(v))

/* 2 REG_BCN_PSR_RPT2			(Offset 0x1600) */

#define BIT_SHIFT_DTIM_CNT2				24
#define BIT_MASK_DTIM_CNT2				0xff
#define BIT_DTIM_CNT2(x)				(((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2)
#define BITS_DTIM_CNT2					(BIT_MASK_DTIM_CNT2 << BIT_SHIFT_DTIM_CNT2)
#define BIT_CLEAR_DTIM_CNT2(x)				((x) & (~BITS_DTIM_CNT2))
#define BIT_GET_DTIM_CNT2(x)				(((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2)
#define BIT_SET_DTIM_CNT2(x, v)			(BIT_CLEAR_DTIM_CNT2(x) | BIT_DTIM_CNT2(v))

#define BIT_SHIFT_DTIM_PERIOD2				16
#define BIT_MASK_DTIM_PERIOD2				0xff
#define BIT_DTIM_PERIOD2(x)				(((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2)
#define BITS_DTIM_PERIOD2				(BIT_MASK_DTIM_PERIOD2 << BIT_SHIFT_DTIM_PERIOD2)
#define BIT_CLEAR_DTIM_PERIOD2(x)			((x) & (~BITS_DTIM_PERIOD2))
#define BIT_GET_DTIM_PERIOD2(x)			(((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2)
#define BIT_SET_DTIM_PERIOD2(x, v)			(BIT_CLEAR_DTIM_PERIOD2(x) | BIT_DTIM_PERIOD2(v))

#define BIT_DTIM2					BIT(15)
#define BIT_TIM2					BIT(14)
#define BIT_RPT_VALID					BIT(13)

#define BIT_SHIFT_PS_AID_2				0
#define BIT_MASK_PS_AID_2				0x7ff
#define BIT_PS_AID_2(x)				(((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2)
#define BITS_PS_AID_2					(BIT_MASK_PS_AID_2 << BIT_SHIFT_PS_AID_2)
#define BIT_CLEAR_PS_AID_2(x)				((x) & (~BITS_PS_AID_2))
#define BIT_GET_PS_AID_2(x)				(((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2)
#define BIT_SET_PS_AID_2(x, v)				(BIT_CLEAR_PS_AID_2(x) | BIT_PS_AID_2(v))

/* 2 REG_BCN_PSR_RPT3			(Offset 0x1604) */

#define BIT_SHIFT_DTIM_CNT3				24
#define BIT_MASK_DTIM_CNT3				0xff
#define BIT_DTIM_CNT3(x)				(((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3)
#define BITS_DTIM_CNT3					(BIT_MASK_DTIM_CNT3 << BIT_SHIFT_DTIM_CNT3)
#define BIT_CLEAR_DTIM_CNT3(x)				((x) & (~BITS_DTIM_CNT3))
#define BIT_GET_DTIM_CNT3(x)				(((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3)
#define BIT_SET_DTIM_CNT3(x, v)			(BIT_CLEAR_DTIM_CNT3(x) | BIT_DTIM_CNT3(v))

#define BIT_SHIFT_DTIM_PERIOD3				16
#define BIT_MASK_DTIM_PERIOD3				0xff
#define BIT_DTIM_PERIOD3(x)				(((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3)
#define BITS_DTIM_PERIOD3				(BIT_MASK_DTIM_PERIOD3 << BIT_SHIFT_DTIM_PERIOD3)
#define BIT_CLEAR_DTIM_PERIOD3(x)			((x) & (~BITS_DTIM_PERIOD3))
#define BIT_GET_DTIM_PERIOD3(x)			(((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3)
#define BIT_SET_DTIM_PERIOD3(x, v)			(BIT_CLEAR_DTIM_PERIOD3(x) | BIT_DTIM_PERIOD3(v))

#define BIT_DTIM3					BIT(15)
#define BIT_TIM3					BIT(14)

#define BIT_SHIFT_PS_AID_3				0
#define BIT_MASK_PS_AID_3				0x7ff
#define BIT_PS_AID_3(x)				(((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3)
#define BITS_PS_AID_3					(BIT_MASK_PS_AID_3 << BIT_SHIFT_PS_AID_3)
#define BIT_CLEAR_PS_AID_3(x)				((x) & (~BITS_PS_AID_3))
#define BIT_GET_PS_AID_3(x)				(((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3)
#define BIT_SET_PS_AID_3(x, v)				(BIT_CLEAR_PS_AID_3(x) | BIT_PS_AID_3(v))

/* 2 REG_BCN_PSR_RPT4			(Offset 0x1608) */

#define BIT_SHIFT_DTIM_CNT4				24
#define BIT_MASK_DTIM_CNT4				0xff
#define BIT_DTIM_CNT4(x)				(((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4)
#define BITS_DTIM_CNT4					(BIT_MASK_DTIM_CNT4 << BIT_SHIFT_DTIM_CNT4)
#define BIT_CLEAR_DTIM_CNT4(x)				((x) & (~BITS_DTIM_CNT4))
#define BIT_GET_DTIM_CNT4(x)				(((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4)
#define BIT_SET_DTIM_CNT4(x, v)			(BIT_CLEAR_DTIM_CNT4(x) | BIT_DTIM_CNT4(v))

#define BIT_SHIFT_DTIM_PERIOD4				16
#define BIT_MASK_DTIM_PERIOD4				0xff
#define BIT_DTIM_PERIOD4(x)				(((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4)
#define BITS_DTIM_PERIOD4				(BIT_MASK_DTIM_PERIOD4 << BIT_SHIFT_DTIM_PERIOD4)
#define BIT_CLEAR_DTIM_PERIOD4(x)			((x) & (~BITS_DTIM_PERIOD4))
#define BIT_GET_DTIM_PERIOD4(x)			(((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4)
#define BIT_SET_DTIM_PERIOD4(x, v)			(BIT_CLEAR_DTIM_PERIOD4(x) | BIT_DTIM_PERIOD4(v))

#define BIT_DTIM4					BIT(15)
#define BIT_TIM4					BIT(14)

#define BIT_SHIFT_PS_AID_4				0
#define BIT_MASK_PS_AID_4				0x7ff
#define BIT_PS_AID_4(x)				(((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4)
#define BITS_PS_AID_4					(BIT_MASK_PS_AID_4 << BIT_SHIFT_PS_AID_4)
#define BIT_CLEAR_PS_AID_4(x)				((x) & (~BITS_PS_AID_4))
#define BIT_GET_PS_AID_4(x)				(((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4)
#define BIT_SET_PS_AID_4(x, v)				(BIT_CLEAR_PS_AID_4(x) | BIT_PS_AID_4(v))

/* 2 REG_A1_ADDR_MASK			(Offset 0x160C) */

#define BIT_SHIFT_A1_ADDR_MASK				0
#define BIT_MASK_A1_ADDR_MASK				0xffffffffL
#define BIT_A1_ADDR_MASK(x)				(((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK)
#define BITS_A1_ADDR_MASK				(BIT_MASK_A1_ADDR_MASK << BIT_SHIFT_A1_ADDR_MASK)
#define BIT_CLEAR_A1_ADDR_MASK(x)			((x) & (~BITS_A1_ADDR_MASK))
#define BIT_GET_A1_ADDR_MASK(x)			(((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK)
#define BIT_SET_A1_ADDR_MASK(x, v)			(BIT_CLEAR_A1_ADDR_MASK(x) | BIT_A1_ADDR_MASK(v))

/* 2 REG_RXPSF_CTRL				(Offset 0x1610) */

#define BIT_RXGCK_FIFOTHR_EN				BIT(28)

#define BIT_SHIFT_RXGCK_VHT_FIFOTHR			26
#define BIT_MASK_RXGCK_VHT_FIFOTHR			0x3
#define BIT_RXGCK_VHT_FIFOTHR(x)			(((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
#define BITS_RXGCK_VHT_FIFOTHR				(BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR)
#define BIT_CLEAR_RXGCK_VHT_FIFOTHR(x)			((x) & (~BITS_RXGCK_VHT_FIFOTHR))
#define BIT_GET_RXGCK_VHT_FIFOTHR(x)			(((x) >> BIT_SHIFT_RXGCK_VHT_FIFOTHR) & BIT_MASK_RXGCK_VHT_FIFOTHR)
#define BIT_SET_RXGCK_VHT_FIFOTHR(x, v)		(BIT_CLEAR_RXGCK_VHT_FIFOTHR(x) | BIT_RXGCK_VHT_FIFOTHR(v))

#define BIT_SHIFT_RXGCK_HT_FIFOTHR			24
#define BIT_MASK_RXGCK_HT_FIFOTHR			0x3
#define BIT_RXGCK_HT_FIFOTHR(x)			(((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR)
#define BITS_RXGCK_HT_FIFOTHR				(BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR)
#define BIT_CLEAR_RXGCK_HT_FIFOTHR(x)			((x) & (~BITS_RXGCK_HT_FIFOTHR))
#define BIT_GET_RXGCK_HT_FIFOTHR(x)			(((x) >> BIT_SHIFT_RXGCK_HT_FIFOTHR) & BIT_MASK_RXGCK_HT_FIFOTHR)
#define BIT_SET_RXGCK_HT_FIFOTHR(x, v)			(BIT_CLEAR_RXGCK_HT_FIFOTHR(x) | BIT_RXGCK_HT_FIFOTHR(v))

#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR			22
#define BIT_MASK_RXGCK_OFDM_FIFOTHR			0x3
#define BIT_RXGCK_OFDM_FIFOTHR(x)			(((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
#define BITS_RXGCK_OFDM_FIFOTHR			(BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)
#define BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x)		((x) & (~BITS_RXGCK_OFDM_FIFOTHR))
#define BIT_GET_RXGCK_OFDM_FIFOTHR(x)			(((x) >> BIT_SHIFT_RXGCK_OFDM_FIFOTHR) & BIT_MASK_RXGCK_OFDM_FIFOTHR)
#define BIT_SET_RXGCK_OFDM_FIFOTHR(x, v)		(BIT_CLEAR_RXGCK_OFDM_FIFOTHR(x) | BIT_RXGCK_OFDM_FIFOTHR(v))

#define BIT_SHIFT_RXGCK_CCK_FIFOTHR			20
#define BIT_MASK_RXGCK_CCK_FIFOTHR			0x3
#define BIT_RXGCK_CCK_FIFOTHR(x)			(((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
#define BITS_RXGCK_CCK_FIFOTHR				(BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR)
#define BIT_CLEAR_RXGCK_CCK_FIFOTHR(x)			((x) & (~BITS_RXGCK_CCK_FIFOTHR))
#define BIT_GET_RXGCK_CCK_FIFOTHR(x)			(((x) >> BIT_SHIFT_RXGCK_CCK_FIFOTHR) & BIT_MASK_RXGCK_CCK_FIFOTHR)
#define BIT_SET_RXGCK_CCK_FIFOTHR(x, v)		(BIT_CLEAR_RXGCK_CCK_FIFOTHR(x) | BIT_RXGCK_CCK_FIFOTHR(v))

#define BIT_SHIFT_RXGCK_ENTRY_DELAY			17
#define BIT_MASK_RXGCK_ENTRY_DELAY			0x7
#define BIT_RXGCK_ENTRY_DELAY(x)			(((x) & BIT_MASK_RXGCK_ENTRY_DELAY) << BIT_SHIFT_RXGCK_ENTRY_DELAY)
#define BITS_RXGCK_ENTRY_DELAY				(BIT_MASK_RXGCK_ENTRY_DELAY << BIT_SHIFT_RXGCK_ENTRY_DELAY)
#define BIT_CLEAR_RXGCK_ENTRY_DELAY(x)			((x) & (~BITS_RXGCK_ENTRY_DELAY))
#define BIT_GET_RXGCK_ENTRY_DELAY(x)			(((x) >> BIT_SHIFT_RXGCK_ENTRY_DELAY) & BIT_MASK_RXGCK_ENTRY_DELAY)
#define BIT_SET_RXGCK_ENTRY_DELAY(x, v)		(BIT_CLEAR_RXGCK_ENTRY_DELAY(x) | BIT_RXGCK_ENTRY_DELAY(v))

#define BIT_RXGCK_OFDMCCA_EN				BIT(16)

#define BIT_SHIFT_RXPSF_PKTLENTHR			13
#define BIT_MASK_RXPSF_PKTLENTHR			0x7
#define BIT_RXPSF_PKTLENTHR(x)				(((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR)
#define BITS_RXPSF_PKTLENTHR				(BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR)
#define BIT_CLEAR_RXPSF_PKTLENTHR(x)			((x) & (~BITS_RXPSF_PKTLENTHR))
#define BIT_GET_RXPSF_PKTLENTHR(x)			(((x) >> BIT_SHIFT_RXPSF_PKTLENTHR) & BIT_MASK_RXPSF_PKTLENTHR)
#define BIT_SET_RXPSF_PKTLENTHR(x, v)			(BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v))

#define BIT_RXPSF_CTRLEN				BIT(12)
#define BIT_RXPSF_VHTCHKEN				BIT(11)
#define BIT_RXPSF_HTCHKEN				BIT(10)
#define BIT_RXPSF_OFDMCHKEN				BIT(9)
#define BIT_RXPSF_CCKCHKEN				BIT(8)
#define BIT_RXPSF_OFDMRST				BIT(7)
#define BIT_RXPSF_CCKRST				BIT(6)
#define BIT_RXPSF_MHCHKEN				BIT(5)
#define BIT_RXPSF_CONT_ERRCHKEN			BIT(4)
#define BIT_RXPSF_ALL_ERRCHKEN				BIT(3)

#define BIT_SHIFT_RXPSF_ERRTHR				0
#define BIT_MASK_RXPSF_ERRTHR				0x7
#define BIT_RXPSF_ERRTHR(x)				(((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR)
#define BITS_RXPSF_ERRTHR				(BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR)
#define BIT_CLEAR_RXPSF_ERRTHR(x)			((x) & (~BITS_RXPSF_ERRTHR))
#define BIT_GET_RXPSF_ERRTHR(x)			(((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR)
#define BIT_SET_RXPSF_ERRTHR(x, v)			(BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v))

/* 2 REG_RXPSF_TYPE_CTRL			(Offset 0x1614) */

#define BIT_RXPSF_DATA15EN				BIT(31)
#define BIT_RXPSF_DATA14EN				BIT(30)
#define BIT_RXPSF_DATA13EN				BIT(29)
#define BIT_RXPSF_DATA12EN				BIT(28)
#define BIT_RXPSF_DATA11EN				BIT(27)
#define BIT_RXPSF_DATA10EN				BIT(26)
#define BIT_RXPSF_DATA9EN				BIT(25)
#define BIT_RXPSF_DATA8EN				BIT(24)
#define BIT_RXPSF_DATA7EN				BIT(23)
#define BIT_RXPSF_DATA6EN				BIT(22)
#define BIT_RXPSF_DATA5EN				BIT(21)
#define BIT_RXPSF_DATA4EN				BIT(20)
#define BIT_RXPSF_DATA3EN				BIT(19)
#define BIT_RXPSF_DATA2EN				BIT(18)
#define BIT_RXPSF_DATA1EN				BIT(17)
#define BIT_RXPSF_DATA0EN				BIT(16)
#define BIT_RXPSF_MGT15EN				BIT(15)
#define BIT_RXPSF_MGT14EN				BIT(14)
#define BIT_RXPSF_MGT13EN				BIT(13)
#define BIT_RXPSF_MGT12EN				BIT(12)
#define BIT_RXPSF_MGT11EN				BIT(11)
#define BIT_RXPSF_MGT10EN				BIT(10)
#define BIT_RXPSF_MGT9EN				BIT(9)
#define BIT_RXPSF_MGT8EN				BIT(8)
#define BIT_RXPSF_MGT7EN				BIT(7)
#define BIT_RXPSF_MGT6EN				BIT(6)
#define BIT_RXPSF_MGT5EN				BIT(5)
#define BIT_RXPSF_MGT4EN				BIT(4)
#define BIT_RXPSF_MGT3EN				BIT(3)
#define BIT_RXPSF_MGT2EN				BIT(2)
#define BIT_RXPSF_MGT1EN				BIT(1)
#define BIT_RXPSF_MGT0EN				BIT(0)

/* 2 REG_WAIT_PHYSTS_CTL			(Offset 0x1618) */

#define BIT_BB_RST_RESP				BIT(7)
#define BIT_CCA_SPOOFING_EN				BIT(6)
#define BIT_RDRDY_NUM_CHK_EN				BIT(5)
#define BIT_WAIT_PHYSTS_EN				BIT(4)

#define BIT_SHIFT_WAIT_PHYSTS_TIME			0
#define BIT_MASK_WAIT_PHYSTS_TIME			0xf
#define BIT_WAIT_PHYSTS_TIME(x)			(((x) & BIT_MASK_WAIT_PHYSTS_TIME) << BIT_SHIFT_WAIT_PHYSTS_TIME)
#define BITS_WAIT_PHYSTS_TIME				(BIT_MASK_WAIT_PHYSTS_TIME << BIT_SHIFT_WAIT_PHYSTS_TIME)
#define BIT_CLEAR_WAIT_PHYSTS_TIME(x)			((x) & (~BITS_WAIT_PHYSTS_TIME))
#define BIT_GET_WAIT_PHYSTS_TIME(x)			(((x) >> BIT_SHIFT_WAIT_PHYSTS_TIME) & BIT_MASK_WAIT_PHYSTS_TIME)
#define BIT_SET_WAIT_PHYSTS_TIME(x, v)			(BIT_CLEAR_WAIT_PHYSTS_TIME(x) | BIT_WAIT_PHYSTS_TIME(v))

/* 2 REG_MACID2				(Offset 0x1620) */

#define BIT_SHIFT_MACID2_V1				0
#define BIT_MASK_MACID2_V1				0xffffffffL
#define BIT_MACID2_V1(x)				(((x) & BIT_MASK_MACID2_V1) << BIT_SHIFT_MACID2_V1)
#define BITS_MACID2_V1					(BIT_MASK_MACID2_V1 << BIT_SHIFT_MACID2_V1)
#define BIT_CLEAR_MACID2_V1(x)				((x) & (~BITS_MACID2_V1))
#define BIT_GET_MACID2_V1(x)				(((x) >> BIT_SHIFT_MACID2_V1) & BIT_MASK_MACID2_V1)
#define BIT_SET_MACID2_V1(x, v)			(BIT_CLEAR_MACID2_V1(x) | BIT_MACID2_V1(v))

/* 2 REG_MACID2_H				(Offset 0x1624) */

#define BIT_SHIFT_MACID2_H_V1				0
#define BIT_MASK_MACID2_H_V1				0xffff
#define BIT_MACID2_H_V1(x)				(((x) & BIT_MASK_MACID2_H_V1) << BIT_SHIFT_MACID2_H_V1)
#define BITS_MACID2_H_V1				(BIT_MASK_MACID2_H_V1 << BIT_SHIFT_MACID2_H_V1)
#define BIT_CLEAR_MACID2_H_V1(x)			((x) & (~BITS_MACID2_H_V1))
#define BIT_GET_MACID2_H_V1(x)				(((x) >> BIT_SHIFT_MACID2_H_V1) & BIT_MASK_MACID2_H_V1)
#define BIT_SET_MACID2_H_V1(x, v)			(BIT_CLEAR_MACID2_H_V1(x) | BIT_MACID2_H_V1(v))

/* 2 REG_BSSID2				(Offset 0x1628) */

#define BIT_SHIFT_BSSID2_V1				0
#define BIT_MASK_BSSID2_V1				0xffffffffL
#define BIT_BSSID2_V1(x)				(((x) & BIT_MASK_BSSID2_V1) << BIT_SHIFT_BSSID2_V1)
#define BITS_BSSID2_V1					(BIT_MASK_BSSID2_V1 << BIT_SHIFT_BSSID2_V1)
#define BIT_CLEAR_BSSID2_V1(x)				((x) & (~BITS_BSSID2_V1))
#define BIT_GET_BSSID2_V1(x)				(((x) >> BIT_SHIFT_BSSID2_V1) & BIT_MASK_BSSID2_V1)
#define BIT_SET_BSSID2_V1(x, v)			(BIT_CLEAR_BSSID2_V1(x) | BIT_BSSID2_V1(v))

/* 2 REG_BSSID2_H				(Offset 0x162C) */

#define BIT_SHIFT_BSSID2_H_V1				0
#define BIT_MASK_BSSID2_H_V1				0xffff
#define BIT_BSSID2_H_V1(x)				(((x) & BIT_MASK_BSSID2_H_V1) << BIT_SHIFT_BSSID2_H_V1)
#define BITS_BSSID2_H_V1				(BIT_MASK_BSSID2_H_V1 << BIT_SHIFT_BSSID2_H_V1)
#define BIT_CLEAR_BSSID2_H_V1(x)			((x) & (~BITS_BSSID2_H_V1))
#define BIT_GET_BSSID2_H_V1(x)				(((x) >> BIT_SHIFT_BSSID2_H_V1) & BIT_MASK_BSSID2_H_V1)
#define BIT_SET_BSSID2_H_V1(x, v)			(BIT_CLEAR_BSSID2_H_V1(x) | BIT_BSSID2_H_V1(v))

/* 2 REG_MACID3				(Offset 0x1630) */

#define BIT_SHIFT_MACID3_V1				0
#define BIT_MASK_MACID3_V1				0xffffffffL
#define BIT_MACID3_V1(x)				(((x) & BIT_MASK_MACID3_V1) << BIT_SHIFT_MACID3_V1)
#define BITS_MACID3_V1					(BIT_MASK_MACID3_V1 << BIT_SHIFT_MACID3_V1)
#define BIT_CLEAR_MACID3_V1(x)				((x) & (~BITS_MACID3_V1))
#define BIT_GET_MACID3_V1(x)				(((x) >> BIT_SHIFT_MACID3_V1) & BIT_MASK_MACID3_V1)
#define BIT_SET_MACID3_V1(x, v)			(BIT_CLEAR_MACID3_V1(x) | BIT_MACID3_V1(v))

/* 2 REG_MACID3_H				(Offset 0x1634) */

#define BIT_SHIFT_MACID3_H_V1				0
#define BIT_MASK_MACID3_H_V1				0xffff
#define BIT_MACID3_H_V1(x)				(((x) & BIT_MASK_MACID3_H_V1) << BIT_SHIFT_MACID3_H_V1)
#define BITS_MACID3_H_V1				(BIT_MASK_MACID3_H_V1 << BIT_SHIFT_MACID3_H_V1)
#define BIT_CLEAR_MACID3_H_V1(x)			((x) & (~BITS_MACID3_H_V1))
#define BIT_GET_MACID3_H_V1(x)				(((x) >> BIT_SHIFT_MACID3_H_V1) & BIT_MASK_MACID3_H_V1)
#define BIT_SET_MACID3_H_V1(x, v)			(BIT_CLEAR_MACID3_H_V1(x) | BIT_MACID3_H_V1(v))

/* 2 REG_BSSID3				(Offset 0x1638) */

#define BIT_SHIFT_BSSID3_V1				0
#define BIT_MASK_BSSID3_V1				0xffffffffL
#define BIT_BSSID3_V1(x)				(((x) & BIT_MASK_BSSID3_V1) << BIT_SHIFT_BSSID3_V1)
#define BITS_BSSID3_V1					(BIT_MASK_BSSID3_V1 << BIT_SHIFT_BSSID3_V1)
#define BIT_CLEAR_BSSID3_V1(x)				((x) & (~BITS_BSSID3_V1))
#define BIT_GET_BSSID3_V1(x)				(((x) >> BIT_SHIFT_BSSID3_V1) & BIT_MASK_BSSID3_V1)
#define BIT_SET_BSSID3_V1(x, v)			(BIT_CLEAR_BSSID3_V1(x) | BIT_BSSID3_V1(v))

/* 2 REG_BSSID3_H				(Offset 0x163C) */

#define BIT_SHIFT_BSSID3_H_V1				0
#define BIT_MASK_BSSID3_H_V1				0xffff
#define BIT_BSSID3_H_V1(x)				(((x) & BIT_MASK_BSSID3_H_V1) << BIT_SHIFT_BSSID3_H_V1)
#define BITS_BSSID3_H_V1				(BIT_MASK_BSSID3_H_V1 << BIT_SHIFT_BSSID3_H_V1)
#define BIT_CLEAR_BSSID3_H_V1(x)			((x) & (~BITS_BSSID3_H_V1))
#define BIT_GET_BSSID3_H_V1(x)				(((x) >> BIT_SHIFT_BSSID3_H_V1) & BIT_MASK_BSSID3_H_V1)
#define BIT_SET_BSSID3_H_V1(x, v)			(BIT_CLEAR_BSSID3_H_V1(x) | BIT_BSSID3_H_V1(v))

/* 2 REG_MACID4				(Offset 0x1640) */

#define BIT_SHIFT_MACID4_V1				0
#define BIT_MASK_MACID4_V1				0xffffffffL
#define BIT_MACID4_V1(x)				(((x) & BIT_MASK_MACID4_V1) << BIT_SHIFT_MACID4_V1)
#define BITS_MACID4_V1					(BIT_MASK_MACID4_V1 << BIT_SHIFT_MACID4_V1)
#define BIT_CLEAR_MACID4_V1(x)				((x) & (~BITS_MACID4_V1))
#define BIT_GET_MACID4_V1(x)				(((x) >> BIT_SHIFT_MACID4_V1) & BIT_MASK_MACID4_V1)
#define BIT_SET_MACID4_V1(x, v)			(BIT_CLEAR_MACID4_V1(x) | BIT_MACID4_V1(v))

/* 2 REG_MACID4_H				(Offset 0x1644) */

#define BIT_SHIFT_MACID4_H_V1				0
#define BIT_MASK_MACID4_H_V1				0xffff
#define BIT_MACID4_H_V1(x)				(((x) & BIT_MASK_MACID4_H_V1) << BIT_SHIFT_MACID4_H_V1)
#define BITS_MACID4_H_V1				(BIT_MASK_MACID4_H_V1 << BIT_SHIFT_MACID4_H_V1)
#define BIT_CLEAR_MACID4_H_V1(x)			((x) & (~BITS_MACID4_H_V1))
#define BIT_GET_MACID4_H_V1(x)				(((x) >> BIT_SHIFT_MACID4_H_V1) & BIT_MASK_MACID4_H_V1)
#define BIT_SET_MACID4_H_V1(x, v)			(BIT_CLEAR_MACID4_H_V1(x) | BIT_MACID4_H_V1(v))

/* 2 REG_BSSID4				(Offset 0x1648) */

#define BIT_SHIFT_BSSID4_V1				0
#define BIT_MASK_BSSID4_V1				0xffffffffL
#define BIT_BSSID4_V1(x)				(((x) & BIT_MASK_BSSID4_V1) << BIT_SHIFT_BSSID4_V1)
#define BITS_BSSID4_V1					(BIT_MASK_BSSID4_V1 << BIT_SHIFT_BSSID4_V1)
#define BIT_CLEAR_BSSID4_V1(x)				((x) & (~BITS_BSSID4_V1))
#define BIT_GET_BSSID4_V1(x)				(((x) >> BIT_SHIFT_BSSID4_V1) & BIT_MASK_BSSID4_V1)
#define BIT_SET_BSSID4_V1(x, v)			(BIT_CLEAR_BSSID4_V1(x) | BIT_BSSID4_V1(v))

/* 2 REG_BSSID4_H				(Offset 0x164C) */

#define BIT_SHIFT_BSSID4_H_V1				0
#define BIT_MASK_BSSID4_H_V1				0xffff
#define BIT_BSSID4_H_V1(x)				(((x) & BIT_MASK_BSSID4_H_V1) << BIT_SHIFT_BSSID4_H_V1)
#define BITS_BSSID4_H_V1				(BIT_MASK_BSSID4_H_V1 << BIT_SHIFT_BSSID4_H_V1)
#define BIT_CLEAR_BSSID4_H_V1(x)			((x) & (~BITS_BSSID4_H_V1))
#define BIT_GET_BSSID4_H_V1(x)				(((x) >> BIT_SHIFT_BSSID4_H_V1) & BIT_MASK_BSSID4_H_V1)
#define BIT_SET_BSSID4_H_V1(x, v)			(BIT_CLEAR_BSSID4_H_V1(x) | BIT_BSSID4_H_V1(v))

/* 2 REG_NOA_REPORT				(Offset 0x1650) */

#define BIT_SHIFT_NOA_RPT				0
#define BIT_MASK_NOA_RPT				0xffffffffL
#define BIT_NOA_RPT(x)					(((x) & BIT_MASK_NOA_RPT) << BIT_SHIFT_NOA_RPT)
#define BITS_NOA_RPT					(BIT_MASK_NOA_RPT << BIT_SHIFT_NOA_RPT)
#define BIT_CLEAR_NOA_RPT(x)				((x) & (~BITS_NOA_RPT))
#define BIT_GET_NOA_RPT(x)				(((x) >> BIT_SHIFT_NOA_RPT) & BIT_MASK_NOA_RPT)
#define BIT_SET_NOA_RPT(x, v)				(BIT_CLEAR_NOA_RPT(x) | BIT_NOA_RPT(v))

/* 2 REG_NOA_REPORT_1			(Offset 0x1654) */

#define BIT_SHIFT_NOA_RPT_1				0
#define BIT_MASK_NOA_RPT_1				0xffffffffL
#define BIT_NOA_RPT_1(x)				(((x) & BIT_MASK_NOA_RPT_1) << BIT_SHIFT_NOA_RPT_1)
#define BITS_NOA_RPT_1					(BIT_MASK_NOA_RPT_1 << BIT_SHIFT_NOA_RPT_1)
#define BIT_CLEAR_NOA_RPT_1(x)				((x) & (~BITS_NOA_RPT_1))
#define BIT_GET_NOA_RPT_1(x)				(((x) >> BIT_SHIFT_NOA_RPT_1) & BIT_MASK_NOA_RPT_1)
#define BIT_SET_NOA_RPT_1(x, v)			(BIT_CLEAR_NOA_RPT_1(x) | BIT_NOA_RPT_1(v))

/* 2 REG_NOA_REPORT_2			(Offset 0x1658) */

#define BIT_SHIFT_NOA_RPT_2				0
#define BIT_MASK_NOA_RPT_2				0xffffffffL
#define BIT_NOA_RPT_2(x)				(((x) & BIT_MASK_NOA_RPT_2) << BIT_SHIFT_NOA_RPT_2)
#define BITS_NOA_RPT_2					(BIT_MASK_NOA_RPT_2 << BIT_SHIFT_NOA_RPT_2)
#define BIT_CLEAR_NOA_RPT_2(x)				((x) & (~BITS_NOA_RPT_2))
#define BIT_GET_NOA_RPT_2(x)				(((x) >> BIT_SHIFT_NOA_RPT_2) & BIT_MASK_NOA_RPT_2)
#define BIT_SET_NOA_RPT_2(x, v)			(BIT_CLEAR_NOA_RPT_2(x) | BIT_NOA_RPT_2(v))

/* 2 REG_NOA_REPORT_3			(Offset 0x165C) */

#define BIT_SHIFT_NOA_RPT_3				0
#define BIT_MASK_NOA_RPT_3				0xff
#define BIT_NOA_RPT_3(x)				(((x) & BIT_MASK_NOA_RPT_3) << BIT_SHIFT_NOA_RPT_3)
#define BITS_NOA_RPT_3					(BIT_MASK_NOA_RPT_3 << BIT_SHIFT_NOA_RPT_3)
#define BIT_CLEAR_NOA_RPT_3(x)				((x) & (~BITS_NOA_RPT_3))
#define BIT_GET_NOA_RPT_3(x)				(((x) >> BIT_SHIFT_NOA_RPT_3) & BIT_MASK_NOA_RPT_3)
#define BIT_SET_NOA_RPT_3(x, v)			(BIT_CLEAR_NOA_RPT_3(x) | BIT_NOA_RPT_3(v))

/* 2 REG_PWRBIT_SETTING			(Offset 0x1660) */

#define BIT_CLI3_PWRBIT_OW_EN				BIT(7)
#define BIT_CLI3_PWR_ST				BIT(6)
#define BIT_CLI2_PWRBIT_OW_EN				BIT(5)
#define BIT_CLI2_PWR_ST				BIT(4)
#define BIT_CLI1_PWRBIT_OW_EN				BIT(3)
#define BIT_CLI1_PWR_ST				BIT(2)
#define BIT_CLI0_PWRBIT_OW_EN				BIT(1)
#define BIT_CLI0_PWR_ST				BIT(0)

/* 2 REG_GENERAL_OPTION			(Offset 0x1664) */

#define BIT_EXT_DBGSEL					BIT(6)
#define BIT_TXSERV_FIELD_SEL				BIT(2)

/* 2 REG_RXAI_CTRL				(Offset 0x1668) */

#define BIT_RXAI_INFO_RST				BIT(7)
#define BIT_RXAI_PRTCT_REL				BIT(6)
#define BIT_RXAI_PRTCT_VIO				BIT(5)
#define BIT_RXAI_PRTCT_SEL				BIT(2)
#define BIT_RXAI_AGG_CHKEN				BIT(1)
#define BIT_RXAI_ADDR_CHKEN				BIT(0)

/* 2 REG_CSI_RRSR				(Offset 0x1678) */

#define BIT_CSI_LDPC_EN				BIT(29)
#define BIT_CSI_STBC_EN				BIT(28)

#define BIT_SHIFT_CSI_RRSC_BITMAP			4
#define BIT_MASK_CSI_RRSC_BITMAP			0xffffff
#define BIT_CSI_RRSC_BITMAP(x)				(((x) & BIT_MASK_CSI_RRSC_BITMAP) << BIT_SHIFT_CSI_RRSC_BITMAP)
#define BITS_CSI_RRSC_BITMAP				(BIT_MASK_CSI_RRSC_BITMAP << BIT_SHIFT_CSI_RRSC_BITMAP)
#define BIT_CLEAR_CSI_RRSC_BITMAP(x)			((x) & (~BITS_CSI_RRSC_BITMAP))
#define BIT_GET_CSI_RRSC_BITMAP(x)			(((x) >> BIT_SHIFT_CSI_RRSC_BITMAP) & BIT_MASK_CSI_RRSC_BITMAP)
#define BIT_SET_CSI_RRSC_BITMAP(x, v)			(BIT_CLEAR_CSI_RRSC_BITMAP(x) | BIT_CSI_RRSC_BITMAP(v))

#define BIT_SHIFT_OFDM_LEN_TH_V1			0
#define BIT_MASK_OFDM_LEN_TH_V1			0xf
#define BIT_OFDM_LEN_TH_V1(x)				(((x) & BIT_MASK_OFDM_LEN_TH_V1) << BIT_SHIFT_OFDM_LEN_TH_V1)
#define BITS_OFDM_LEN_TH_V1				(BIT_MASK_OFDM_LEN_TH_V1 << BIT_SHIFT_OFDM_LEN_TH_V1)
#define BIT_CLEAR_OFDM_LEN_TH_V1(x)			((x) & (~BITS_OFDM_LEN_TH_V1))
#define BIT_GET_OFDM_LEN_TH_V1(x)			(((x) >> BIT_SHIFT_OFDM_LEN_TH_V1) & BIT_MASK_OFDM_LEN_TH_V1)
#define BIT_SET_OFDM_LEN_TH_V1(x, v)			(BIT_CLEAR_OFDM_LEN_TH_V1(x) | BIT_OFDM_LEN_TH_V1(v))

/* 2 REG_MU_BF_OPTION			(Offset 0x167C) */

#define BIT_WMAC_RESP_NONSTA1_DIS			BIT(7)

#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL		1
#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL			0x7
#define BIT_WMAC_MU_BFEE_PORT_SEL(x)			(((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL)
#define BITS_WMAC_MU_BFEE_PORT_SEL			(BIT_MASK_WMAC_MU_BFEE_PORT_SEL << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL)
#define BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x)		((x) & (~BITS_WMAC_MU_BFEE_PORT_SEL))
#define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x)		(((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL)
#define BIT_SET_WMAC_MU_BFEE_PORT_SEL(x, v)		(BIT_CLEAR_WMAC_MU_BFEE_PORT_SEL(x) | BIT_WMAC_MU_BFEE_PORT_SEL(v))

#define BIT_WMAC_MU_BFEE_DIS				BIT(0)

/* 2 REG_WMAC_PAUSE_BB_CLR_TH		(Offset 0x167D) */

#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH			0
#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH			0xff
#define BIT_WMAC_PAUSE_BB_CLR_TH(x)			(((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH)
#define BITS_WMAC_PAUSE_BB_CLR_TH			(BIT_MASK_WMAC_PAUSE_BB_CLR_TH << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH)
#define BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x)		((x) & (~BITS_WMAC_PAUSE_BB_CLR_TH))
#define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x)		(((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH)
#define BIT_SET_WMAC_PAUSE_BB_CLR_TH(x, v)		(BIT_CLEAR_WMAC_PAUSE_BB_CLR_TH(x) | BIT_WMAC_PAUSE_BB_CLR_TH(v))

/* 2 REG_WMAC_ARB_CLR			(Offset 0x167E) */

#define BIT_ARB_HW_ADAPT_EN				BIT(7)
#define BIT_ARB_SW_EN					BIT(6)

#define BIT_SHIFT_ARB_SW_STATE				0
#define BIT_MASK_ARB_SW_STATE				0x3f
#define BIT_ARB_SW_STATE(x)				(((x) & BIT_MASK_ARB_SW_STATE) << BIT_SHIFT_ARB_SW_STATE)
#define BITS_ARB_SW_STATE				(BIT_MASK_ARB_SW_STATE << BIT_SHIFT_ARB_SW_STATE)
#define BIT_CLEAR_ARB_SW_STATE(x)			((x) & (~BITS_ARB_SW_STATE))
#define BIT_GET_ARB_SW_STATE(x)			(((x) >> BIT_SHIFT_ARB_SW_STATE) & BIT_MASK_ARB_SW_STATE)
#define BIT_SET_ARB_SW_STATE(x, v)			(BIT_CLEAR_ARB_SW_STATE(x) | BIT_ARB_SW_STATE(v))

/* 2 REG_WMAC_MU_OPTION			(Offset 0x167F) */

#define BIT_WMAC_NOCHK_BFPOLL_BMP			BIT(7)

#define BIT_SHIFT_WMAC_CSI_PARA_RDY_DLYCNT		0
#define BIT_MASK_WMAC_CSI_PARA_RDY_DLYCNT		0x1f
#define BIT_WMAC_CSI_PARA_RDY_DLYCNT(x)		(((x) & BIT_MASK_WMAC_CSI_PARA_RDY_DLYCNT) << BIT_SHIFT_WMAC_CSI_PARA_RDY_DLYCNT)
#define BITS_WMAC_CSI_PARA_RDY_DLYCNT			(BIT_MASK_WMAC_CSI_PARA_RDY_DLYCNT << BIT_SHIFT_WMAC_CSI_PARA_RDY_DLYCNT)
#define BIT_CLEAR_WMAC_CSI_PARA_RDY_DLYCNT(x)		((x) & (~BITS_WMAC_CSI_PARA_RDY_DLYCNT))
#define BIT_GET_WMAC_CSI_PARA_RDY_DLYCNT(x)		(((x) >> BIT_SHIFT_WMAC_CSI_PARA_RDY_DLYCNT) & BIT_MASK_WMAC_CSI_PARA_RDY_DLYCNT)
#define BIT_SET_WMAC_CSI_PARA_RDY_DLYCNT(x, v)	(BIT_CLEAR_WMAC_CSI_PARA_RDY_DLYCNT(x) | BIT_WMAC_CSI_PARA_RDY_DLYCNT(v))

/* 2 REG_WMAC_MU_BF_CTL			(Offset 0x1680) */

#define BIT_WMAC_INVLD_BFPRT_CHK			BIT(15)
#define BIT_WMAC_RETXBFRPTSEQ_UPD			BIT(14)

#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL			12
#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL			0x3
#define BIT_WMAC_MU_BFRPTSEG_SEL(x)			(((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL)
#define BITS_WMAC_MU_BFRPTSEG_SEL			(BIT_MASK_WMAC_MU_BFRPTSEG_SEL << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL)
#define BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x)		((x) & (~BITS_WMAC_MU_BFRPTSEG_SEL))
#define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x)		(((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL)
#define BIT_SET_WMAC_MU_BFRPTSEG_SEL(x, v)		(BIT_CLEAR_WMAC_MU_BFRPTSEG_SEL(x) | BIT_WMAC_MU_BFRPTSEG_SEL(v))

#define BIT_SHIFT_WMAC_MU_BF_MYAID			0
#define BIT_MASK_WMAC_MU_BF_MYAID			0xfff
#define BIT_WMAC_MU_BF_MYAID(x)			(((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID)
#define BITS_WMAC_MU_BF_MYAID				(BIT_MASK_WMAC_MU_BF_MYAID << BIT_SHIFT_WMAC_MU_BF_MYAID)
#define BIT_CLEAR_WMAC_MU_BF_MYAID(x)			((x) & (~BITS_WMAC_MU_BF_MYAID))
#define BIT_GET_WMAC_MU_BF_MYAID(x)			(((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID)
#define BIT_SET_WMAC_MU_BF_MYAID(x, v)			(BIT_CLEAR_WMAC_MU_BF_MYAID(x) | BIT_WMAC_MU_BF_MYAID(v))

/* 2 REG_WMAC_MU_BFRPT_PARA			(Offset 0x1682) */

#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1		13
#define BIT_MASK_BFRPT_PARA_USERID_SEL_V1		0x7
#define BIT_BFRPT_PARA_USERID_SEL_V1(x)		(((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1) << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1)
#define BITS_BFRPT_PARA_USERID_SEL_V1			(BIT_MASK_BFRPT_PARA_USERID_SEL_V1 << BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1)
#define BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x)		((x) & (~BITS_BFRPT_PARA_USERID_SEL_V1))
#define BIT_GET_BFRPT_PARA_USERID_SEL_V1(x)		(((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_V1) & BIT_MASK_BFRPT_PARA_USERID_SEL_V1)
#define BIT_SET_BFRPT_PARA_USERID_SEL_V1(x, v)	(BIT_CLEAR_BFRPT_PARA_USERID_SEL_V1(x) | BIT_BFRPT_PARA_USERID_SEL_V1(v))

#define BIT_SHIFT_BFRPT_PARA_V1			0
#define BIT_MASK_BFRPT_PARA_V1				0x1fff
#define BIT_BFRPT_PARA_V1(x)				(((x) & BIT_MASK_BFRPT_PARA_V1) << BIT_SHIFT_BFRPT_PARA_V1)
#define BITS_BFRPT_PARA_V1				(BIT_MASK_BFRPT_PARA_V1 << BIT_SHIFT_BFRPT_PARA_V1)
#define BIT_CLEAR_BFRPT_PARA_V1(x)			((x) & (~BITS_BFRPT_PARA_V1))
#define BIT_GET_BFRPT_PARA_V1(x)			(((x) >> BIT_SHIFT_BFRPT_PARA_V1) & BIT_MASK_BFRPT_PARA_V1)
#define BIT_SET_BFRPT_PARA_V1(x, v)			(BIT_CLEAR_BFRPT_PARA_V1(x) | BIT_BFRPT_PARA_V1(v))

/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2		(Offset 0x1684) */

#define BIT_STATUS_BFEE2				BIT(10)
#define BIT_WMAC_MU_BFEE2_EN				BIT(9)

#define BIT_SHIFT_WMAC_MU_BFEE2_AID			0
#define BIT_MASK_WMAC_MU_BFEE2_AID			0x1ff
#define BIT_WMAC_MU_BFEE2_AID(x)			(((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID)
#define BITS_WMAC_MU_BFEE2_AID				(BIT_MASK_WMAC_MU_BFEE2_AID << BIT_SHIFT_WMAC_MU_BFEE2_AID)
#define BIT_CLEAR_WMAC_MU_BFEE2_AID(x)			((x) & (~BITS_WMAC_MU_BFEE2_AID))
#define BIT_GET_WMAC_MU_BFEE2_AID(x)			(((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID)
#define BIT_SET_WMAC_MU_BFEE2_AID(x, v)		(BIT_CLEAR_WMAC_MU_BFEE2_AID(x) | BIT_WMAC_MU_BFEE2_AID(v))

/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3		(Offset 0x1686) */

#define BIT_STATUS_BFEE3				BIT(10)
#define BIT_WMAC_MU_BFEE3_EN				BIT(9)

#define BIT_SHIFT_WMAC_MU_BFEE3_AID			0
#define BIT_MASK_WMAC_MU_BFEE3_AID			0x1ff
#define BIT_WMAC_MU_BFEE3_AID(x)			(((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID)
#define BITS_WMAC_MU_BFEE3_AID				(BIT_MASK_WMAC_MU_BFEE3_AID << BIT_SHIFT_WMAC_MU_BFEE3_AID)
#define BIT_CLEAR_WMAC_MU_BFEE3_AID(x)			((x) & (~BITS_WMAC_MU_BFEE3_AID))
#define BIT_GET_WMAC_MU_BFEE3_AID(x)			(((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID)
#define BIT_SET_WMAC_MU_BFEE3_AID(x, v)		(BIT_CLEAR_WMAC_MU_BFEE3_AID(x) | BIT_WMAC_MU_BFEE3_AID(v))

/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4		(Offset 0x1688) */

#define BIT_STATUS_BFEE4				BIT(10)
#define BIT_WMAC_MU_BFEE4_EN				BIT(9)

#define BIT_SHIFT_WMAC_MU_BFEE4_AID			0
#define BIT_MASK_WMAC_MU_BFEE4_AID			0x1ff
#define BIT_WMAC_MU_BFEE4_AID(x)			(((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID)
#define BITS_WMAC_MU_BFEE4_AID				(BIT_MASK_WMAC_MU_BFEE4_AID << BIT_SHIFT_WMAC_MU_BFEE4_AID)
#define BIT_CLEAR_WMAC_MU_BFEE4_AID(x)			((x) & (~BITS_WMAC_MU_BFEE4_AID))
#define BIT_GET_WMAC_MU_BFEE4_AID(x)			(((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID)
#define BIT_SET_WMAC_MU_BFEE4_AID(x, v)		(BIT_CLEAR_WMAC_MU_BFEE4_AID(x) | BIT_WMAC_MU_BFEE4_AID(v))

/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5		(Offset 0x168A) */

#define BIT_BIT_STATUS_BFEE5				BIT(10)
#define BIT_WMAC_MU_BFEE5_EN				BIT(9)

#define BIT_SHIFT_WMAC_MU_BFEE5_AID			0
#define BIT_MASK_WMAC_MU_BFEE5_AID			0x1ff
#define BIT_WMAC_MU_BFEE5_AID(x)			(((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID)
#define BITS_WMAC_MU_BFEE5_AID				(BIT_MASK_WMAC_MU_BFEE5_AID << BIT_SHIFT_WMAC_MU_BFEE5_AID)
#define BIT_CLEAR_WMAC_MU_BFEE5_AID(x)			((x) & (~BITS_WMAC_MU_BFEE5_AID))
#define BIT_GET_WMAC_MU_BFEE5_AID(x)			(((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID)
#define BIT_SET_WMAC_MU_BFEE5_AID(x, v)		(BIT_CLEAR_WMAC_MU_BFEE5_AID(x) | BIT_WMAC_MU_BFEE5_AID(v))

/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6		(Offset 0x168C) */

#define BIT_STATUS_BFEE6				BIT(10)
#define BIT_WMAC_MU_BFEE6_EN				BIT(9)

#define BIT_SHIFT_WMAC_MU_BFEE6_AID			0
#define BIT_MASK_WMAC_MU_BFEE6_AID			0x1ff
#define BIT_WMAC_MU_BFEE6_AID(x)			(((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID)
#define BITS_WMAC_MU_BFEE6_AID				(BIT_MASK_WMAC_MU_BFEE6_AID << BIT_SHIFT_WMAC_MU_BFEE6_AID)
#define BIT_CLEAR_WMAC_MU_BFEE6_AID(x)			((x) & (~BITS_WMAC_MU_BFEE6_AID))
#define BIT_GET_WMAC_MU_BFEE6_AID(x)			(((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID)
#define BIT_SET_WMAC_MU_BFEE6_AID(x, v)		(BIT_CLEAR_WMAC_MU_BFEE6_AID(x) | BIT_WMAC_MU_BFEE6_AID(v))

/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7		(Offset 0x168E) */

#define BIT_STATUS_BFEE7				BIT(10)
#define BIT_WMAC_MU_BFEE7_EN				BIT(9)

#define BIT_SHIFT_WMAC_MU_BFEE7_AID			0
#define BIT_MASK_WMAC_MU_BFEE7_AID			0x1ff
#define BIT_WMAC_MU_BFEE7_AID(x)			(((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID)
#define BITS_WMAC_MU_BFEE7_AID				(BIT_MASK_WMAC_MU_BFEE7_AID << BIT_SHIFT_WMAC_MU_BFEE7_AID)
#define BIT_CLEAR_WMAC_MU_BFEE7_AID(x)			((x) & (~BITS_WMAC_MU_BFEE7_AID))
#define BIT_GET_WMAC_MU_BFEE7_AID(x)			(((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID)
#define BIT_SET_WMAC_MU_BFEE7_AID(x, v)		(BIT_CLEAR_WMAC_MU_BFEE7_AID(x) | BIT_WMAC_MU_BFEE7_AID(v))

/* 2 REG_WMAC_BB_STOP_RX_COUNTER		(Offset 0x1690) */

#define BIT_RST_ALL_COUNTER				BIT(31)

#define BIT_SHIFT_ABORT_RX_VBON_COUNTER		16
#define BIT_MASK_ABORT_RX_VBON_COUNTER			0xff
#define BIT_ABORT_RX_VBON_COUNTER(x)			(((x) & BIT_MASK_ABORT_RX_VBON_COUNTER) << BIT_SHIFT_ABORT_RX_VBON_COUNTER)
#define BITS_ABORT_RX_VBON_COUNTER			(BIT_MASK_ABORT_RX_VBON_COUNTER << BIT_SHIFT_ABORT_RX_VBON_COUNTER)
#define BIT_CLEAR_ABORT_RX_VBON_COUNTER(x)		((x) & (~BITS_ABORT_RX_VBON_COUNTER))
#define BIT_GET_ABORT_RX_VBON_COUNTER(x)		(((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) & BIT_MASK_ABORT_RX_VBON_COUNTER)
#define BIT_SET_ABORT_RX_VBON_COUNTER(x, v)		(BIT_CLEAR_ABORT_RX_VBON_COUNTER(x) | BIT_ABORT_RX_VBON_COUNTER(v))

#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER		8
#define BIT_MASK_ABORT_RX_RDRDY_COUNTER		0xff
#define BIT_ABORT_RX_RDRDY_COUNTER(x)			(((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER)
#define BITS_ABORT_RX_RDRDY_COUNTER			(BIT_MASK_ABORT_RX_RDRDY_COUNTER << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER)
#define BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x)		((x) & (~BITS_ABORT_RX_RDRDY_COUNTER))
#define BIT_GET_ABORT_RX_RDRDY_COUNTER(x)		(((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) & BIT_MASK_ABORT_RX_RDRDY_COUNTER)
#define BIT_SET_ABORT_RX_RDRDY_COUNTER(x, v)		(BIT_CLEAR_ABORT_RX_RDRDY_COUNTER(x) | BIT_ABORT_RX_RDRDY_COUNTER(v))

#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER		0
#define BIT_MASK_VBON_EARLY_FALLING_COUNTER		0xff
#define BIT_VBON_EARLY_FALLING_COUNTER(x)		(((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER)
#define BITS_VBON_EARLY_FALLING_COUNTER		(BIT_MASK_VBON_EARLY_FALLING_COUNTER << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER)
#define BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x)	((x) & (~BITS_VBON_EARLY_FALLING_COUNTER))
#define BIT_GET_VBON_EARLY_FALLING_COUNTER(x)		(((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) & BIT_MASK_VBON_EARLY_FALLING_COUNTER)
#define BIT_SET_VBON_EARLY_FALLING_COUNTER(x, v)	(BIT_CLEAR_VBON_EARLY_FALLING_COUNTER(x) | BIT_VBON_EARLY_FALLING_COUNTER(v))

/* 2 REG_WMAC_PLCP_MONITOR			(Offset 0x1694) */

#define BIT_WMAC_PLCP_TRX_SEL				BIT(31)

#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL			28
#define BIT_MASK_WMAC_PLCP_RDSIG_SEL			0x7
#define BIT_WMAC_PLCP_RDSIG_SEL(x)			(((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL)
#define BITS_WMAC_PLCP_RDSIG_SEL			(BIT_MASK_WMAC_PLCP_RDSIG_SEL << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL)
#define BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x)		((x) & (~BITS_WMAC_PLCP_RDSIG_SEL))
#define BIT_GET_WMAC_PLCP_RDSIG_SEL(x)			(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL)
#define BIT_SET_WMAC_PLCP_RDSIG_SEL(x, v)		(BIT_CLEAR_WMAC_PLCP_RDSIG_SEL(x) | BIT_WMAC_PLCP_RDSIG_SEL(v))

#define BIT_SHIFT_WMAC_RATE_IDX			24
#define BIT_MASK_WMAC_RATE_IDX				0xf
#define BIT_WMAC_RATE_IDX(x)				(((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX)
#define BITS_WMAC_RATE_IDX				(BIT_MASK_WMAC_RATE_IDX << BIT_SHIFT_WMAC_RATE_IDX)
#define BIT_CLEAR_WMAC_RATE_IDX(x)			((x) & (~BITS_WMAC_RATE_IDX))
#define BIT_GET_WMAC_RATE_IDX(x)			(((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX)
#define BIT_SET_WMAC_RATE_IDX(x, v)			(BIT_CLEAR_WMAC_RATE_IDX(x) | BIT_WMAC_RATE_IDX(v))

#define BIT_SHIFT_WMAC_PLCP_RDSIG			0
#define BIT_MASK_WMAC_PLCP_RDSIG			0xffffff
#define BIT_WMAC_PLCP_RDSIG(x)				(((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG)
#define BITS_WMAC_PLCP_RDSIG				(BIT_MASK_WMAC_PLCP_RDSIG << BIT_SHIFT_WMAC_PLCP_RDSIG)
#define BIT_CLEAR_WMAC_PLCP_RDSIG(x)			((x) & (~BITS_WMAC_PLCP_RDSIG))
#define BIT_GET_WMAC_PLCP_RDSIG(x)			(((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG)
#define BIT_SET_WMAC_PLCP_RDSIG(x, v)			(BIT_CLEAR_WMAC_PLCP_RDSIG(x) | BIT_WMAC_PLCP_RDSIG(v))

/* 2 REG_WMAC_CSIDMA_CFG			(Offset 0x169C) */

#define BIT_SHIFT_CSI_SEG_SIZE				16
#define BIT_MASK_CSI_SEG_SIZE				0xfff
#define BIT_CSI_SEG_SIZE(x)				(((x) & BIT_MASK_CSI_SEG_SIZE) << BIT_SHIFT_CSI_SEG_SIZE)
#define BITS_CSI_SEG_SIZE				(BIT_MASK_CSI_SEG_SIZE << BIT_SHIFT_CSI_SEG_SIZE)
#define BIT_CLEAR_CSI_SEG_SIZE(x)			((x) & (~BITS_CSI_SEG_SIZE))
#define BIT_GET_CSI_SEG_SIZE(x)			(((x) >> BIT_SHIFT_CSI_SEG_SIZE) & BIT_MASK_CSI_SEG_SIZE)
#define BIT_SET_CSI_SEG_SIZE(x, v)			(BIT_CLEAR_CSI_SEG_SIZE(x) | BIT_CSI_SEG_SIZE(v))

#define BIT_SHIFT_CSI_START_PAGE			0
#define BIT_MASK_CSI_START_PAGE			0xfff
#define BIT_CSI_START_PAGE(x)				(((x) & BIT_MASK_CSI_START_PAGE) << BIT_SHIFT_CSI_START_PAGE)
#define BITS_CSI_START_PAGE				(BIT_MASK_CSI_START_PAGE << BIT_SHIFT_CSI_START_PAGE)
#define BIT_CLEAR_CSI_START_PAGE(x)			((x) & (~BITS_CSI_START_PAGE))
#define BIT_GET_CSI_START_PAGE(x)			(((x) >> BIT_SHIFT_CSI_START_PAGE) & BIT_MASK_CSI_START_PAGE)
#define BIT_SET_CSI_START_PAGE(x, v)			(BIT_CLEAR_CSI_START_PAGE(x) | BIT_CSI_START_PAGE(v))

/* 2 REG_TRANSMIT_ADDRSS_0			(Offset 0x16A0) */

#define BIT_SHIFT_TA0_V1				0
#define BIT_MASK_TA0_V1				0xffffffffL
#define BIT_TA0_V1(x)					(((x) & BIT_MASK_TA0_V1) << BIT_SHIFT_TA0_V1)
#define BITS_TA0_V1					(BIT_MASK_TA0_V1 << BIT_SHIFT_TA0_V1)
#define BIT_CLEAR_TA0_V1(x)				((x) & (~BITS_TA0_V1))
#define BIT_GET_TA0_V1(x)				(((x) >> BIT_SHIFT_TA0_V1) & BIT_MASK_TA0_V1)
#define BIT_SET_TA0_V1(x, v)				(BIT_CLEAR_TA0_V1(x) | BIT_TA0_V1(v))

/* 2 REG_TRANSMIT_ADDRSS_0_H			(Offset 0x16A4) */

#define BIT_SHIFT_TA0_H_V1				0
#define BIT_MASK_TA0_H_V1				0xffff
#define BIT_TA0_H_V1(x)				(((x) & BIT_MASK_TA0_H_V1) << BIT_SHIFT_TA0_H_V1)
#define BITS_TA0_H_V1					(BIT_MASK_TA0_H_V1 << BIT_SHIFT_TA0_H_V1)
#define BIT_CLEAR_TA0_H_V1(x)				((x) & (~BITS_TA0_H_V1))
#define BIT_GET_TA0_H_V1(x)				(((x) >> BIT_SHIFT_TA0_H_V1) & BIT_MASK_TA0_H_V1)
#define BIT_SET_TA0_H_V1(x, v)				(BIT_CLEAR_TA0_H_V1(x) | BIT_TA0_H_V1(v))

/* 2 REG_TRANSMIT_ADDRSS_1			(Offset 0x16A8) */

#define BIT_SHIFT_TA1_V1				0
#define BIT_MASK_TA1_V1				0xffffffffL
#define BIT_TA1_V1(x)					(((x) & BIT_MASK_TA1_V1) << BIT_SHIFT_TA1_V1)
#define BITS_TA1_V1					(BIT_MASK_TA1_V1 << BIT_SHIFT_TA1_V1)
#define BIT_CLEAR_TA1_V1(x)				((x) & (~BITS_TA1_V1))
#define BIT_GET_TA1_V1(x)				(((x) >> BIT_SHIFT_TA1_V1) & BIT_MASK_TA1_V1)
#define BIT_SET_TA1_V1(x, v)				(BIT_CLEAR_TA1_V1(x) | BIT_TA1_V1(v))

/* 2 REG_TRANSMIT_ADDRSS_1_H			(Offset 0x16AC) */

#define BIT_SHIFT_TA1_H_V1				0
#define BIT_MASK_TA1_H_V1				0xffff
#define BIT_TA1_H_V1(x)				(((x) & BIT_MASK_TA1_H_V1) << BIT_SHIFT_TA1_H_V1)
#define BITS_TA1_H_V1					(BIT_MASK_TA1_H_V1 << BIT_SHIFT_TA1_H_V1)
#define BIT_CLEAR_TA1_H_V1(x)				((x) & (~BITS_TA1_H_V1))
#define BIT_GET_TA1_H_V1(x)				(((x) >> BIT_SHIFT_TA1_H_V1) & BIT_MASK_TA1_H_V1)
#define BIT_SET_TA1_H_V1(x, v)				(BIT_CLEAR_TA1_H_V1(x) | BIT_TA1_H_V1(v))

#define BIT_SHIFT_TA2_V1				0
#define BIT_MASK_TA2_V1				0xffffffffL
#define BIT_TA2_V1(x)					(((x) & BIT_MASK_TA2_V1) << BIT_SHIFT_TA2_V1)
#define BITS_TA2_V1					(BIT_MASK_TA2_V1 << BIT_SHIFT_TA2_V1)
#define BIT_CLEAR_TA2_V1(x)				((x) & (~BITS_TA2_V1))
#define BIT_GET_TA2_V1(x)				(((x) >> BIT_SHIFT_TA2_V1) & BIT_MASK_TA2_V1)
#define BIT_SET_TA2_V1(x, v)				(BIT_CLEAR_TA2_V1(x) | BIT_TA2_V1(v))

/* 2 REG_TRANSMIT_ADDRSS_2_H			(Offset 0x16B4) */

#define BIT_SHIFT_TA2_H_V1				0
#define BIT_MASK_TA2_H_V1				0xffff
#define BIT_TA2_H_V1(x)				(((x) & BIT_MASK_TA2_H_V1) << BIT_SHIFT_TA2_H_V1)
#define BITS_TA2_H_V1					(BIT_MASK_TA2_H_V1 << BIT_SHIFT_TA2_H_V1)
#define BIT_CLEAR_TA2_H_V1(x)				((x) & (~BITS_TA2_H_V1))
#define BIT_GET_TA2_H_V1(x)				(((x) >> BIT_SHIFT_TA2_H_V1) & BIT_MASK_TA2_H_V1)
#define BIT_SET_TA2_H_V1(x, v)				(BIT_CLEAR_TA2_H_V1(x) | BIT_TA2_H_V1(v))

/* 2 REG_TRANSMIT_ADDRSS_3_H			(Offset 0x16BC) */

#define BIT_SHIFT_TA3_H_V1				0
#define BIT_MASK_TA3_H_V1				0xffff
#define BIT_TA3_H_V1(x)				(((x) & BIT_MASK_TA3_H_V1) << BIT_SHIFT_TA3_H_V1)
#define BITS_TA3_H_V1					(BIT_MASK_TA3_H_V1 << BIT_SHIFT_TA3_H_V1)
#define BIT_CLEAR_TA3_H_V1(x)				((x) & (~BITS_TA3_H_V1))
#define BIT_GET_TA3_H_V1(x)				(((x) >> BIT_SHIFT_TA3_H_V1) & BIT_MASK_TA3_H_V1)
#define BIT_SET_TA3_H_V1(x, v)				(BIT_CLEAR_TA3_H_V1(x) | BIT_TA3_H_V1(v))

/* 2 REG_TRANSMIT_ADDRSS_4			(Offset 0x16C0) */

#define BIT_SHIFT_TA4_V1				0
#define BIT_MASK_TA4_V1				0xffffffffL
#define BIT_TA4_V1(x)					(((x) & BIT_MASK_TA4_V1) << BIT_SHIFT_TA4_V1)
#define BITS_TA4_V1					(BIT_MASK_TA4_V1 << BIT_SHIFT_TA4_V1)
#define BIT_CLEAR_TA4_V1(x)				((x) & (~BITS_TA4_V1))
#define BIT_GET_TA4_V1(x)				(((x) >> BIT_SHIFT_TA4_V1) & BIT_MASK_TA4_V1)
#define BIT_SET_TA4_V1(x, v)				(BIT_CLEAR_TA4_V1(x) | BIT_TA4_V1(v))

/* 2 REG_TRANSMIT_ADDRSS_4_H			(Offset 0x16C4) */

#define BIT_SHIFT_TA4_H_V1				0
#define BIT_MASK_TA4_H_V1				0xffff
#define BIT_TA4_H_V1(x)				(((x) & BIT_MASK_TA4_H_V1) << BIT_SHIFT_TA4_H_V1)
#define BITS_TA4_H_V1					(BIT_MASK_TA4_H_V1 << BIT_SHIFT_TA4_H_V1)
#define BIT_CLEAR_TA4_H_V1(x)				((x) & (~BITS_TA4_H_V1))
#define BIT_GET_TA4_H_V1(x)				(((x) >> BIT_SHIFT_TA4_H_V1) & BIT_MASK_TA4_H_V1)
#define BIT_SET_TA4_H_V1(x, v)				(BIT_CLEAR_TA4_H_V1(x) | BIT_TA4_H_V1(v))

#endif

#endif/* __RTL_WLAN_BITDEF_H__ */
